1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_hsi_dma_channels.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_hsi_dma_channels msbfirst ( addr base ) "" { 29 30 31 constants dst_add_mode_status width(2) "" { 32 DST_ADD_MODE_0 = 0 "constant address"; 33 DST_ADD_MODE_1 = 1 "post increment address"; 34 }; 35 36 constants enable_status width(1) "" { 37 ENABLE_0 = 0 "transfer stops and is reset"; 38 ENABLE_1 = 1 "transfer is enabled. Automatically cleared by hardware once transfer is finished"; 39 }; 40 41 constants dst_burst_en_status width(2) "" { 42 DST_BURST_EN_0 = 0 "single access"; 43 DST_BURST_EN_1 = 1 "single access"; 44 DST_BURST_EN_3 = 3 "burst 8x32 bits (not implemented)"; 45 DST_BURST_EN_2 = 2 "burst 4x32 bits"; 46 }; 47 48 constants dst_status width(4) "" { 49 DST_8 = 8 "Transfer to Memory port"; 50 DST_9 = 9 "Transfer to Peripheral port"; 51 }; 52 53 constants src_status width(4) "" { 54 SRC_8 = 8 "Transfer From Memory port"; 55 SRC_9 = 9 "Transfer From Peripheral port"; 56 }; 57 58 register dma_ccr_csdp_i_0 addr(base, 0x0) "Stores source and destination parameters and channel control bits" { 59 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 60 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 61 _ 4 mbz; 62 enable 1 rw type(enable_status) "Logical channel enable"; 63 _ 7 mbz; 64 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 65 _ 1 mbz; 66 dst 4 rw type(dst_status) "Transfer destination"; 67 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 68 _ 1 mbz; 69 src 4 rw type(src_status) "Transfer source"; 70 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 71 }; 72 73 register dma_ccr_csdp_i_1 addr(base, 0x40) "Stores source and destination parameters and channel control bits" { 74 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 75 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 76 _ 4 mbz; 77 enable 1 rw type(enable_status) "Logical channel enable"; 78 _ 7 mbz; 79 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 80 _ 1 mbz; 81 dst 4 rw type(dst_status) "Transfer destination"; 82 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 83 _ 1 mbz; 84 src 4 rw type(src_status) "Transfer source"; 85 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 86 }; 87 88 register dma_ccr_csdp_i_2 addr(base, 0x80) "Stores source and destination parameters and channel control bits" { 89 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 90 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 91 _ 4 mbz; 92 enable 1 rw type(enable_status) "Logical channel enable"; 93 _ 7 mbz; 94 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 95 _ 1 mbz; 96 dst 4 rw type(dst_status) "Transfer destination"; 97 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 98 _ 1 mbz; 99 src 4 rw type(src_status) "Transfer source"; 100 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 101 }; 102 103 register dma_ccr_csdp_i_3 addr(base, 0xC0) "Stores source and destination parameters and channel control bits" { 104 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 105 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 106 _ 4 mbz; 107 enable 1 rw type(enable_status) "Logical channel enable"; 108 _ 7 mbz; 109 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 110 _ 1 mbz; 111 dst 4 rw type(dst_status) "Transfer destination"; 112 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 113 _ 1 mbz; 114 src 4 rw type(src_status) "Transfer source"; 115 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 116 }; 117 118 register dma_ccr_csdp_i_4 addr(base, 0x100) "Stores source and destination parameters and channel control bits" { 119 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 120 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 121 _ 4 mbz; 122 enable 1 rw type(enable_status) "Logical channel enable"; 123 _ 7 mbz; 124 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 125 _ 1 mbz; 126 dst 4 rw type(dst_status) "Transfer destination"; 127 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 128 _ 1 mbz; 129 src 4 rw type(src_status) "Transfer source"; 130 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 131 }; 132 133 register dma_ccr_csdp_i_5 addr(base, 0x140) "Stores source and destination parameters and channel control bits" { 134 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 135 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 136 _ 4 mbz; 137 enable 1 rw type(enable_status) "Logical channel enable"; 138 _ 7 mbz; 139 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 140 _ 1 mbz; 141 dst 4 rw type(dst_status) "Transfer destination"; 142 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 143 _ 1 mbz; 144 src 4 rw type(src_status) "Transfer source"; 145 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 146 }; 147 148 register dma_ccr_csdp_i_6 addr(base, 0x180) "Stores source and destination parameters and channel control bits" { 149 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 150 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 151 _ 4 mbz; 152 enable 1 rw type(enable_status) "Logical channel enable"; 153 _ 7 mbz; 154 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 155 _ 1 mbz; 156 dst 4 rw type(dst_status) "Transfer destination"; 157 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 158 _ 1 mbz; 159 src 4 rw type(src_status) "Transfer source"; 160 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 161 }; 162 163 register dma_ccr_csdp_i_7 addr(base, 0x1C0) "Stores source and destination parameters and channel control bits" { 164 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 165 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 166 _ 4 mbz; 167 enable 1 rw type(enable_status) "Logical channel enable"; 168 _ 7 mbz; 169 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 170 _ 1 mbz; 171 dst 4 rw type(dst_status) "Transfer destination"; 172 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 173 _ 1 mbz; 174 src 4 rw type(src_status) "Transfer source"; 175 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 176 }; 177 178 register dma_ccr_csdp_i_8 addr(base, 0x200) "Stores source and destination parameters and channel control bits" { 179 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 180 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 181 _ 4 mbz; 182 enable 1 rw type(enable_status) "Logical channel enable"; 183 _ 7 mbz; 184 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 185 _ 1 mbz; 186 dst 4 rw type(dst_status) "Transfer destination"; 187 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 188 _ 1 mbz; 189 src 4 rw type(src_status) "Transfer source"; 190 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 191 }; 192 193 register dma_ccr_csdp_i_9 addr(base, 0x240) "Stores source and destination parameters and channel control bits" { 194 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 195 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 196 _ 4 mbz; 197 enable 1 rw type(enable_status) "Logical channel enable"; 198 _ 7 mbz; 199 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 200 _ 1 mbz; 201 dst 4 rw type(dst_status) "Transfer destination"; 202 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 203 _ 1 mbz; 204 src 4 rw type(src_status) "Transfer source"; 205 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 206 }; 207 208 register dma_ccr_csdp_i_10 addr(base, 0x280) "Stores source and destination parameters and channel control bits" { 209 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 210 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 211 _ 4 mbz; 212 enable 1 rw type(enable_status) "Logical channel enable"; 213 _ 7 mbz; 214 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 215 _ 1 mbz; 216 dst 4 rw type(dst_status) "Transfer destination"; 217 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 218 _ 1 mbz; 219 src 4 rw type(src_status) "Transfer source"; 220 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 221 }; 222 223 register dma_ccr_csdp_i_11 addr(base, 0x2C0) "Stores source and destination parameters and channel control bits" { 224 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 225 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 226 _ 4 mbz; 227 enable 1 rw type(enable_status) "Logical channel enable"; 228 _ 7 mbz; 229 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 230 _ 1 mbz; 231 dst 4 rw type(dst_status) "Transfer destination"; 232 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 233 _ 1 mbz; 234 src 4 rw type(src_status) "Transfer source"; 235 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 236 }; 237 238 register dma_ccr_csdp_i_12 addr(base, 0x300) "Stores source and destination parameters and channel control bits" { 239 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 240 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 241 _ 4 mbz; 242 enable 1 rw type(enable_status) "Logical channel enable"; 243 _ 7 mbz; 244 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 245 _ 1 mbz; 246 dst 4 rw type(dst_status) "Transfer destination"; 247 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 248 _ 1 mbz; 249 src 4 rw type(src_status) "Transfer source"; 250 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 251 }; 252 253 register dma_ccr_csdp_i_13 addr(base, 0x340) "Stores source and destination parameters and channel control bits" { 254 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 255 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 256 _ 4 mbz; 257 enable 1 rw type(enable_status) "Logical channel enable"; 258 _ 7 mbz; 259 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 260 _ 1 mbz; 261 dst 4 rw type(dst_status) "Transfer destination"; 262 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 263 _ 1 mbz; 264 src 4 rw type(src_status) "Transfer source"; 265 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 266 }; 267 268 register dma_ccr_csdp_i_14 addr(base, 0x380) "Stores source and destination parameters and channel control bits" { 269 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 270 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 271 _ 4 mbz; 272 enable 1 rw type(enable_status) "Logical channel enable"; 273 _ 7 mbz; 274 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 275 _ 1 mbz; 276 dst 4 rw type(dst_status) "Transfer destination"; 277 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 278 _ 1 mbz; 279 src 4 rw type(src_status) "Transfer source"; 280 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 281 }; 282 283 register dma_ccr_csdp_i_15 addr(base, 0x3C0) "Stores source and destination parameters and channel control bits" { 284 dst_add_mode 2 rw type(dst_add_mode_status) "Destination addressing mode"; 285 src_add_mode 2 rw type(dst_add_mode_status) "Source addressing mode"; 286 _ 4 mbz; 287 enable 1 rw type(enable_status) "Logical channel enable"; 288 _ 7 mbz; 289 dst_burst_en 2 rw type(dst_burst_en_status) "Destination burst enable"; 290 _ 1 mbz; 291 dst 4 rw type(dst_status) "Transfer destination"; 292 src_burst_en 2 rw type(dst_burst_en_status) "Source burst enable"; 293 _ 1 mbz; 294 src 4 rw type(src_status) "Transfer source"; 295 data_type 2 rw "Defines data typesImplemented bitfield but not used"; 296 }; 297 298 constants block_is_status width(1) "" { 299 BLOCK_IS_1_r = 1 "block transferred"; 300 BLOCK_IS_0_r = 0 "no event"; 301 }; 302 303 constants half_is_status width(1) "" { 304 HALF_IS_1_r = 1 "half block transferred"; 305 HALF_IS_0_r = 0 "no event"; 306 }; 307 308 constants tout_is_status width(1) "" { 309 TOUT_IS_1_r = 1 "time-out occurred"; 310 TOUT_IS_0_r = 0 "no event"; 311 }; 312 313 constants block_ie_status width(1) "" { 314 BLOCK_IE_0 = 0 "no interrupt"; 315 BLOCK_IE_1 = 1 "interrupt enable"; 316 }; 317 318 register dma_csr_ccir_i_0 addr(base, 0x4) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 319 _ 10 mbz; 320 block_is 1 ro type(block_is_status) "Block transferred"; 321 _ 2 mbz; 322 half_is 1 ro type(half_is_status) "Half block reached"; 323 _ 1 mbz; 324 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 325 _ 10 mbz; 326 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 327 _ 2 mbz; 328 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 329 _ 1 mbz; 330 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 331 }; 332 333 register dma_csr_ccir_i_1 addr(base, 0x44) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 334 _ 10 mbz; 335 block_is 1 ro type(block_is_status) "Block transferred"; 336 _ 2 mbz; 337 half_is 1 ro type(half_is_status) "Half block reached"; 338 _ 1 mbz; 339 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 340 _ 10 mbz; 341 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 342 _ 2 mbz; 343 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 344 _ 1 mbz; 345 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 346 }; 347 348 register dma_csr_ccir_i_2 addr(base, 0x84) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 349 _ 10 mbz; 350 block_is 1 ro type(block_is_status) "Block transferred"; 351 _ 2 mbz; 352 half_is 1 ro type(half_is_status) "Half block reached"; 353 _ 1 mbz; 354 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 355 _ 10 mbz; 356 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 357 _ 2 mbz; 358 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 359 _ 1 mbz; 360 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 361 }; 362 363 register dma_csr_ccir_i_3 addr(base, 0xC4) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 364 _ 10 mbz; 365 block_is 1 ro type(block_is_status) "Block transferred"; 366 _ 2 mbz; 367 half_is 1 ro type(half_is_status) "Half block reached"; 368 _ 1 mbz; 369 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 370 _ 10 mbz; 371 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 372 _ 2 mbz; 373 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 374 _ 1 mbz; 375 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 376 }; 377 378 register dma_csr_ccir_i_4 addr(base, 0x104) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 379 _ 10 mbz; 380 block_is 1 ro type(block_is_status) "Block transferred"; 381 _ 2 mbz; 382 half_is 1 ro type(half_is_status) "Half block reached"; 383 _ 1 mbz; 384 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 385 _ 10 mbz; 386 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 387 _ 2 mbz; 388 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 389 _ 1 mbz; 390 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 391 }; 392 393 register dma_csr_ccir_i_5 addr(base, 0x144) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 394 _ 10 mbz; 395 block_is 1 ro type(block_is_status) "Block transferred"; 396 _ 2 mbz; 397 half_is 1 ro type(half_is_status) "Half block reached"; 398 _ 1 mbz; 399 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 400 _ 10 mbz; 401 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 402 _ 2 mbz; 403 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 404 _ 1 mbz; 405 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 406 }; 407 408 register dma_csr_ccir_i_6 addr(base, 0x184) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 409 _ 10 mbz; 410 block_is 1 ro type(block_is_status) "Block transferred"; 411 _ 2 mbz; 412 half_is 1 ro type(half_is_status) "Half block reached"; 413 _ 1 mbz; 414 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 415 _ 10 mbz; 416 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 417 _ 2 mbz; 418 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 419 _ 1 mbz; 420 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 421 }; 422 423 register dma_csr_ccir_i_7 addr(base, 0x1C4) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 424 _ 10 mbz; 425 block_is 1 ro type(block_is_status) "Block transferred"; 426 _ 2 mbz; 427 half_is 1 ro type(half_is_status) "Half block reached"; 428 _ 1 mbz; 429 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 430 _ 10 mbz; 431 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 432 _ 2 mbz; 433 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 434 _ 1 mbz; 435 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 436 }; 437 438 register dma_csr_ccir_i_8 addr(base, 0x204) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 439 _ 10 mbz; 440 block_is 1 ro type(block_is_status) "Block transferred"; 441 _ 2 mbz; 442 half_is 1 ro type(half_is_status) "Half block reached"; 443 _ 1 mbz; 444 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 445 _ 10 mbz; 446 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 447 _ 2 mbz; 448 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 449 _ 1 mbz; 450 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 451 }; 452 453 register dma_csr_ccir_i_9 addr(base, 0x244) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 454 _ 10 mbz; 455 block_is 1 ro type(block_is_status) "Block transferred"; 456 _ 2 mbz; 457 half_is 1 ro type(half_is_status) "Half block reached"; 458 _ 1 mbz; 459 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 460 _ 10 mbz; 461 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 462 _ 2 mbz; 463 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 464 _ 1 mbz; 465 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 466 }; 467 468 register dma_csr_ccir_i_10 addr(base, 0x284) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 469 _ 10 mbz; 470 block_is 1 ro type(block_is_status) "Block transferred"; 471 _ 2 mbz; 472 half_is 1 ro type(half_is_status) "Half block reached"; 473 _ 1 mbz; 474 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 475 _ 10 mbz; 476 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 477 _ 2 mbz; 478 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 479 _ 1 mbz; 480 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 481 }; 482 483 register dma_csr_ccir_i_11 addr(base, 0x2C4) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 484 _ 10 mbz; 485 block_is 1 ro type(block_is_status) "Block transferred"; 486 _ 2 mbz; 487 half_is 1 ro type(half_is_status) "Half block reached"; 488 _ 1 mbz; 489 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 490 _ 10 mbz; 491 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 492 _ 2 mbz; 493 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 494 _ 1 mbz; 495 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 496 }; 497 498 register dma_csr_ccir_i_12 addr(base, 0x304) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 499 _ 10 mbz; 500 block_is 1 ro type(block_is_status) "Block transferred"; 501 _ 2 mbz; 502 half_is 1 ro type(half_is_status) "Half block reached"; 503 _ 1 mbz; 504 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 505 _ 10 mbz; 506 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 507 _ 2 mbz; 508 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 509 _ 1 mbz; 510 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 511 }; 512 513 register dma_csr_ccir_i_13 addr(base, 0x344) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 514 _ 10 mbz; 515 block_is 1 ro type(block_is_status) "Block transferred"; 516 _ 2 mbz; 517 half_is 1 ro type(half_is_status) "Half block reached"; 518 _ 1 mbz; 519 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 520 _ 10 mbz; 521 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 522 _ 2 mbz; 523 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 524 _ 1 mbz; 525 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 526 }; 527 528 register dma_csr_ccir_i_14 addr(base, 0x384) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 529 _ 10 mbz; 530 block_is 1 ro type(block_is_status) "Block transferred"; 531 _ 2 mbz; 532 half_is 1 ro type(half_is_status) "Half block reached"; 533 _ 1 mbz; 534 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 535 _ 10 mbz; 536 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 537 _ 2 mbz; 538 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 539 _ 1 mbz; 540 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 541 }; 542 543 register dma_csr_ccir_i_15 addr(base, 0x3C4) "Interrupt enable and status registerInterrupt flag fields will be cleared through read access using the following byteenable values:0xC0xF" { 544 _ 10 mbz; 545 block_is 1 ro type(block_is_status) "Block transferred"; 546 _ 2 mbz; 547 half_is 1 ro type(half_is_status) "Half block reached"; 548 _ 1 mbz; 549 tout_is 1 ro type(tout_is_status) "Time-out overflow event"; 550 _ 10 mbz; 551 block_ie 1 rw type(block_ie_status) "Interrupt is sent when a full block is transferred"; 552 _ 2 mbz; 553 half_ie 1 rw type(block_ie_status) "Interrupt is sent when a half block is transferred"; 554 _ 1 mbz; 555 tout_ie 1 rw type(block_ie_status) "Interrupt is sent when a time-out overflow occurs"; 556 }; 557 558 register dma_cssa_i_0 rw addr(base, 0x8) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 559 560 register dma_cssa_i_1 rw addr(base, 0x48) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 561 562 register dma_cssa_i_2 rw addr(base, 0x88) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 563 564 register dma_cssa_i_3 rw addr(base, 0xC8) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 565 566 register dma_cssa_i_4 rw addr(base, 0x108) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 567 568 register dma_cssa_i_5 rw addr(base, 0x148) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 569 570 register dma_cssa_i_6 rw addr(base, 0x188) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 571 572 register dma_cssa_i_7 rw addr(base, 0x1C8) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 573 574 register dma_cssa_i_8 rw addr(base, 0x208) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 575 576 register dma_cssa_i_9 rw addr(base, 0x248) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 577 578 register dma_cssa_i_10 rw addr(base, 0x288) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 579 580 register dma_cssa_i_11 rw addr(base, 0x2C8) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 581 582 register dma_cssa_i_12 rw addr(base, 0x308) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 583 584 register dma_cssa_i_13 rw addr(base, 0x348) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 585 586 register dma_cssa_i_14 rw addr(base, 0x388) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 587 588 register dma_cssa_i_15 rw addr(base, 0x3C8) "Stores source start addressIf the transfer configured from memory port all bits are taken into account as an address,if the transfer configured from peripheral port the lower four bits will determine the FIFO ID." type(uint32); 589 590 register dma_cdsa_i_0 rw addr(base, 0xC) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 591 592 register dma_cdsa_i_1 rw addr(base, 0x4C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 593 594 register dma_cdsa_i_2 rw addr(base, 0x8C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 595 596 register dma_cdsa_i_3 rw addr(base, 0xCC) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 597 598 register dma_cdsa_i_4 rw addr(base, 0x10C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 599 600 register dma_cdsa_i_5 rw addr(base, 0x14C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 601 602 register dma_cdsa_i_6 rw addr(base, 0x18C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 603 604 register dma_cdsa_i_7 rw addr(base, 0x1CC) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 605 606 register dma_cdsa_i_8 rw addr(base, 0x20C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 607 608 register dma_cdsa_i_9 rw addr(base, 0x24C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 609 610 register dma_cdsa_i_10 rw addr(base, 0x28C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 611 612 register dma_cdsa_i_11 rw addr(base, 0x2CC) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 613 614 register dma_cdsa_i_12 rw addr(base, 0x30C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 615 616 register dma_cdsa_i_13 rw addr(base, 0x34C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 617 618 register dma_cdsa_i_14 rw addr(base, 0x38C) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 619 620 register dma_cdsa_i_15 rw addr(base, 0x3CC) "Stores destination start addressIf the transfer configured to memory port all bits are taken into account as an address,if the transfer configured to peripheral port the lower four bits will determine the FIFO ID." type(uint32); 621 622 register dma_cen_i_0 addr(base, 0x10) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 623 _ 16 mbz; 624 size 16 rw "Number of elements in a block. Max is 65536."; 625 }; 626 627 register dma_cen_i_1 addr(base, 0x50) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 628 _ 16 mbz; 629 size 16 rw "Number of elements in a block. Max is 65536."; 630 }; 631 632 register dma_cen_i_2 addr(base, 0x90) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 633 _ 16 mbz; 634 size 16 rw "Number of elements in a block. Max is 65536."; 635 }; 636 637 register dma_cen_i_3 addr(base, 0xD0) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 638 _ 16 mbz; 639 size 16 rw "Number of elements in a block. Max is 65536."; 640 }; 641 642 register dma_cen_i_4 addr(base, 0x110) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 643 _ 16 mbz; 644 size 16 rw "Number of elements in a block. Max is 65536."; 645 }; 646 647 register dma_cen_i_5 addr(base, 0x150) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 648 _ 16 mbz; 649 size 16 rw "Number of elements in a block. Max is 65536."; 650 }; 651 652 register dma_cen_i_6 addr(base, 0x190) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 653 _ 16 mbz; 654 size 16 rw "Number of elements in a block. Max is 65536."; 655 }; 656 657 register dma_cen_i_7 addr(base, 0x1D0) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 658 _ 16 mbz; 659 size 16 rw "Number of elements in a block. Max is 65536."; 660 }; 661 662 register dma_cen_i_8 addr(base, 0x210) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 663 _ 16 mbz; 664 size 16 rw "Number of elements in a block. Max is 65536."; 665 }; 666 667 register dma_cen_i_9 addr(base, 0x250) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 668 _ 16 mbz; 669 size 16 rw "Number of elements in a block. Max is 65536."; 670 }; 671 672 register dma_cen_i_10 addr(base, 0x290) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 673 _ 16 mbz; 674 size 16 rw "Number of elements in a block. Max is 65536."; 675 }; 676 677 register dma_cen_i_11 addr(base, 0x2D0) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 678 _ 16 mbz; 679 size 16 rw "Number of elements in a block. Max is 65536."; 680 }; 681 682 register dma_cen_i_12 addr(base, 0x310) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 683 _ 16 mbz; 684 size 16 rw "Number of elements in a block. Max is 65536."; 685 }; 686 687 register dma_cen_i_13 addr(base, 0x350) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 688 _ 16 mbz; 689 size 16 rw "Number of elements in a block. Max is 65536."; 690 }; 691 692 register dma_cen_i_14 addr(base, 0x390) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 693 _ 16 mbz; 694 size 16 rw "Number of elements in a block. Max is 65536."; 695 }; 696 697 register dma_cen_i_15 addr(base, 0x3D0) "Stores the number of 4 byte words in a DMA data block. Max is 65536." { 698 _ 16 mbz; 699 size 16 rw "Number of elements in a block. Max is 65536."; 700 }; 701 702 register dma_cdac_csac_i_0 addr(base, 0x18) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 703 address_cdac 16 ro "Destination address"; 704 address_csac 16 ro "Source address"; 705 }; 706 707 register dma_cdac_csac_i_1 addr(base, 0x58) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 708 address_cdac 16 ro "Destination address"; 709 address_csac 16 ro "Source address"; 710 }; 711 712 register dma_cdac_csac_i_2 addr(base, 0x98) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 713 address_cdac 16 ro "Destination address"; 714 address_csac 16 ro "Source address"; 715 }; 716 717 register dma_cdac_csac_i_3 addr(base, 0xD8) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 718 address_cdac 16 ro "Destination address"; 719 address_csac 16 ro "Source address"; 720 }; 721 722 register dma_cdac_csac_i_4 addr(base, 0x118) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 723 address_cdac 16 ro "Destination address"; 724 address_csac 16 ro "Source address"; 725 }; 726 727 register dma_cdac_csac_i_5 addr(base, 0x158) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 728 address_cdac 16 ro "Destination address"; 729 address_csac 16 ro "Source address"; 730 }; 731 732 register dma_cdac_csac_i_6 addr(base, 0x198) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 733 address_cdac 16 ro "Destination address"; 734 address_csac 16 ro "Source address"; 735 }; 736 737 register dma_cdac_csac_i_7 addr(base, 0x1D8) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 738 address_cdac 16 ro "Destination address"; 739 address_csac 16 ro "Source address"; 740 }; 741 742 register dma_cdac_csac_i_8 addr(base, 0x218) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 743 address_cdac 16 ro "Destination address"; 744 address_csac 16 ro "Source address"; 745 }; 746 747 register dma_cdac_csac_i_9 addr(base, 0x258) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 748 address_cdac 16 ro "Destination address"; 749 address_csac 16 ro "Source address"; 750 }; 751 752 register dma_cdac_csac_i_10 addr(base, 0x298) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 753 address_cdac 16 ro "Destination address"; 754 address_csac 16 ro "Source address"; 755 }; 756 757 register dma_cdac_csac_i_11 addr(base, 0x2D8) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 758 address_cdac 16 ro "Destination address"; 759 address_csac 16 ro "Source address"; 760 }; 761 762 register dma_cdac_csac_i_12 addr(base, 0x318) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 763 address_cdac 16 ro "Destination address"; 764 address_csac 16 ro "Source address"; 765 }; 766 767 register dma_cdac_csac_i_13 addr(base, 0x358) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 768 address_cdac 16 ro "Destination address"; 769 address_csac 16 ro "Source address"; 770 }; 771 772 register dma_cdac_csac_i_14 addr(base, 0x398) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 773 address_cdac 16 ro "Destination address"; 774 address_csac 16 ro "Source address"; 775 }; 776 777 register dma_cdac_csac_i_15 addr(base, 0x3D8) "Monitors the progress of DMA transfer, by storing the 16-bit counter address for source and destination." { 778 address_cdac 16 ro "Destination address"; 779 address_csac 16 ro "Source address"; 780 }; 781};