1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_gptimer2_l4interconnect.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_gptimer2_l4interconnect msbfirst ( addr base ) "" {
29    
30    
31    register gpt_tidr ro addr(base, 0x0) "This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." type(uint32);
32
33    constants clockactivity_status width(2) "" {
34        CLOCKACTIVITY_0 = 0 "Functional clock can be switched-off ; L4 clock can be switched-off.";
35        CLOCKACTIVITY_1 = 1 "Functional clock can be switched-off ; L4 clock is maintained during wake-up period.";
36        CLOCKACTIVITY_2 = 2 "Functional clock is maintained during wake-up period; L4 clock can be switched-off.";
37        CLOCKACTIVITY_3 = 3 "Functional clock is maintained during wake-up period; L4 clock is maintained during wake-up period.";
38    };
39
40    constants emufree_status width(1) "" {
41        EMUFREE_0 = 0 "Timer counter frozen in emulation";
42        EMUFREE_1 = 1 "Timer counter free-running in emulation";
43    };
44
45    constants idlemode_status width(2) "" {
46        IDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally.";
47        IDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged.";
48        IDLEMODE_2 = 2 "Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the module.";
49        IDLEMODE_3 = 3 "Reserved, do not use.";
50    };
51
52    constants enawakeup_status width(1) "" {
53        ENAWAKEUP_0 = 0 "No wake-up line assertion in idle mode";
54        ENAWAKEUP_1 = 1 "Wake-up line assertion enabled in smart-idle mode.";
55    };
56
57    constants softreset_status width(1) "" {
58        SOFTRESET_0 = 0 "Normal mode";
59        SOFTRESET_1 = 1 "The module is reset.";
60    };
61
62    constants autoidle_status width(1) "" {
63        AUTOIDLE_0 = 0 "L4 clock is free-running.";
64        AUTOIDLE_1 = 1 "Automatic L4 clock gating strategy is applied, based on the L4 interface activity.";
65    };
66    
67    register gpt1ms_tiocp_cfg addr(base, 0x10) "This register controls the various parameters of the OCP interface." {
68        _ 22 mbz;
69        clockactivity 2 rw type(clockactivity_status) "Clock activity";
70        _ 2 mbz;
71        emufree 1 rw type(emufree_status) "Emulation mode";
72        idlemode 2 rw type(idlemode_status) "Power management, req/ack control";
73        enawakeup 1 rw type(enawakeup_status) "Wake-up feature global control";
74        softreset 1 rw type(softreset_status) "Software reset. This bit is automatically reset by the hardware. During reads, it always returns 0.";
75        autoidle 1 rw type(autoidle_status) "Internal L4 clock gating strategy";
76    };
77
78    constants resetdone_status width(1) "" {
79        RESETDONE_0_r = 0 "Internal module reset in ongoing.";
80        RESETDONE_1_r = 1 "Reset complete";
81    };
82    
83    register gpt_tistat addr(base, 0x14) "This register provides status information about the module, excluding interrupt status information." {
84        _ 31 mbz;
85        resetdone 1 ro type(resetdone_status) "Internal reset monitoring";
86    };
87
88    constants tcar_it_flag_status width(1) "" {
89        TCAR_IT_FLAG_0 = 0 "No capture interrupt request";
90        TCAR_IT_FLAG_1 = 1 "Capture interrupt request";
91    };
92
93    constants ovf_it_flag_status width(1) "" {
94        OVF_IT_FLAG_0 = 0 "No overflow interrupt request";
95        OVF_IT_FLAG_1 = 1 "Overflow interrupt pending";
96    };
97
98    constants mat_it_flag_status width(1) "" {
99        MAT_IT_FLAG_0 = 0 "No compare interrupt request";
100        MAT_IT_FLAG_1 = 1 "Compare interrupt pending";
101    };
102    
103    register gpt_tisr addr(base, 0x18) "The timer status register is used to determine which of the timer events requested an interrupt." {
104        _ 29 mbz;
105        tcar_it_flag 1 rw type(tcar_it_flag_status) "Indicates when an external pulse transition of the correct polarity is detected on external pin GPTi_EVENT_CAPTURE";
106        ovf_it_flag 1 rw type(ovf_it_flag_status) "TCRR overflow";
107        mat_it_flag 1 rw type(mat_it_flag_status) "The compare result of TCRR and TMAR";
108    };
109
110    constants tcar_it_ena_status width(1) "" {
111        TCAR_IT_ENA_0 = 0 "Disable capture interrupt.";
112        TCAR_IT_ENA_1 = 1 "Enable capture interrupt.";
113    };
114
115    constants ovf_it_ena_status width(1) "" {
116        OVF_IT_ENA_0 = 0 "Disable overflow interrupt.";
117        OVF_IT_ENA_1 = 1 "Enable overflow interrupt.";
118    };
119
120    constants mat_it_ena_status width(1) "" {
121        MAT_IT_ENA_0 = 0 "Disable match interrupt.";
122        MAT_IT_ENA_1 = 1 "Enable match interrupt.";
123    };
124    
125    register gpt_tier addr(base, 0x1C) "This register controls (enable/disable) the interrupt events." {
126        _ 29 mbz;
127        tcar_it_ena 1 rw type(tcar_it_ena_status) "Capture interrupt enable";
128        ovf_it_ena 1 rw type(ovf_it_ena_status) "Overflow interrupt enable";
129        mat_it_ena 1 rw type(mat_it_ena_status) "Match interrupt enable";
130    };
131
132    constants tcar_wup_ena_status width(1) "" {
133        TCAR_WUP_ENA_0 = 0 "Disable capture wake-up.";
134        TCAR_WUP_ENA_1 = 1 "Enable capture wake-up.";
135    };
136
137    constants ovf_wup_ena_status width(1) "" {
138        OVF_WUP_ENA_0 = 0 "Disable overflow wake-up.";
139        OVF_WUP_ENA_1 = 1 "Enable overflow wake-up.";
140    };
141
142    constants mat_wup_ena_status width(1) "" {
143        MAT_WUP_ENA_0 = 0 "Disable match wake-up.";
144        MAT_WUP_ENA_1 = 1 "Enable match wake-up.";
145    };
146    
147    register gpt_twer addr(base, 0x20) "This register controls (enable/disable) the wake-up feature on specific interrupt events." {
148        _ 29 mbz;
149        tcar_wup_ena 1 rw type(tcar_wup_ena_status) "Capture wake-up enable";
150        ovf_wup_ena 1 rw type(ovf_wup_ena_status) "Overflow wake-up enable";
151        mat_wup_ena 1 rw type(mat_wup_ena_status) "Match wake-up enable";
152    };
153
154    constants gpo_cfg_status width(1) "" {
155        GPO_CFG_0 = 0 "GPTi_PORGPOCFG drives 0.";
156        GPO_CFG_1 = 1 "GPTi_PORGPOCFG drives 1.";
157    };
158
159    constants capt_mode_status width(1) "" {
160        CAPT_MODE_0 = 0 "Single capture: Capture the first enabled capture event in TCAR1.";
161        CAPT_MODE_1 = 1 "Capture on second event: Capture the second enabled capture event in TCAR2.";
162    };
163
164    constants pt_status width(1) "" {
165        PT_0 = 0 "Pulse modulation";
166        PT_1 = 1 "Toggle modulation";
167    };
168
169    constants trg_status width(2) "" {
170        TRG_0 = 0 "No trigger";
171        TRG_1 = 1 "Trigger on overflow.";
172        TRG_2 = 2 "Trigger on overflow and match.";
173        TRG_3 = 3 "Reserved";
174    };
175
176    constants tcm_status width(2) "" {
177        TCM_0 = 0 "No capture";
178        TCM_1 = 1 "Capture on rising edges of GPTi_EVENT_CAPTURE pin";
179        TCM_2 = 2 "Capture on falling edges of GPTi_EVENT_CAPTURE pin";
180        TCM_3 = 3 "Capture on both edges of GPTi_EVENT_CAPTURE pin";
181    };
182
183    constants ce_status width(1) "" {
184        CE_0 = 0 "Compare mode is disable.";
185        CE_1 = 1 "Compare mode is enable.";
186    };
187
188    constants pre_status width(1) "" {
189        PRE_0 = 0 "The TIMER clock input pin clocks the counter.";
190        PRE_1 = 1 "The divided input pin clocks the counter.";
191    };
192
193    constants ar_status width(1) "" {
194        AR_0 = 0 "One shot timer";
195        AR_1 = 1 "Autoreload timer";
196    };
197
198    constants st_status width(1) "" {
199        ST_0 = 0 "Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed.";
200        ST_1 = 1 "Start timer";
201    };
202    
203    register gpt_tclr addr(base, 0x24) "This register controls optional features specific to the timer functionality." {
204        _ 17 mbz;
205        gpo_cfg 1 rw type(gpo_cfg_status) "General-purpose output - this register directly drives the GPTi_PORGPOCFG output pin. For specific use of the GPO_CFG bit, see, .";
206        capt_mode 1 rw type(capt_mode_status) "Capture mode select bit (first/second)";
207        pt 1 rw type(pt_status) "Pulse or toggle mode on GPTi_PWM_out output pin";
208        trg 2 rw type(trg_status) "Trigger output mode on GPTi_PWM_out output pin";
209        tcm 2 rw type(tcm_status) "Transition capture mode on GPTi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)";
210        scpwm 1 rw type(idlemode_status) "Pulse width modulation output pin default settingThis bit must be set or clear while the timer is stopped or the trigger is off.";
211        ce 1 rw type(ce_status) "Compare enable";
212        pre 1 rw type(pre_status) "Prescaler enable";
213        ptv 3 rw "Prescale clock timer valueThe timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods.";
214        ar 1 rw type(ar_status) "Autoreload mode";
215        st 1 rw type(st_status) "Start/stop timer control";
216    };
217    
218    register gpt_tcrr rw addr(base, 0x28) "This register holds the value of the internal counter." type(uint32);
219    
220    register gpt_tldr rw addr(base, 0x2C) "This register holds the timer load value." type(uint32);
221    
222    register gpt_ttgr rw addr(base, 0x30) "The read value of this register is always 0xFFFF FFFF." type(uint32);
223    
224    register gpt_twps addr(base, 0x34) "This register contains the write posting bits for all writable functional registers." {
225        _ 27 mbz;
226        w_pend_tmar 1 ro "When equal to 1, a write is pending to theGPT_TMAR register.";
227        w_pend_ttgr 1 ro "When equal to 1, a write is pending to theGPT_TTGR register.";
228        w_pend_tldr 1 ro "When equal to 1, a write is pending to theGPT_TLDR register.";
229        w_pend_tcrr 1 ro "When equal to 1, a write is pending to theGPT_TCRR register.";
230        w_pend_tclr 1 ro "When equal to 1, a write is pending to theGPT_TCLR register.";
231    };
232    
233    register gpt_tmar rw addr(base, 0x38) "The compare logic consists of a 32-bit-wide, read/write data TMAR register and logic to compare counter." type(uint32);
234    
235    register gpt_tcar1 ro addr(base, 0x3C) "This register holds the first captured value of the counter register." type(uint32);
236
237    constants posted_status width(1) "" {
238        POSTED_0 = 0 "Posted mode inactive: Delay the command accept output signal.";
239        POSTED_1 = 1 "Posted mode active";
240    };
241
242    constants sft_status width(1) "" {
243        SFT_0 = 0 "Software reset is disabled.";
244        SFT_1 = 1 "Software reset is enabled.";
245    };
246    
247    register gpt_tsicr addr(base, 0x40) "Timer synchronous interface control register" {
248        _ 29 mbz;
249        posted 1 rw type(posted_status) "Posted mode selection";
250        sft 1 rw type(sft_status) "This bit resets all the functional part of the module.";
251        _ 1 mbz;
252    };
253    
254    register gpt_tcar2 ro addr(base, 0x44) "This register holds the second captured value of the counter register." type(uint32);
255    
256    register gpt_tpir rw addr(base, 0x48) "This register is used for 1-ms tick generation. The TPIR register holds the value of the positive increment. The value of this register is added to the value of TCVR to determine whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
257    
258    register gpt_tnir rw addr(base, 0x4C) "This register is used for 1-ms tick generation. The TNIR register holds the value of the negative increment. The value of this register is added to the value of the TCVR to determine whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
259    
260    register gpt_tcvr rw addr(base, 0x50) "This register is used for 1-ms tick generation. The TCVR register determines whether next value loaded in TCRR is the subperiod value or the overperiod value." type(uint32);
261    
262    register gpt_tocr addr(base, 0x54) "This register is used to mask the tick interrupt for a selected number of ticks." {
263        _ 8 mbz;
264        ovf_counter_value 24 rw "Number of overflow events";
265    };
266    
267    register gpt_towr addr(base, 0x58) "This register holds the number of masked overflow interrupts." {
268        _ 8 mbz;
269        ovf_wrapping_value 24 rw "Number of masked interrupts";
270    };
271};