1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_fdif.dev 12 * 13 * DESCRIPTION: Mackerel file for OMAP4 FDIF module. 14 * 15 */ 16 17device omap44xx_fdif msbfirst ( addr base ) "" { 18 19 20 register fdif_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 21 22 register fdif_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." { 23 _ 28 mbz; 24 fdif_tags 4 ro "Hardware design value. This bit field reflects the value of the FDIF_TAG generic parameter. 0x0: 1 tag supported 0x1: 2 tags supported [...] 0xF: 16 tags supported"; 25 }; 26 27 constants standbymode_status width(2) "" { 28 STANDBYMODE_0 = 0 "Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only."; 29 STANDBYMODE_1 = 1 "No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only."; 30 STANDBYMODE_2 = 2 "Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator. IP module shall not generate (initiator-related) wake-up events."; 31 STANDBYMODE_3 = 3 "Reserved"; 32 }; 33 34 constants idlemode_status width(2) "" { 35 IDLEMODE_0 = 0 "Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only."; 36 IDLEMODE_1 = 1 "No-idle mode: local target never enters idle state. Backup mode, for debug only."; 37 IDLEMODE_2 = 2 "Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events."; 38 IDLEMODE_3 = 3 "Reserved"; 39 }; 40 41 constants softreset_status width(1) "" { 42 SOFTRESET_DONE = 0 "Reset done, no pending action"; 43 SOFTRESET_ONGOING = 1 "Reset (software or other) ongoing"; 44 }; 45 46 register fdif_sysconfig addr(base, 0x10) "Clock management configuration" { 47 _ 26 mbz; 48 standbymode 2 rw type(standbymode_status) "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."; 49 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."; 50 _ 1 mbz; 51 softreset 1 rw type(softreset_status) "Software reset."; 52 }; 53 54 constants finish_irq_status width(1) "" { 55 FINISH_IRQ_0 = 0 "No event pending"; 56 FINISH_IRQ_1 = 1 "Event pending"; 57 }; 58 59 regarray fdif_irqstatus_raw addr(base, 0x24)[3;0x10] "Per-event raw interrupt status vector, line #n. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 60 _ 23 mbz; 61 finish_irq 1 rw type(finish_irq_status) "Face detection processing done."; 62 _ 7 mbz; 63 err_irq 1 rw type(finish_irq_status) "Error received by the L3 port."; 64 }; 65 66 67 regarray fdif_irqstatus addr(base, 0x28)[3;0x10] "Per-event 'enabled' interrupt status vector, line #n. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 68 _ 23 mbz; 69 finish_irq 1 rw1c type(finish_irq_status) "Face detection processing done."; 70 _ 7 mbz; 71 err_irq 1 rw1c type(finish_irq_status) "Error received by the L3 port."; 72 }; 73 74 constants finish_irqenable_status width(1) "" { 75 FINISH_IRQ_MASKED = 0 "Interrupt disabled (masked)"; 76 FINISH_IRQ_ENABLED = 1 "Interrupt enabled"; 77 }; 78 79 regarray fdif_irqenable_set addr(base, 0x2C)[3;0x10] "Per-event interrupt enable bit vector, line #n. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 80 _ 23 mbz; 81 finish_irq 1 rw type(finish_irqenable_status) "Face detection processing done."; 82 _ 7 mbz; 83 err_irq 1 rw type(finish_irqenable_status) "Error received by the L3 port."; 84 }; 85 86 constants finish_irq_status3 width(1) "" { 87 FINISH_IRQ_0_r_9 = 0 "Interrupt disabled (masked)"; 88 FINISH_IRQ_1_r_9 = 1 "Interrupt enabled"; 89 }; 90 91 regarray fdif_irqenable_clr addr(base, 0x30)[3;0x10] "Per-event interrupt enable bit vector, line #n. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 92 _ 23 mbz; 93 finish_irq 1 rw1c type(finish_irqenable_status) "Face detection processing done."; 94 _ 7 mbz; 95 err_irq 1 rw1c type(finish_irqenable_status) "Error received by the L3 port."; 96 }; 97 98 register fdif_picaddr addr(base, 0x60) "Picture data store address. The 5 least significant bits are forced to 0." type(uint32); 99 100 constants mstandby_hdshk_status width(1) "" { 101 MSTANDBY_HDSHK_COMPLETE = 0 "Handshaking not completed. Do not initiate traffic on L3."; 102 MSTANDBY_HDSHK_INCOMPLETE = 1 "Handshaking completed. Can safely use the FDIF module."; 103 }; 104 105 constants mstandby_status width(1) "" { 106 MSTANDBY_0 = 0 "Write: Clear MStandby signal. One polls.MSTANDBY_HDSHK = 1 after writing this bit to ensure that the power management handshaking is completed."; 107 MSTANDBY_1 = 1 "Write: Asserts MStandby signal"; 108 }; 109 110 constants wrnp_status width(1) "" { 111 WRNP_0 = 0 "All writes are non posted"; 112 WRNP_1 = 1 "All writes are posted"; 113 }; 114 115 register fdif_ctrl addr(base, 0x64) "" { 116 _ 25 mbz; 117 mstandby_hdshk 1 ro type(mstandby_hdshk_status) "MStandby / Wait power management handshaking status bit The power management framework of the FDIF module is based on the handshaking of the MSTANDBY and WAIT signals. When going from a idle to normal power management transition, the software polls for FDIF_CTRL.MSTANDBY_HDSHK = 1 before starting the face detection processing."; 118 mstandby 1 rw type(mstandby_status) "MStandby signal generation. This bit shall be set to initiate a power management transition from NORMAL to IDLE or IDLE to NORMAL."; 119 max_tags 4 rw "Max interconnect tags. This bit field sets the maximum number of interconnect tags that the module shall use. This number is programmable between 1 (MAX_TAGS = 0) and FDIF_TAGS (MAX_TAGS = FDIF_TAGS - 1). The value of MAX_TAGS is reflected in the FIDIF_HWINFO register setting. This register setting is expected to have impact on performance. It shall be set once at initialization. Higher value will give more bandwidth to the initiator. Lower value will give less bandwidth to the initiator. This value shall be set as low as possible such that other system initiators are not penalized."; 120 wrnp 1 rw type(wrnp_status) "L3 port non-posted write control. Dynamic usage of this feature is not supported. This bit shall be set at initialization and not modified hereafter until the processing is completed. When non-posted writes are used, tags shall be used for best performance (MAX_TAGS > 1)."; 121 }; 122 123 register fdif_wkaddr addr(base, 0x68) "Work area address. The 5 least significant bits are forced to 0." type(uint32); 124 125 constants finish_status width(1) "" { 126 FINISH_INCOMPLETE = 0 "Write: Disable Read: Process incomplete"; 127 FINISH_COMPLETE = 1 "Write: Process complete flag clear Read: Process complete"; 128 }; 129 130 constants run_status width(1) "" { 131 RUN_0 = 0 "Write: Disable Read: No processing"; 132 RUN_1 = 1 "Write: Process start request Read: Processing data"; 133 }; 134 135 constants srst_status width(1) "" { 136 SRST_CANCEL = 0 "Write: Disable Read: Reset cancel"; 137 SRST_UNDER_RESET = 1 "Write: Reset Read: Under reset"; 138 }; 139 140 register fd_ctrl addr(base, 0x80) "Control register Don't set more than 2 bits to '1' at the same time. Otherwise, operations cannot be guaranteed." { 141 _ 29 mbz; 142 finish 1 rw type(finish_status) "Process Completion Flag Clear"; 143 run 1 rw type(run_status) "Process Start Request"; 144 srst 1 rw type(srst_status) "Software Reset This bit shall not be used to reset the FDIF module. Instead, the FDIF_SYSCONFIG[0] SOFTRESET bit shall be used for complete soft reset."; 145 }; 146 147 register fd_dnum addr(base, 0x84) "Face Detection Result Count Register" { 148 _ 26 mbz; 149 dnum 6 ro "Face detection result count. Up to 35 faces can be detected. Number of face(s) detected: 0x0: 0 face detected 0x1: 1 face detected 0x2: 2 faces detected [...] 0x23: 35 faces detected 0x24 to 0x3F: unused"; 150 }; 151 152 constants dir_status width(2) "" { 153 DIR_UP = 0 "Executes only for UP"; 154 DIR_RIGHT = 1 "Executes only for RIGHT"; 155 DIR_LEFT = 2 "Executes only for LEFT"; 156 DIR_3 = 3 "Reserved"; 157 }; 158 159 constants min_status width(2) "" { 160 MIN_20 = 0 "Set the min face size to 20 pixels"; 161 MIN_25 = 1 "Set the min face size to 25 pixels"; 162 MIN_32 = 2 "Set the min face size to 32 pixels"; 163 MIN_40 = 3 "Set the min face size to 40 pixels"; 164 }; 165 166 register fd_dcond addr(base, 0x88) "Detection Condition Setting Register" { 167 _ 28 mbz; 168 dir 2 rw type(dir_status) "Detection direction setting"; 169 min 2 rw type(min_status) "Reserved"; 170 }; 171 172 register fd_startx addr(base, 0x8C) "Detection Area Setting Register: X Start Coordinate." { 173 _ 24 mbz; 174 startx 8 rw "Starting X coordinates Permitted values are 0<=STARTX<=160"; 175 }; 176 177 register fd_starty addr(base, 0x90) "Detection Area Setting Register: Y Start Coordinate." { 178 _ 25 mbz; 179 starty 7 rw "Starting Y coordinates Permitted values are 0<=STARTY<=120"; 180 }; 181 182 register fd_sizex addr(base, 0x94) "Detection Area Setting Register: X Direction Size" { 183 _ 23 mbz; 184 sizex 9 rw "X Direction Size"; 185 }; 186 187 register fd_sizey addr(base, 0x98) "Detection Area Setting Register: Y Direction Size" { 188 _ 24 mbz; 189 sizey 8 rw "Y Direction Size"; 190 }; 191 192 register fd_lhit addr(base, 0x9C) "Threshold Setting Register" { 193 _ 28 mbz; 194 lhit 4 rw "Threshold Permitted values are 0x0 to 0x9"; 195 }; 196 197 regarray fd_centerx addr(base, 0x160)[35;0x10] "Detection Result: X Coordinate. Its value is undefined after reset." { 198 _ 23 rsvd; 199 centerx 9 ro "Face position: center X coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0x13F"; 200 }; 201 202 regarray fd_centery addr(base, 0x164)[35;0x10] "Detection Result: Y Coordinate. Its value is undefined after reset." { 203 _ 24 rsvd; 204 centery 8 ro "Face position: center Y coordinate The coordinates given by (FD_CENTERX_i, FD_CENTERY_i) give the central coordinates of the face position. Permitted values are 0x0 to 0xEF"; 205 }; 206 207 regarray fd_confsize addr(base, 0x168)[35;0x10] "Detection Result: Confidence Level and Size. Its value is undefined after reset." { 208 _ 20 rsvd; 209 conf 4 ro "Confidence level Permitted values are 0x0 (high) to 0x9 (low)"; 210 size 8 ro "Detection result face size Permitted values 0x14 to 0xF0"; 211 }; 212 213 regarray fd_angle addr(base, 0x16C)[35;0x10] "Detection Result: Angle. Its value is undefined after reset." { 214 _ 23 rsvd; 215 angle 9 ro "Detection result face angle Permitted values: When DIR = 0: 0x0 (0 deg) to 0x1E (30 deg) and 0x14A (330 deg) to 0x167 (359 deg) When DIR = 1: 0x03C (60 deg) to 0x078 (120 deg) When DIR = 2: 0x0F0 (240 deg) to 0x12C (300 deg)"; 216 }; 217};