1/*
2 * Copyright (c) 2012, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_emif.dev
12 *
13 * DESCRIPTION: OMAP44xx device identification
14 *
15 * This is derived from:
16 *
17 * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
18 * Manual Version Q, in particular Section 15.3.6
19 *
20 */
21
22device omap44xx_emif msbfirst ( addr base ) "OMAP44xx external memory intf." {
23
24    register mod_id_rev ro addr(base, 0x0000) "Revision" type(uint32);
25
26    register status ro addr(base, 0x0004) "SDRAM status" 
27    {
28	be		1	"Big endian select for 8 and 16-bit devices";
29	dual_clk	1	"Dual Clock mode";
30	fast_init	1	"Fast initialization mode";
31	_		26 mbz;
32	phy_dll_ready	1	"DDR Phy ready";
33	_		2 mbz;
34    };
35
36    constants sdram_type width(3) "SDRAM type values" {
37	sdram_s4 = 0x4		"LPDDR2-S4";
38	sdram_s2 = 0x5		"LPDDR2-S2";
39    };
40
41    register sdram_config rw addr(base, 0x0008) "SDRAM config" 
42    {
43	sdram_type	3 type(sdram_type) "SDRAM type";
44	ibank_pos	2	"Internal bank position";
45	_	        11;
46	narrow_mode	2	"SDRAM data bus width";
47	cl		4	"CAS latency";
48	rowsize		3	"Row size (add 9 for # row bits)";
49	ibank		3	"Internal bank setup: (1<<x) banks";
50	ebank		1	"External chip select setup";
51	pagesize	3	"Page size (add 9 for # column bits)";
52    };
53
54    register sdram_config2 rw addr(base, 0x000c) "SDRAM config 2" 
55    {
56	_		1;
57	cs1nvmen	1	"CS1 LPDDR2-NVM enable";
58	_		2;
59	ebank_pos	1	"External bank position";
60	_		21;
61	rdbnum		2	"Row buffer setup (1<<x) row buffers";
62	_		1;
63	rdbsize		3	"Row data buffer size 32(1<<x) bytes";
64    };
65
66    register sdram_ref_ctrl rw addr(base, 0x0010) "SDRAM refresh control" 
67    {
68	initref_dis	1	"Initialization and refresh disable";
69	_		15;
70	refresh_rate	16	"Refresh rate";
71    };
72    register sdram_ref_ctrl_shdw rw addr(base, 0x0014) 
73	"SDRAM refresh control shadow" type(sdram_ref_ctrl);
74
75    register sdram_tim1 rw addr(base, 0x0018) "SDRAM timing 1" 
76    {
77	_		3;
78	rp		4	"Minimum #DDR clocks precharge to act. or ref.";
79	rcd		4	"Minimum #DDR clocks activate to r or w";
80	wr		4	"Minimum #DDR clocks write to precharge";
81	ras		5	"Minimum #DDR clocks activate to precharge";
82	rc		6	"Minimum #DDR clocks activate to activate";
83	rrd		3	"Minimum #DDR clocks act. to act. other bank";
84	wtr		3	"Minimum #DDR clocks last write to read";
85    };
86    register sdram_tim1_shdw rw addr(base, 0x001c) "SDRAM timing 1 shadow" 
87	type(sdram_tim1);
88
89
90    register sdram_tim2 rw addr(base, 0x0020) "SDRAM timing 2" 
91    {
92	_		1;
93	xp		3	"Minimum #DDR clocks powerdown to non-read";
94	_		3;
95	xsnr		9	"Minimum #DDR clocks self-refresh to non-read";
96	xsrd		10	"Minimum #DDR clocks self-refresh to read";
97	rtp		3	"Minimum #DDR clocks last read to precharge";
98	cke		3	"Minimum #DDR clocks between pad_cke_o changes";
99    };
100    register sdram_tim2_shdw rw addr(base, 0x0024) "SDRAM timing 2 shadow" 
101	type(sdram_tim2);
102
103    register sdram_tim3 rw addr(base, 0x0028) "SDRAM timing 3" 
104    {
105	_		8;
106	ckesr		3	"Minimum #DDR clocks LPDDR2 in self-refresh";
107	zqcs		6	"#DDR clocks a ZQCS command";
108	tdqsckmax	2	"#DDR clocks that satisfies tDQSCKmax";
109	rfc		9	"Minimum #DDR clocks from ref/ld to ref/act.";
110	ras_max		4	"Maximum #interfaces from act. to precharge";
111     };
112    register sdram_tim3_shdw rw addr(base, 0x002c) "SDRAM timing 3 shadow" 
113	type(sdram_tim3);
114
115    register lpddr2_nvm_tim rw addr(base, 0x0030) "LPDDR2-NVM timing" 
116    {
117	_		1;
118	xp		3	"Minimum #DDR clocks from powerdown";
119	_		1;
120	wtr		3	"Minimum #DDR clocks last write to read";
121	rp		4	"Minimum #DDR clocks preactive to activate";
122	wra		4	"Minimum #DDR clocks last write to activate";
123	rrd		8	"Minimum #DDR clocks act. to act. other bank.";
124	rcdmin		8	"Minimum #DDR clocks activate to r/w";
125    };
126    register lpddr2_nvm_tim_shdw rw addr(base, 0x0034) 
127	"LPDDR2-NVM timing shadow" type(lpddr2_nvm_tim);
128
129
130    constants apm_mode width(3) "Auto power management mode" {
131	apm_cs = 1	"Clock stop";
132	apm_sr = 2	"Self-refresh";
133	apm_pd = 4	"Power down";
134    };
135    
136    register pwr_mgmt_ctrl rw addr(base, 0x0038) "Power management control" 
137    {
138	_		16;
139	pd_tim		4	"Power mangement timer for power-down";
140	dpd_en		1	"Deep power down enable";
141	lp_mode		3 type(apm_mode) "Automatic power management enable";
142	sr_tim		4	"Power mangement timer for self refresh";
143	cs_tim		4	"Power mangement timer for clock stop";
144    };
145    register pwr_mgmt_ctrl_shdw rw addr(base, 0x003c) 
146	"Power management control shadow" type(pwr_mgmt_ctrl);
147
148    register lpddr2_mode_reg_data rw addr(base, 0x0040) 
149	"LPDDR2 mode register data" type(uint32);
150
151    register lpddr2_mode_reg_cfg rw addr(base, 0x0050) 
152        "LPDDR2 mode register config"
153    {
154        cs              1       "Chip select to issue mode register command";
155        refresh_en      1       "Refresh Enable after MRW write";
156        _               22;
157        address         8       "Mode register address";
158    };
159
160    register l3_config rw addr(base, 0x0054) "L3 configuration" 
161    {
162	_		4;
163	sys_thresh_max	4	"System L3 threshold maximum";
164	_		4;
165	ll_thresh_max	4	"Low-latency L3 threshold maximum";
166	_		8;
167	pr_old_count	8	"Priority raise old counter";
168    };
169
170    register l3_cfg_val1 ro addr(base, 0x0058) "L3 config value 1" 
171    {
172	sys_bus_width	2	"System L3 data bus width 32*(1<<x) bits";
173	ll_bus_width	2	"Low-latency L3 data bus width 32*(1<<x)";
174	_		12 mbz;
175	wr_fifo_depth	8	"Write data FIFO depth";
176	cmd_fifo_depth	8	"Command FIFO depth";
177    };
178
179    register l3_cfg_val2 ro addr(base, 0x005c) "L3 config value 2" 
180    {
181	_		8 mbz;
182	rreg_fifo_depth 8	"Register Read Data FIFO depth";
183	rsd_fifo_depth	8	"SDRAM read data FIFO depth";
184	rcmd_fifo_depth	8	"Read command FIFO depth";
185    };
186
187    register perf_cnt_1 ro addr(base, 0x0080) "Perf. counter 1" type(uint32);
188    register perf_cnt_2 ro addr(base, 0x0084) "Perf. counter 2" type(uint32);
189
190    constants pcfilter width(4) "Performance counter filter" {
191	pcf_sdr_acc	= 0x0	"Total SDRAM accesses";
192	pcf_sdr_act	= 0x1	"Total SDRAM activates";
193	pcf_tot_rds	= 0x2	"Total reads";
194	pcf_tot_wrs	= 0x3	"Total writes";
195	pcf_cf_full	= 0x4	"Cycles L3 command FIFO is full";
196	pcf_wf_full	= 0x5	"Cycles L3 Write Data FIFO is full";
197	pcf_rf_full	= 0x6	"Cycles L3 Read Data FIFO is full";
198	pcf_tf_full	= 0x7	"Cycles L3 Return Command FIFO is full";
199	pcf_pri_elv	= 0x8	"Priority elevations";
200	pcf_cmd_pnd	= 0x9	"Cycles that a command was pending";
201	pcf_mem_xfr	= 0xa	"Cycles for which mem. data bus xferd data";
202    };
203    register perf_cnt_cfg rw addr(base, 0x0088) "Perf. cntr. config" 
204    {
205	cntr2_mconnid_en 1	"MConnID filter enable for perf. cntr. 2";
206	cntr2_region_en	1	"Chip Select filter enable for Perf. cntr 2";
207	_		10;
208	cntr2_cfg	4 type(pcfilter) "Filter config. for perf. cntr. 2";
209	cntr1_mconnid_en 1	"MConnID filter enable for perf. cntr. 1";
210	cntr1_region_en	1	"Chip Select filter enable for Perf. cntr 1";
211	_		10;
212	cntr1_cfg	4 type(pcfilter) "Filter config. for perf. cntr. 1";
213    };
214
215    register perf_cnt_sel rw addr(base, 0x008c) "Perf. cntr. master reg. sel." 
216    {
217	mconnid2	8	"MConnID for perf. counter 2";
218	_		6;
219	region_sel2	2	"MAddrSpace for perf. counter 2";
220	mconnid1	8	"MConnID for perf. counter 1";
221	_		6;
222	region_sel1	2	"MAddrSpace for perf. counter 1";
223    };
224
225    register perf_cnt_tim ro addr(base, 0x0090) "Perf. counter time" 
226	type(uint32);
227
228    register read_idle_ctrl rw addr(base, 0x0098) "Read idle control" 
229    {
230	_		12;
231	read_idle_len	4	"Min size of read idle window";
232	_		7;
233	read_idle_interval 9	"Read idle interval";
234    };
235    register read_idle_ctrl_shdw rw addr(base, 0x009C)
236	"Read idle control shadow" type(read_idle_ctrl);
237
238
239    regtype irq_l3 "L3 interrupt" { 
240	_		30;
241	ta_sys		1 	"SDRAM temperature alert.";
242	err_sys		1	"Command or address error.";
243    };
244
245    register irqstatus_raw_sys rw addr(base, 0x00a4) 
246	"System L3 interrupt raw status" type(irq_l3);
247
248    register irqstatus_raw_ll rw addr(base, 0x00a8) 
249	"Low-latency L3 interrupt raw status" type(irq_l3);
250
251    register irqstatus_sys rw addr(base, 0x00ac) 
252	"System L3 interrupt status" type(irq_l3);
253
254    register irqstatus_ll rw addr(base, 0x00b0) 
255	"Low-latency L3 interrupt status" type(irq_l3);
256
257    register irqenable_set_sys rw addr(base, 0x00b4) 
258	"System L3 interrupt enable set" type(irq_l3);
259
260    register irqenable_set_ll rw addr(base, 0x00b8) 
261	"Low-latency L3 interrupt enable set" type(irq_l3);
262
263    register irqenable_clr_sys rw addr(base, 0x00bc) 
264	"System L3 interrupt enable clear" type(irq_l3);
265
266    register irqenable_clr_ll rw addr(base, 0x00c0)
267	"Low-latency L3 interrupt enable clear" type(irq_l3);
268
269    register zq_config rw addr(base, 0x00c8) 
270	"SDRAM output impedance calibration config"
271    {
272	cs1en		1	"Enable ZQ calibration for CS1";
273	cs0en		1	"Enable ZQ calibration for CS0";
274	dualcalen	1	"ZQ Dual Calibration enable";
275	sfexiten	1	"ZQCL on self-rfr., act. pwrdn, prchrge pwrdwn";
276	_		8;
277	zqinit_mult	2	"Num ZQCL intervals in a ZQINIT interval -1";
278	zqcl_mult	2	"Num ZQCS intervals in a ZQCL interval -1";
279	refinterval	16	"Num rfrsh periods between ZQCS commands";
280    };
281
282    register temp_alert_config rw addr(base, 0x00cc) "Temperature Alert Config" 
283    {
284	cs1en		1	"Enables temperature alert polling for CS1";
285	cs0en		1	"Enables temperature alert polling for CS0";
286	_		1;
287	sfexiten	1	"Poll on self-rfr., act. pwrdn, prchrge pwrdwn";
288	devwdt		2	"Physical device width";
289	devcnt		2	"#lanes w/ temp. monitoring device";
290	_		2;
291	refinterval	22	"Num. refresh periods btw alert polls";
292    };
293
294    constants err_spc width(2) "Address space of errored transaction" {
295	es_sdram	= 0x0	"SDRAM";
296	es_ddr2		= 0x1	"LPDDR2-NVM";
297	es_int		= 0x3	"Internal registers";
298    };
299
300    register l3_err_log ro addr(base, 0x00d0) "Error log" 
301    {		
302	_		16;
303	maddrspace	2 type(err_spc) "Addr spc of 1st errored transaction";
304	mburstseq	3	"Addr mode of 1st errored transaction";
305	mcmd		3	"Cmd type of 1st errored transaction";
306	mconnid		8	"Connection ID of 1st errored transaction";
307    };
308
309    register ddr_phy_ctrl_1 rw addr(base, 0x00e4) "DDR PHY control 1" 
310    {
311	_		2;
312	freeze_delay_code_postamble	4
313	    "Postamble time respected by the DATA PHY";
314	freeze_delay_code_preamble	4
315	    "Preamble time respected by the DATA PHY";
316	dll_master_sw_code_ctrl		10 
317	    "DLL delay code when in software override mode";
318	dll_slave_dly_ctrl		8 
319	    "DLL slave delay ratio control";
320	read_latency			4
321	    "Read latency for the read data from SDRAM in DDR clock cycles";
322    };
323
324    register ddr_phy_ctrl_1_shdw rw addr(base, 0x00e8) 
325	"DDR PHY control 1 shadow" type(ddr_phy_ctrl_1);
326
327    register ddr_phy_ctrl_2 rw addr(base, 0x00ec) "DDR PHY control 2" 
328	type(uint32);
329};
330