1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_dsp_mmu.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_dsp_mmu msbfirst ( addr base ) "" { 29 30 31 register mmu_revision ro addr(base, 0x0) "This register contains the IP revision code" type(uint32); 32 33 constants idlemode_status width(2) "" { 34 IDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally"; 35 IDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged"; 36 IDLEMODE_2 = 2 "Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module"; 37 IDLEMODE_3 = 3 "reserved do not use"; 38 }; 39 40 constants softreset_status width(1) "" { 41 SOFTRESET_0_r = 0 "always return 0"; 42 SOFTRESET_0_w = 0 "no functional effect"; 43 SOFTRESET_1_w = 1 "The module is reset"; 44 SOFTRESET_1_r = 1 "never happens"; 45 }; 46 47 constants autoidle_status width(1) "" { 48 AUTOIDLE_0 = 0 "interconnect clock is free-running"; 49 AUTOIDLE_1 = 1 "Automatic interconnect clock gating strategy is applied, based on the interconnect interface activity"; 50 }; 51 52 register mmu_sysconfig addr(base, 0x10) "This register controls the various parameters of the L3 interconnect interface" { 53 _ 22 mbz; 54 clockactivity 2 ro "Clock activity during wake-up mode 00 Functional and Interconnect clocks can be switched off"; 55 _ 3 mbz; 56 idlemode 2 rw type(idlemode_status) "IdleMode"; 57 _ 1 mbz; 58 softreset 1 rw type(softreset_status) "Software reset. This bit is automatically reset by the hardware. During reads, it always return 0"; 59 autoidle 1 rw type(autoidle_status) "Internal interconnect clock gating strategy"; 60 }; 61 62 constants resetdone_status width(1) "" { 63 RESETDONE_0_r = 0 "Internal module reset in on-going"; 64 RESETDONE_1_r = 1 "Reset completed"; 65 }; 66 67 register mmu_sysstatus addr(base, 0x14) "This register provides status information about the module, excluding the interrupt status information" { 68 _ 31 mbz; 69 resetdone 1 ro type(resetdone_status) "Internal reset monitoring"; 70 }; 71 72 constants multihitfault_status width(1) "" { 73 MULTIHITFAULT_0_r = 0 "MultiHitFault false"; 74 MULTIHITFAULT_0_w = 0 "MultiHitFault status bit unchanged"; 75 MULTIHITFAULT_1_w = 1 "MultiHitFault status bit is reset"; 76 MULTIHITFAULT_1_r = 1 "MultiHitFault is true ('pending')"; 77 }; 78 79 constants tablewalkfault_status width(1) "" { 80 TABLEWALKFAULT_0_r = 0 "TableWalkFault false"; 81 TABLEWALKFAULT_0_w = 0 "TableWalkFault status bit unchanged"; 82 TABLEWALKFAULT_1_w = 1 "TableWalkFault status bit is reset"; 83 TABLEWALKFAULT_1_r = 1 "TableWalkFault is true ('pending')"; 84 }; 85 86 constants emumiss_status width(1) "" { 87 EMUMISS_0_r = 0 "EMUMiss false"; 88 EMUMISS_0_w = 0 "EMUMiss status bit unchanged"; 89 EMUMISS_1_w = 1 "EMUMiss status bit is reset"; 90 EMUMISS_1_r = 1 "EMUMiss is true ('pending')"; 91 }; 92 93 constants translationfault_status width(1) "" { 94 TRANSLATIONFAULT_0_r = 0 "TranslationFault false"; 95 TRANSLATIONFAULT_0_w = 0 "TranslationFault status bit unchanged"; 96 TRANSLATIONFAULT_1_w = 1 "TranslationFault status bit is reset"; 97 TRANSLATIONFAULT_1_r = 1 "TranslationFault is true ('pending')"; 98 }; 99 100 constants tlbmiss_status width(1) "" { 101 TLBMISS_0_r = 0 "TLBMiss false"; 102 TLBMISS_0_w = 0 "TLBMiss status bit unchanged"; 103 TLBMISS_1_w = 1 "TLBMiss status bit is reset"; 104 TLBMISS_1_r = 1 "TLBMiss is true ('pending')"; 105 }; 106 107 register mmu_irqstatus addr(base, 0x18) "This interrupt status register regroups all the status of the module internal events that can generate an interrupt." { 108 _ 27 mbz; 109 multihitfault 1 rw1c type(multihitfault_status) "Error due to multiple matches in the TLB"; 110 tablewalkfault 1 rw1c type(tablewalkfault_status) "Error response received during a Table Walk"; 111 emumiss 1 rw1c type(emumiss_status) "Unrecoverable TLB miss during debug (hardware TWL disabled)"; 112 translationfault 1 rw1c type(translationfault_status) "Invalid descriptor in translation tables (translation fault)"; 113 tlbmiss 1 rw1c type(tlbmiss_status) "Unrecoverable TLB miss (hardware TWL disabled)"; 114 }; 115 116 constants multihitfault_status1 width(1) "" { 117 MULTIHITFAULT_0 = 0 "MultiHitFault is masked"; 118 MULTIHITFAULT_1 = 1 "MultiHitFault event generates an interrupt if occurs"; 119 }; 120 121 constants tablewalkfault_status1 width(1) "" { 122 TABLEWALKFAULT_0 = 0 "TableWalkFault is masked"; 123 TABLEWALKFAULT_1 = 1 "TableWalkFault event generates an interrupt if occurs"; 124 }; 125 126 constants emumiss_status1 width(1) "" { 127 EMUMISS_0 = 0 "EMUMiss interrupt is masked"; 128 EMUMISS_1 = 1 "EMUMiss event generates an interrupt when it occurs"; 129 }; 130 131 constants translationfault_status1 width(1) "" { 132 TRANSLATIONFAULT_0 = 0 "TranslationFault is masked"; 133 TRANSLATIONFAULT_1 = 1 "TranslationFault event generates an interrupt if occurs"; 134 }; 135 136 constants tlbmiss_status1 width(1) "" { 137 TLBMISS_0 = 0 "TLBMiss interrupt is masked"; 138 TLBMISS_1 = 1 "TLBMiss event generates an interrupt when if occurs"; 139 }; 140 141 register mmu_irqenable addr(base, 0x1C) "The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." { 142 _ 27 mbz; 143 multihitfault 1 rw type(multihitfault_status1) "Error due to multiple matches in the TLB"; 144 tablewalkfault 1 rw type(tablewalkfault_status1) "Error response received during a Table Walk"; 145 emumiss 1 rw type(emumiss_status1) "Unrecoverable TLB miss during debug (hardware TWL disabled)"; 146 translationfault 1 rw type(translationfault_status1) "Invalid descriptor in translation tables (translation fault)"; 147 tlbmiss 1 rw type(tlbmiss_status1) "Unrecoverable TLB miss (hardware TWL disabled)"; 148 }; 149 150 constants twlrunning_status width(1) "" { 151 TWLRUNNING_0_r = 0 "TWL Completed"; 152 TWLRUNNING_1_r = 1 "TWL Running"; 153 }; 154 155 register mmu_walking_st addr(base, 0x40) "This register provides status information about the table walking logic" { 156 _ 31 mbz; 157 twlrunning 1 ro type(twlrunning_status) "Table Walking Logic is running"; 158 }; 159 160 constants emutlbupdate_status width(1) "" { 161 EMUTLBUPDATE_0 = 0 "Emulator TLB update disabled"; 162 EMUTLBUPDATE_1 = 1 "Emulator TLB update enabled"; 163 }; 164 165 constants twlenable_status width(1) "" { 166 TWLENABLE_0 = 0 "TWL disabled"; 167 TWLENABLE_1 = 1 "TWL enabled"; 168 }; 169 170 constants mmuenable_status width(1) "" { 171 MMUENABLE_0 = 0 "MMU disabled"; 172 MMUENABLE_1 = 1 "MMU enabled"; 173 }; 174 175 register mmu_cntl addr(base, 0x44) "This register programs the MMU features" { 176 _ 28 mbz; 177 emutlbupdate 1 rw type(emutlbupdate_status) "Enable TLB update on emulator table walk"; 178 twlenable 1 rw type(twlenable_status) "Table Walking Logic enable"; 179 mmuenable 1 rw type(mmuenable_status) "MMU enable"; 180 _ 1 mbz; 181 }; 182 183 register mmu_fault_ad ro addr(base, 0x48) "This register contains the virtual address that generated the interrupt" type(uint32); 184 185 register mmu_ttb addr(base, 0x4C) "This register contains the Translation Table Base address" { 186 ttbaddress 25 rw "Translation Table Base Address"; 187 _ 7 mbz; 188 }; 189 190 register mmu_lock addr(base, 0x50) "This register locks some of the TLB entries" { 191 _ 17 mbz; 192 basevalue 5 rw "Locked entries base value"; 193 _ 1 mbz; 194 currentvictim 5 rw "Current entry to be updated either by the TWL or by the software Write value : TLB entry to be updated by software, Read value : TLB entry that will be updated by table walk logic"; 195 _ 4 mbz; 196 }; 197 198 constants ldtlbitem_status width(1) "" { 199 LDTLBITEM_0_r = 0 "always return 0"; 200 LDTLBITEM_0_w = 0 "no functional effect"; 201 LDTLBITEM_1_w = 1 "load TLB data"; 202 LDTLBITEM_1_r = 1 "never happens"; 203 }; 204 205 register mmu_ld_tlb addr(base, 0x54) "This register loads a TLB entry (CAM+RAM)" { 206 _ 31 mbz; 207 ldtlbitem 1 rw type(ldtlbitem_status) "Write (load) data in the TLB"; 208 }; 209 210 constants p_status width(1) "" { 211 P_0 = 0 "TLB entry may be flushed"; 212 P_1 = 1 "TLB entry is protected against flush"; 213 }; 214 215 constants v_status width(1) "" { 216 V_0 = 0 "TLB entry is invalid"; 217 V_1 = 1 "TLB entry is valid"; 218 }; 219 220 constants pagesize_status width(2) "" { 221 PAGESIZE_0 = 0 "Section (1MB)"; 222 PAGESIZE_1 = 1 "Large page (64KB)"; 223 PAGESIZE_2 = 2 "Small page (4KB)"; 224 PAGESIZE_3 = 3 "Supersection (16MB)"; 225 }; 226 227 register mmu_cam addr(base, 0x58) "This register holds a CAM entry" { 228 vatag 20 rw "Virtual address tag"; 229 _ 8 mbz; 230 p 1 rw type(p_status) "Preserved bit"; 231 v 1 rw type(v_status) "Valid bit"; 232 pagesize 2 rw type(pagesize_status) "Page size"; 233 }; 234 235 constants endianness_status width(1) "" { 236 ENDIANNESS_0 = 0 "Little Endian"; 237 ENDIANNESS_1 = 1 "Big endian"; 238 }; 239 240 constants elementsize_status width(2) "" { 241 ELEMENTSIZE_0 = 0 "8-bits"; 242 ELEMENTSIZE_1 = 1 "16-bits"; 243 ELEMENTSIZE_2 = 2 "32-bits"; 244 ELEMENTSIZE_3 = 3 "No translation"; 245 }; 246 247 constants mixed_status width(1) "" { 248 MIXED_0 = 0 "Use TLB element size"; 249 MIXED_1 = 1 "Use CPU element size"; 250 }; 251 252 register mmu_ram addr(base, 0x5C) "This register holds a RAM entry" { 253 physicaladdress 20 rw "Physical address of the page"; 254 _ 2 mbz; 255 endianness 1 rw type(endianness_status) "Endianness of the page"; 256 elementsize 2 rw type(elementsize_status) "Element size of the page (8, 16, 32, no translation)"; 257 mixed 1 rw type(mixed_status) "Mixed page attribute (use CPU element size)"; 258 _ 6 mbz; 259 }; 260 261 constants globalflush_status width(1) "" { 262 GLOBALFLUSH_0_r = 0 "always return 0"; 263 GLOBALFLUSH_0_w = 0 "no functional effect"; 264 GLOBALFLUSH_1_w = 1 "flush all the non-protected TLB entries"; 265 GLOBALFLUSH_1_r = 1 "never happens"; 266 }; 267 268 register mmu_gflush addr(base, 0x60) "This register flushes all the non-protected TLB entries" { 269 _ 31 mbz; 270 globalflush 1 rw type(globalflush_status) "Flush all the non-protected TLB entries when set"; 271 }; 272 273 constants flushentry_status width(1) "" { 274 FLUSHENTRY_0_r = 0 "always return 0"; 275 FLUSHENTRY_0_w = 0 "no functional effect"; 276 FLUSHENTRY_1_w = 1 "flush all the TLB entries specified by the CAM register"; 277 FLUSHENTRY_1_r = 1 "never happens"; 278 }; 279 280 register mmu_flush_entry addr(base, 0x64) "This register flushes the entry pointed to by the CAM virtual address" { 281 _ 31 mbz; 282 flushentry 1 rw type(flushentry_status) "Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected"; 283 }; 284 285 register mmu_read_cam addr(base, 0x68) "This register reads CAM data from a CAM entry" { 286 vatag 20 ro "Virtual address tag"; 287 _ 8 mbz; 288 p 1 ro type(p_status) "Preserved bit"; 289 v 1 ro type(v_status) "Valid bit"; 290 pagesize 2 ro type(pagesize_status) "Page size"; 291 }; 292 293 register mmu_read_ram addr(base, 0x6C) "This register reads RAM data from a RAM entry" { 294 physicaladdress 20 ro "Physical address of the page"; 295 _ 2 mbz; 296 endianness 1 ro type(endianness_status) "Endianness of the page"; 297 elementsize 2 ro type(elementsize_status) "Element size of the page (8, 16, 32, no translation)"; 298 mixed 1 ro type(mixed_status) "Mixed page attribute (use CPU element size)"; 299 _ 6 mbz; 300 }; 301 302 register mmu_emu_fault_ad ro addr(base, 0x70) "This register contains the last virtual address of a fault caused by the debugger" type(uint32); 303 304 register mmu_fault_pc ro addr(base, 0x80) "Capture first fault PC value, controlled by[0] FAULTINDICATION. Notes: The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to Posted-write. All this description is valid only for the DSP MMU. The Cortex-M3 L2 MMU always reads zero from this register." type(uint32); 305 306 constants mmu_fault_trans_id_status width(4) "" { 307 MMU_FAULT_TRANS_ID_0_r = 0 "posted writes out of shared cache for Cortex-M3 MMU / eDMA read port 1 for DSP MMU"; 308 MMU_FAULT_TRANS_ID_1_r = 1 "Cortex-M3 video and display control processor I/D bus access for Cortex-M3 MMU / eDMA read port 2 for DSP MMU"; 309 MMU_FAULT_TRANS_ID_2_r = 2 "Cortex-M3 video and display control processor S bus access for Cortex-M3 MMU / eDMA write port 1 for DSP MMU"; 310 MMU_FAULT_TRANS_ID_3_r = 3 "Cortex-M3 SIMCOP control processor I/D bus access for Cortex-M3 MMU / eDMA write port 2 for DSP MMU"; 311 MMU_FAULT_TRANS_ID_4_r = 4 "Cortex-M3 SIMCOP control processor S bus access for Cortex-M3 MMU / shared cache Evictions/stores/Non-cacheable for DSP MMU"; 312 MMU_FAULT_TRANS_ID_5_r = 5 "reserved for Cortex-M3 MMU / shared cache request for Program/Data for DSP MMU"; 313 MMU_FAULT_TRANS_ID_6_r = 6 "reserved for Cortex-M3 MMU / shared cache request for DMA for DSP MMU"; 314 MMU_FAULT_TRANS_ID_7_r = 7 "reserved (for both Cortex-M3 MMU and DSP MMU)"; 315 MMU_FAULT_TRANS_ID_8_r = 8 "MMU hardware table walk (for both Cortex-M3 MMU and DSP MMU)"; 316 }; 317 318 constants mmu_fault_type_status width(2) "" { 319 MMU_FAULT_TYPE_2_r = 2 "reserved for Cortex-M3 MMU / DMA address for DSP MMU"; 320 MMU_FAULT_TYPE_1_r = 1 "Fetch address"; 321 MMU_FAULT_TYPE_0_r = 0 "Data Load/Store"; 322 }; 323 324 register mmu_fault_status addr(base, 0x84) "" { 325 _ 24 mbz; 326 mmu_fault_trans_id 4 ro type(mmu_fault_trans_id_status) "Master ID who cause a faultRead 0x9 to 0xF: reserved (for both Cortex-M3 MMU and DSP MMU) ."; 327 rd_wr 1 ro "indicates read or write"; 328 mmu_fault_type 2 ro type(mmu_fault_type_status) "MReq Type[1:0]"; 329 faultindication 1 rw1c "indicates a MMU fault"; 330 }; 331 332 register dspss_mmu_gpr addr(base, 0x88) "This register controls the DSP MMU hardware debug output multiplexer. It also controls force-idle request generation. For more information about the use of this register, see, Control Module." { 333 _ 16 mbz; 334 force_idle_req 1 rw "Force-idle request to see existence of pending bus request. This bit must be used only for debug purposes, not in functional mode."; 335 _ 11 mbz; 336 hwdebug_mux 4 rw "Control HWDEBUG output MUX"; 337 }; 338};