1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_dma_l3interconnect.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_dma_l3interconnect msbfirst ( addr base ) "" { 29 30 31 register simcop_dma_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility." type(uint32); 32 33 constants chan_status width(1) "" { 34 CHAN_0_r = 0 "4"; 35 CHAN_1_r = 1 "8"; 36 }; 37 38 constants context_status width(2) "" { 39 CONTEXT_0_r = 0 "4"; 40 CONTEXT_1_r = 1 "8"; 41 CONTEXT_2_r = 2 "16"; 42 }; 43 44 register simcop_dma_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration, that is, typically the module's HDL generics." { 45 _ 29 mbz; 46 chan 1 ro type(chan_status) "Logical channels"; 47 context 2 ro type(context_status) "Maximum outstanding OCP transactions"; 48 }; 49 50 constants standbymode_status width(2) "" { 51 STANDBYMODE_0 = 0 "Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only."; 52 STANDBYMODE_1 = 1 "No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only."; 53 STANDBYMODE_2 = 2 "Smart-standby mode."; 54 STANDBYMODE_3 = 3 "Smart-standby mode."; 55 }; 56 57 register simcop_dma_sysconfig addr(base, 0x10) "Clock management configuration" { 58 _ 26 mbz; 59 standbymode 2 rw type(standbymode_status) "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."; 60 _ 4 mbz; 61 }; 62 63 constants posted_writes_status width(1) "" { 64 POSTED_WRITES_0 = 0 "Only nonposted writes are generated"; 65 POSTED_WRITES_1 = 1 "Only posted writes are generated"; 66 }; 67 68 constants max_burst_size_status width(2) "" { 69 MAX_BURST_SIZE_0 = 0 "Single requests only"; 70 MAX_BURST_SIZE_1 = 1 "less or equal to 2"; 71 MAX_BURST_SIZE_2 = 2 "less or equal to 4"; 72 MAX_BURST_SIZE_3 = 3 "less or equal to 8"; 73 }; 74 75 register simcop_dma_ctrl addr(base, 0x1C) "" { 76 bw_limiter 16 rw "SIMCOP DMA guarantees that there are at least BW_LIMITER functional clock cycles between two OCP requests. No IDLE cycles are inserted during an OCP transaction. This parameter could be used to reduce traffic generated by the SIMCOP DMA for non timing critical applications. Doing so leaves more BW for other system initiators. Default value corresponds to maximum performance."; 77 _ 8 mbz; 78 tag_cnt 4 rw "Limits the outstanding transactions count. Only tags 0 - TAG_CNT will be used by SIMCOP DMA The maximum allowed value is 2"; 79 posted_writes 1 rw type(posted_writes_status) "Select write type. Setting depend on the used interconnect"; 80 _ 1 mbz; 81 max_burst_size 2 rw type(max_burst_size_status) "Defines the maximum burst length for INCR bursts. In case of 2D bursts, length x height is less or equal to this value."; 82 }; 83 84 constants chan7_frame_done_irq_status width(1) "" { 85 CHAN7_FRAME_DONE_IRQ_0_w = 0 "No action"; 86 CHAN7_FRAME_DONE_IRQ_0_r = 0 "No event pending"; 87 CHAN7_FRAME_DONE_IRQ_1_r = 1 "Event pending"; 88 CHAN7_FRAME_DONE_IRQ_1_w = 1 "Set event (debug)"; 89 }; 90 91 register simcop_dma_irqstatus_raw_j_0 addr(base, 0x20) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 92 chan7_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 93 chan6_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 94 chan5_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 95 chan4_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 96 chan3_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 97 chan2_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 98 chan1_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 99 chan0_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 100 chan7_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 101 chan6_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 102 chan5_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 103 chan4_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 104 chan3_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 105 chan2_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 106 chan1_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 107 chan0_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 108 _ 15 mbz; 109 ocp_err 1 rw type(chan7_frame_done_irq_status) "OCP error"; 110 }; 111 112 register simcop_dma_irqstatus_raw_j_1 addr(base, 0x30) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 113 chan7_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 114 chan6_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 115 chan5_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 116 chan4_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 117 chan3_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 118 chan2_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 119 chan1_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 120 chan0_frame_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of the full frame"; 121 chan7_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 122 chan6_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 123 chan5_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 124 chan4_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 125 chan3_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 126 chan2_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 127 chan1_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 128 chan0_block_done_irq 1 rw type(chan7_frame_done_irq_status) "Channel has completed transfer of one 2D block"; 129 _ 15 mbz; 130 ocp_err 1 rw type(chan7_frame_done_irq_status) "OCP error"; 131 }; 132 133 constants chan7_frame_done_irq_status1 width(1) "" { 134 CHAN7_FRAME_DONE_IRQ_0_w_2 = 0 "No action"; 135 CHAN7_FRAME_DONE_IRQ_0_r_2 = 0 "No (enabled) event pending"; 136 CHAN7_FRAME_DONE_IRQ_1_r_2 = 1 "Event pending"; 137 CHAN7_FRAME_DONE_IRQ_1_w_2 = 1 "Clear (raw) event"; 138 }; 139 140 register simcop_dma_irqstatus_j_0 addr(base, 0x24) "Per-event 'enabled' interrupt status vector Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 141 chan7_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 142 chan6_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 143 chan5_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 144 chan4_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 145 chan3_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 146 chan2_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 147 chan1_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 148 chan0_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 149 chan7_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 150 chan6_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 151 chan5_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 152 chan4_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 153 chan3_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 154 chan2_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 155 chan1_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 156 chan0_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 157 _ 15 mbz; 158 bus_err 1 rw1c type(chan7_frame_done_irq_status1) "BUS error"; 159 }; 160 161 register simcop_dma_irqstatus_j_1 addr(base, 0x34) "Per-event 'enabled' interrupt status vector Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 162 chan7_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 163 chan6_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 164 chan5_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 165 chan4_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 166 chan3_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 167 chan2_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 168 chan1_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 169 chan0_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of the full frame"; 170 chan7_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 171 chan6_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 172 chan5_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 173 chan4_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 174 chan3_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 175 chan2_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 176 chan1_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 177 chan0_block_done_irq 1 rw1c type(chan7_frame_done_irq_status1) "Channel has completed transfer of one 2D block"; 178 _ 15 mbz; 179 bus_err 1 rw1c type(chan7_frame_done_irq_status1) "BUS error"; 180 }; 181 182 constants chan7_frame_done_irq_status2 width(1) "" { 183 CHAN7_FRAME_DONE_IRQ_0_w_4 = 0 "No action"; 184 CHAN7_FRAME_DONE_IRQ_0_r_4 = 0 "Interrupt disabled (masked)"; 185 CHAN7_FRAME_DONE_IRQ_1_r_4 = 1 "Interrupt enabled"; 186 CHAN7_FRAME_DONE_IRQ_1_w_4 = 1 "Enable interrupt"; 187 }; 188 189 register simcop_dma_irqenable_set_j_0 addr(base, 0x28) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 190 chan7_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 191 chan6_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 192 chan5_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 193 chan4_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 194 chan3_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 195 chan2_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 196 chan1_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 197 chan0_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 198 chan7_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 199 chan6_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 200 chan5_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 201 chan4_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 202 chan3_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 203 chan2_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 204 chan1_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 205 chan0_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 206 _ 15 mbz; 207 ocp_err 1 rw type(chan7_frame_done_irq_status2) "OCP error"; 208 }; 209 210 register simcop_dma_irqenable_set_j_1 addr(base, 0x38) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 211 chan7_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 212 chan6_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 213 chan5_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 214 chan4_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 215 chan3_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 216 chan2_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 217 chan1_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 218 chan0_frame_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of the full frame"; 219 chan7_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 220 chan6_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 221 chan5_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 222 chan4_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 223 chan3_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 224 chan2_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 225 chan1_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 226 chan0_block_done_irq 1 rw type(chan7_frame_done_irq_status2) "Channel has completed transfer of one 2D block"; 227 _ 15 mbz; 228 ocp_err 1 rw type(chan7_frame_done_irq_status2) "OCP error"; 229 }; 230 231 constants chan7_frame_done_irq_status3 width(1) "" { 232 CHAN7_FRAME_DONE_IRQ_0_w_6 = 0 "No action"; 233 CHAN7_FRAME_DONE_IRQ_0_r_6 = 0 "Interrupt disabled (masked)"; 234 CHAN7_FRAME_DONE_IRQ_1_r_6 = 1 "Interrupt enabled"; 235 CHAN7_FRAME_DONE_IRQ_1_w_6 = 1 "Disable interrupt"; 236 }; 237 238 register simcop_dma_irqenable_clr_j_0 addr(base, 0x2C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 239 chan7_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 240 chan6_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 241 chan5_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 242 chan4_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 243 chan3_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 244 chan2_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 245 chan1_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 246 chan0_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 247 chan7_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 248 chan6_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 249 chan5_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 250 chan4_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 251 chan3_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 252 chan2_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 253 chan1_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 254 chan0_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 255 _ 15 mbz; 256 ocp_err 1 rw1c type(chan7_frame_done_irq_status3) "OCP error"; 257 }; 258 259 register simcop_dma_irqenable_clr_j_1 addr(base, 0x3C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 260 chan7_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 261 chan6_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 262 chan5_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 263 chan4_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 264 chan3_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 265 chan2_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 266 chan1_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 267 chan0_frame_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of the full frame"; 268 chan7_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 269 chan6_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 270 chan5_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 271 chan4_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 272 chan3_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 273 chan2_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 274 chan1_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 275 chan0_block_done_irq 1 rw1c type(chan7_frame_done_irq_status3) "Channel has completed transfer of one 2D block"; 276 _ 15 mbz; 277 ocp_err 1 rw1c type(chan7_frame_done_irq_status3) "OCP error"; 278 }; 279 280 constants hwstop_status width(3) "" { 281 HWSTOP_0 = 0 "Disabled."; 282 HWSTOP_4 = 4 "Use hardware synchronization channel 0"; 283 HWSTOP_5 = 5 "Use hardware synchronization channel 1"; 284 HWSTOP_6 = 6 "Use hardware synchronization channel 2"; 285 HWSTOP_7 = 7 "Use hardware synchronization channel 3"; 286 }; 287 288 constants linked_status width(5) "" { 289 LINKED_0 = 0 "Disabled."; 290 LINKED_16 = 16 "Start channel 0 when this channel has completed transfer of one 2D block"; 291 LINKED_17 = 17 "Start channel 1 when this channel has completed transfer of one 2D block"; 292 LINKED_18 = 18 "Start channel 2 when this channel has completed transfer of one 2D block"; 293 LINKED_19 = 19 "Start channel 3 when this channel has completed transfer of one 2D block"; 294 LINKED_20 = 20 "Start channel 4 when this channel has completed transfer of one 2D block"; 295 LINKED_21 = 21 "Start channel 5 when this channel has completed transfer of one 2D block"; 296 LINKED_22 = 22 "Start channel 6 when this channel has completed transfer of one 2D block"; 297 LINKED_23 = 23 "Start channel 7 when this channel has completed transfer of one 2D block"; 298 }; 299 300 constants tilermode_status width(1) "" { 301 TILERMODE_0 = 0 "Regular mode. INCR burst are used. ADDR[32]=0 for OCP transactions"; 302 TILERMODE_1 = 1 "Tiler mode. BLCK burst are used. ADDR[32]=1 for OCP transactions"; 303 }; 304 305 constants dir_status width(1) "" { 306 DIR_0 = 0 "System memory - SIMCOP buffers"; 307 DIR_1 = 1 "SIMCOP buffers - system memory"; 308 }; 309 310 constants status_status width(2) "" { 311 STATUS_0_r = 0 "Idle"; 312 STATUS_1_r = 1 "Active"; 313 STATUS_2_r = 2 "Pending"; 314 STATUS_3_r = 3 "Running"; 315 }; 316 317 constants swtrigger_status width(1) "" { 318 SWTRIGGER_0_w = 0 "No effect"; 319 SWTRIGGER_1_w = 1 "Change the logical channel state to PENDING if it is in ACTIVE state. No effect if the channel is in RUNNING, PENDING or IDLE state"; 320 }; 321 322 constants disable_status width(1) "" { 323 DISABLE_0_w = 0 "No effect."; 324 DISABLE_1_w = 1 "Disable the channel. Changes the logical channel state to IDLE when it is in ACTIVE state. Memorize a disable request when the channel is in RUNNING or PENDING state."; 325 }; 326 327 constants enable_status width(1) "" { 328 ENABLE_0_w = 0 "No effect"; 329 ENABLE_1_w = 1 "Enable the channel. Changes the state of the logical channel from IDLE to ACTIVE."; 330 }; 331 332 register simcop_dma_chan_ctrl_i_0 addr(base, 0x80) "Logical channel control register" { 333 _ 9 mbz; 334 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 335 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 336 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 337 _ 5 mbz; 338 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 339 dir 1 rw type(dir_status) "Transfer direction"; 340 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 341 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 342 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 343 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 344 }; 345 346 register simcop_dma_chan_ctrl_i_1 addr(base, 0xB0) "Logical channel control register" { 347 _ 9 mbz; 348 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 349 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 350 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 351 _ 5 mbz; 352 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 353 dir 1 rw type(dir_status) "Transfer direction"; 354 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 355 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 356 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 357 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 358 }; 359 360 register simcop_dma_chan_ctrl_i_2 addr(base, 0xE0) "Logical channel control register" { 361 _ 9 mbz; 362 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 363 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 364 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 365 _ 5 mbz; 366 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 367 dir 1 rw type(dir_status) "Transfer direction"; 368 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 369 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 370 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 371 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 372 }; 373 374 register simcop_dma_chan_ctrl_i_3 addr(base, 0x110) "Logical channel control register" { 375 _ 9 mbz; 376 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 377 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 378 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 379 _ 5 mbz; 380 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 381 dir 1 rw type(dir_status) "Transfer direction"; 382 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 383 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 384 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 385 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 386 }; 387 388 register simcop_dma_chan_ctrl_i_4 addr(base, 0x140) "Logical channel control register" { 389 _ 9 mbz; 390 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 391 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 392 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 393 _ 5 mbz; 394 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 395 dir 1 rw type(dir_status) "Transfer direction"; 396 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 397 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 398 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 399 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 400 }; 401 402 register simcop_dma_chan_ctrl_i_5 addr(base, 0x170) "Logical channel control register" { 403 _ 9 mbz; 404 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 405 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 406 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 407 _ 5 mbz; 408 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 409 dir 1 rw type(dir_status) "Transfer direction"; 410 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 411 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 412 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 413 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 414 }; 415 416 register simcop_dma_chan_ctrl_i_6 addr(base, 0x1A0) "Logical channel control register" { 417 _ 9 mbz; 418 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 419 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 420 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 421 _ 5 mbz; 422 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 423 dir 1 rw type(dir_status) "Transfer direction"; 424 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 425 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 426 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 427 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 428 }; 429 430 register simcop_dma_chan_ctrl_i_7 addr(base, 0x1D0) "Logical channel control register" { 431 _ 9 mbz; 432 hwstop 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls generation of the DONE pulse for the logical channel Only the values listed below are allowed. Other values lead to undefined behavior."; 433 hwstart 3 rw type(hwstop_status) "DMA logical channel hardware synchronization. Controls sensitivity of the logical channel on a START pulse Only the values listed below are allowed. Other values lead to undefined behavior."; 434 linked 5 rw type(linked_status) "DMA logical channel linking. Only the values listed below are allowed. Other values lead to undefined behavior."; 435 _ 5 mbz; 436 tilermode 1 rw type(tilermode_status) "Selects OCP transaction breakdown algorithm"; 437 dir 1 rw type(dir_status) "Transfer direction"; 438 status 2 ro type(status_status) "SW could poll this bit to know the state of the channel"; 439 swtrigger 1 wo type(swtrigger_status) "Software trigger of the DMA channel. Read of this register always returns 0."; 440 disable 1 wo type(disable_status) "Disable control of the logical channel. Read of this register always returns 0."; 441 enable 1 wo type(enable_status) "Enable control of the logical channel. Read of this register always returns 0."; 442 }; 443 444 register simcop_dma_chan_smem_addr_i_0 addr(base, 0x84) "System memory address" { 445 addr 28 rw "Address in 128-bit words"; 446 _ 4 mbz; 447 }; 448 449 register simcop_dma_chan_smem_addr_i_1 addr(base, 0xB4) "System memory address" { 450 addr 28 rw "Address in 128-bit words"; 451 _ 4 mbz; 452 }; 453 454 register simcop_dma_chan_smem_addr_i_2 addr(base, 0xE4) "System memory address" { 455 addr 28 rw "Address in 128-bit words"; 456 _ 4 mbz; 457 }; 458 459 register simcop_dma_chan_smem_addr_i_3 addr(base, 0x114) "System memory address" { 460 addr 28 rw "Address in 128-bit words"; 461 _ 4 mbz; 462 }; 463 464 register simcop_dma_chan_smem_addr_i_4 addr(base, 0x144) "System memory address" { 465 addr 28 rw "Address in 128-bit words"; 466 _ 4 mbz; 467 }; 468 469 register simcop_dma_chan_smem_addr_i_5 addr(base, 0x174) "System memory address" { 470 addr 28 rw "Address in 128-bit words"; 471 _ 4 mbz; 472 }; 473 474 register simcop_dma_chan_smem_addr_i_6 addr(base, 0x1A4) "System memory address" { 475 addr 28 rw "Address in 128-bit words"; 476 _ 4 mbz; 477 }; 478 479 register simcop_dma_chan_smem_addr_i_7 addr(base, 0x1D4) "System memory address" { 480 addr 28 rw "Address in 128-bit words"; 481 _ 4 mbz; 482 }; 483 484 register simcop_dma_chan_smem_ofst_i_0 addr(base, 0x88) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 485 _ 12 mbz; 486 ofst 16 rw "Line offset. In 128-bit words."; 487 _ 4 mbz; 488 }; 489 490 register simcop_dma_chan_smem_ofst_i_1 addr(base, 0xB8) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 491 _ 12 mbz; 492 ofst 16 rw "Line offset. In 128-bit words."; 493 _ 4 mbz; 494 }; 495 496 register simcop_dma_chan_smem_ofst_i_2 addr(base, 0xE8) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 497 _ 12 mbz; 498 ofst 16 rw "Line offset. In 128-bit words."; 499 _ 4 mbz; 500 }; 501 502 register simcop_dma_chan_smem_ofst_i_3 addr(base, 0x118) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 503 _ 12 mbz; 504 ofst 16 rw "Line offset. In 128-bit words."; 505 _ 4 mbz; 506 }; 507 508 register simcop_dma_chan_smem_ofst_i_4 addr(base, 0x148) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 509 _ 12 mbz; 510 ofst 16 rw "Line offset. In 128-bit words."; 511 _ 4 mbz; 512 }; 513 514 register simcop_dma_chan_smem_ofst_i_5 addr(base, 0x178) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 515 _ 12 mbz; 516 ofst 16 rw "Line offset. In 128-bit words."; 517 _ 4 mbz; 518 }; 519 520 register simcop_dma_chan_smem_ofst_i_6 addr(base, 0x1A8) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 521 _ 12 mbz; 522 ofst 16 rw "Line offset. In 128-bit words."; 523 _ 4 mbz; 524 }; 525 526 register simcop_dma_chan_smem_ofst_i_7 addr(base, 0x1D8) "System memory line offset in 128-bit words. Maximum stride = 1MB" { 527 _ 12 mbz; 528 ofst 16 rw "Line offset. In 128-bit words."; 529 _ 4 mbz; 530 }; 531 532 register simcop_dma_chan_buf_ofst_i_0 addr(base, 0x8C) "SIMCOP memory line offset" { 533 _ 8 mbz; 534 ofst 20 rw "Line offset. In 128-bit words."; 535 _ 4 mbz; 536 }; 537 538 register simcop_dma_chan_buf_ofst_i_1 addr(base, 0xBC) "SIMCOP memory line offset" { 539 _ 8 mbz; 540 ofst 20 rw "Line offset. In 128-bit words."; 541 _ 4 mbz; 542 }; 543 544 register simcop_dma_chan_buf_ofst_i_2 addr(base, 0xEC) "SIMCOP memory line offset" { 545 _ 8 mbz; 546 ofst 20 rw "Line offset. In 128-bit words."; 547 _ 4 mbz; 548 }; 549 550 register simcop_dma_chan_buf_ofst_i_3 addr(base, 0x11C) "SIMCOP memory line offset" { 551 _ 8 mbz; 552 ofst 20 rw "Line offset. In 128-bit words."; 553 _ 4 mbz; 554 }; 555 556 register simcop_dma_chan_buf_ofst_i_4 addr(base, 0x14C) "SIMCOP memory line offset" { 557 _ 8 mbz; 558 ofst 20 rw "Line offset. In 128-bit words."; 559 _ 4 mbz; 560 }; 561 562 register simcop_dma_chan_buf_ofst_i_5 addr(base, 0x17C) "SIMCOP memory line offset" { 563 _ 8 mbz; 564 ofst 20 rw "Line offset. In 128-bit words."; 565 _ 4 mbz; 566 }; 567 568 register simcop_dma_chan_buf_ofst_i_6 addr(base, 0x1AC) "SIMCOP memory line offset" { 569 _ 8 mbz; 570 ofst 20 rw "Line offset. In 128-bit words."; 571 _ 4 mbz; 572 }; 573 574 register simcop_dma_chan_buf_ofst_i_7 addr(base, 0x1DC) "SIMCOP memory line offset" { 575 _ 8 mbz; 576 ofst 20 rw "Line offset. In 128-bit words."; 577 _ 4 mbz; 578 }; 579 580 register simcop_dma_chan_buf_addr_i_0 addr(base, 0x90) "SIMCOP memory address" { 581 _ 8 mbz; 582 addr 20 rw "Address in 128-bit words."; 583 _ 4 mbz; 584 }; 585 586 register simcop_dma_chan_buf_addr_i_1 addr(base, 0xC0) "SIMCOP memory address" { 587 _ 8 mbz; 588 addr 20 rw "Address in 128-bit words."; 589 _ 4 mbz; 590 }; 591 592 register simcop_dma_chan_buf_addr_i_2 addr(base, 0xF0) "SIMCOP memory address" { 593 _ 8 mbz; 594 addr 20 rw "Address in 128-bit words."; 595 _ 4 mbz; 596 }; 597 598 register simcop_dma_chan_buf_addr_i_3 addr(base, 0x120) "SIMCOP memory address" { 599 _ 8 mbz; 600 addr 20 rw "Address in 128-bit words."; 601 _ 4 mbz; 602 }; 603 604 register simcop_dma_chan_buf_addr_i_4 addr(base, 0x150) "SIMCOP memory address" { 605 _ 8 mbz; 606 addr 20 rw "Address in 128-bit words."; 607 _ 4 mbz; 608 }; 609 610 register simcop_dma_chan_buf_addr_i_5 addr(base, 0x180) "SIMCOP memory address" { 611 _ 8 mbz; 612 addr 20 rw "Address in 128-bit words."; 613 _ 4 mbz; 614 }; 615 616 register simcop_dma_chan_buf_addr_i_6 addr(base, 0x1B0) "SIMCOP memory address" { 617 _ 8 mbz; 618 addr 20 rw "Address in 128-bit words."; 619 _ 4 mbz; 620 }; 621 622 register simcop_dma_chan_buf_addr_i_7 addr(base, 0x1E0) "SIMCOP memory address" { 623 _ 8 mbz; 624 addr 20 rw "Address in 128-bit words."; 625 _ 4 mbz; 626 }; 627 628 register simcop_dma_chan_block_size_i_0 addr(base, 0x94) "2D block size" { 629 _ 3 mbz; 630 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 631 _ 2 mbz; 632 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 633 _ 4 mbz; 634 }; 635 636 register simcop_dma_chan_block_size_i_1 addr(base, 0xC4) "2D block size" { 637 _ 3 mbz; 638 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 639 _ 2 mbz; 640 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 641 _ 4 mbz; 642 }; 643 644 register simcop_dma_chan_block_size_i_2 addr(base, 0xF4) "2D block size" { 645 _ 3 mbz; 646 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 647 _ 2 mbz; 648 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 649 _ 4 mbz; 650 }; 651 652 register simcop_dma_chan_block_size_i_3 addr(base, 0x124) "2D block size" { 653 _ 3 mbz; 654 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 655 _ 2 mbz; 656 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 657 _ 4 mbz; 658 }; 659 660 register simcop_dma_chan_block_size_i_4 addr(base, 0x154) "2D block size" { 661 _ 3 mbz; 662 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 663 _ 2 mbz; 664 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 665 _ 4 mbz; 666 }; 667 668 register simcop_dma_chan_block_size_i_5 addr(base, 0x184) "2D block size" { 669 _ 3 mbz; 670 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 671 _ 2 mbz; 672 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 673 _ 4 mbz; 674 }; 675 676 register simcop_dma_chan_block_size_i_6 addr(base, 0x1B4) "2D block size" { 677 _ 3 mbz; 678 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 679 _ 2 mbz; 680 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 681 _ 4 mbz; 682 }; 683 684 register simcop_dma_chan_block_size_i_7 addr(base, 0x1E4) "2D block size" { 685 _ 3 mbz; 686 ynum 13 rw "Height, in lines, per 2D block Valid values are 1- 8191."; 687 _ 2 mbz; 688 xnum 10 rw "Width, in 128-bit words, per 2D block. Valid values are 1-1023, that corresponds to 16 bytes to 16KB."; 689 _ 4 mbz; 690 }; 691 692 register simcop_dma_chan_frame_i_0 addr(base, 0x98) "Defines a frame. A frame is composed of 2D blocks." { 693 _ 6 mbz; 694 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 695 _ 6 mbz; 696 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 697 }; 698 699 register simcop_dma_chan_frame_i_1 addr(base, 0xC8) "Defines a frame. A frame is composed of 2D blocks." { 700 _ 6 mbz; 701 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 702 _ 6 mbz; 703 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 704 }; 705 706 register simcop_dma_chan_frame_i_2 addr(base, 0xF8) "Defines a frame. A frame is composed of 2D blocks." { 707 _ 6 mbz; 708 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 709 _ 6 mbz; 710 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 711 }; 712 713 register simcop_dma_chan_frame_i_3 addr(base, 0x128) "Defines a frame. A frame is composed of 2D blocks." { 714 _ 6 mbz; 715 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 716 _ 6 mbz; 717 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 718 }; 719 720 register simcop_dma_chan_frame_i_4 addr(base, 0x158) "Defines a frame. A frame is composed of 2D blocks." { 721 _ 6 mbz; 722 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 723 _ 6 mbz; 724 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 725 }; 726 727 register simcop_dma_chan_frame_i_5 addr(base, 0x188) "Defines a frame. A frame is composed of 2D blocks." { 728 _ 6 mbz; 729 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 730 _ 6 mbz; 731 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 732 }; 733 734 register simcop_dma_chan_frame_i_6 addr(base, 0x1B8) "Defines a frame. A frame is composed of 2D blocks." { 735 _ 6 mbz; 736 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 737 _ 6 mbz; 738 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 739 }; 740 741 register simcop_dma_chan_frame_i_7 addr(base, 0x1E8) "Defines a frame. A frame is composed of 2D blocks." { 742 _ 6 mbz; 743 ycnt 10 rw "Vertical count of 2D blocks per frame. Valid values are 1-1023"; 744 _ 6 mbz; 745 xcnt 10 rw "Horizontal count of 2D blocks per frame. Valid values are 1-1023"; 746 }; 747 748 register simcop_dma_chan_current_block_i_0 addr(base, 0xA0) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 749 _ 6 mbz; 750 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 751 _ 6 mbz; 752 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 753 }; 754 755 register simcop_dma_chan_current_block_i_1 addr(base, 0xD0) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 756 _ 6 mbz; 757 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 758 _ 6 mbz; 759 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 760 }; 761 762 register simcop_dma_chan_current_block_i_2 addr(base, 0x100) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 763 _ 6 mbz; 764 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 765 _ 6 mbz; 766 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 767 }; 768 769 register simcop_dma_chan_current_block_i_3 addr(base, 0x130) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 770 _ 6 mbz; 771 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 772 _ 6 mbz; 773 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 774 }; 775 776 register simcop_dma_chan_current_block_i_4 addr(base, 0x160) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 777 _ 6 mbz; 778 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 779 _ 6 mbz; 780 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 781 }; 782 783 register simcop_dma_chan_current_block_i_5 addr(base, 0x190) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 784 _ 6 mbz; 785 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 786 _ 6 mbz; 787 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 788 }; 789 790 register simcop_dma_chan_current_block_i_6 addr(base, 0x1C0) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 791 _ 6 mbz; 792 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 793 _ 6 mbz; 794 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 795 }; 796 797 register simcop_dma_chan_current_block_i_7 addr(base, 0x1F0) "SW could read the coordinates of the last transferred block. The status is reset when the channel is enabled (change the state of CTRL.ENABLE from 0 to 1)." { 798 _ 6 mbz; 799 by 10 ro "Vertical position of the last transferred 2D block in the frame."; 800 _ 6 mbz; 801 bx 10 ro "Horizontal position of the last transferred 2D block in the frame."; 802 }; 803 804 register simcop_dma_chan_block_step_i_0 addr(base, 0xA4) "Offset between 2D blocks." { 805 _ 2 mbz; 806 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 807 _ 1 mbz; 808 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 809 _ 4 mbz; 810 }; 811 812 register simcop_dma_chan_block_step_i_1 addr(base, 0xD4) "Offset between 2D blocks." { 813 _ 2 mbz; 814 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 815 _ 1 mbz; 816 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 817 _ 4 mbz; 818 }; 819 820 register simcop_dma_chan_block_step_i_2 addr(base, 0x104) "Offset between 2D blocks." { 821 _ 2 mbz; 822 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 823 _ 1 mbz; 824 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 825 _ 4 mbz; 826 }; 827 828 register simcop_dma_chan_block_step_i_3 addr(base, 0x134) "Offset between 2D blocks." { 829 _ 2 mbz; 830 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 831 _ 1 mbz; 832 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 833 _ 4 mbz; 834 }; 835 836 register simcop_dma_chan_block_step_i_4 addr(base, 0x164) "Offset between 2D blocks." { 837 _ 2 mbz; 838 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 839 _ 1 mbz; 840 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 841 _ 4 mbz; 842 }; 843 844 register simcop_dma_chan_block_step_i_5 addr(base, 0x194) "Offset between 2D blocks." { 845 _ 2 mbz; 846 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 847 _ 1 mbz; 848 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 849 _ 4 mbz; 850 }; 851 852 register simcop_dma_chan_block_step_i_6 addr(base, 0x1C4) "Offset between 2D blocks." { 853 _ 2 mbz; 854 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 855 _ 1 mbz; 856 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 857 _ 4 mbz; 858 }; 859 860 register simcop_dma_chan_block_step_i_7 addr(base, 0x1F4) "Offset between 2D blocks." { 861 _ 2 mbz; 862 ystep 14 rw "Vertical offset, in lines, between rows of 2D blocks. For contiguous 2D blocks YSTEP=YNUM Valid values are -8192 to +8191."; 863 _ 1 mbz; 864 xstep 11 rw "Horizontal offset, in 128-bit words, between 2D block columns. For contiguous 2D blocks XSTEP=XNUM Valid values are -1024 to +1023, that corresponds to 16 bytes to 16KB."; 865 _ 4 mbz; 866 }; 867};