1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_cortexa9_cpu0.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_cortexa9_cpu0 msbfirst ( addr base ) "" { 29 30 31 constants l1_bank_onstate_status width(2) "" { 32 L1_BANK_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants l1_bank_retstate_status width(1) "" { 36 L1_BANK_RETSTATE_1_r = 1 "Memory bank is retained when domain is in RETENTION state."; 37 }; 38 39 constants logicretstate_status width(1) "" { 40 LOGICRETSTATE_0 = 0 "All CPU logic is off when the domain is in RETENTION state."; 41 LOGICRETSTATE_1 = 1 "Whole logic is retained when domain is in RETENTION state."; 42 }; 43 44 constants powerstate_status width(2) "" { 45 POWERSTATE_0 = 0 "OFF state"; 46 POWERSTATE_1 = 1 "RETENTION state"; 47 POWERSTATE_2 = 2 "INACTIVE state"; 48 POWERSTATE_3 = 3 "ON State"; 49 }; 50 51 register pm_pda_cpui_pwrstctrl addr(base, 0x0) "This register controls the CPU domain power state to reach upon a domain sleep transition" { 52 _ 14 mbz; 53 l1_bank_onstate 2 ro type(l1_bank_onstate_status) "CPU_L1 memory state when domain is ON."; 54 _ 7 mbz; 55 l1_bank_retstate 1 ro type(l1_bank_retstate_status) "CPU L1 memory state when domain is RETENTION state."; 56 _ 5 mbz; 57 logicretstate 1 rw type(logicretstate_status) "Logic state control when power domain is RETENTION"; 58 powerstate 2 rw type(powerstate_status) "Power state control"; 59 }; 60 61 constants intransition_status width(1) "" { 62 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 63 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 64 }; 65 66 constants l1_bank_statest_status width(2) "" { 67 L1_BANK_STATEST_0_r = 0 "Memory is OFF"; 68 L1_BANK_STATEST_1_r = 1 "Memory is RET"; 69 L1_BANK_STATEST_2_r = 2 "Reserved"; 70 L1_BANK_STATEST_3_r = 3 "Memory is ON"; 71 }; 72 73 constants logicstatest_status width(1) "" { 74 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 75 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 76 }; 77 78 constants powerstatest_status width(2) "" { 79 POWERSTATEST_0_r = 0 "Power domain is OFF"; 80 POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; 81 POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; 82 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 83 }; 84 85 register pm_pda_cpui_pwrstst addr(base, 0x4) "This register provides a status on the CPU domain current power state. [warm reset insensitive]" { 86 _ 6 mbz; 87 lastpowerstateentered 2 rw "Last low power state entered. The software has to write 0x3 in this field to update this register. 0x0: Power domain was previously in OFF 0x1: Power domain was previously in RETENTION 0x2: Power domain was previously INACTIVE 0x3: Power domain was previously ON"; 88 _ 3 mbz; 89 intransition 1 ro type(intransition_status) "Domain transition status"; 90 _ 14 mbz; 91 l1_bank_statest 2 ro type(l1_bank_statest_status) "CPU_L1 memory state status"; 92 _ 1 mbz; 93 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 94 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 95 }; 96 97 constants lostmem_cpu_l1_status width(1) "" { 98 LOSTMEM_CPU_L1_0 = 0 "Context has been maintained"; 99 LOSTMEM_CPU_L1_1 = 1 "Context has been lost"; 100 }; 101 102 register rm_pda_cpui_context addr(base, 0x8) "This register contains dedicated CPU context statuses. [warm reset insensitive]" { 103 _ 23 mbz; 104 lostmem_cpu_l1 1 rw1c type(lostmem_cpu_l1_status) "Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source."; 105 _ 7 mbz; 106 lostcontext_dff 1 rw1c type(lostmem_cpu_l1_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source."; 107 }; 108 109 constants rst_status width(1) "" { 110 RST_0 = 0 "Reset is cleared"; 111 RST_1 = 1 "Reset is asserted"; 112 }; 113 114 register rm_pda_cpui_rstctrl addr(base, 0xC) "This register controls the assertion/release of the CPU CORE reset. This is basically a software warm reset (that asserts CPUx_RST) per CPU. One CPU can set this bit to reset the other CPU. Actually the CPU can set this bit to reset itself as well (and it will be kept in reset until the other active CPU clears this bit)." { 115 _ 31 mbz; 116 rst 1 rw type(rst_status) "CPU warm local reset control"; 117 }; 118 119 constants stbyst_status width(1) "" { 120 STBYST_0_r = 0 "Module is functional (not in standby)"; 121 STBYST_1_r = 1 "Module is in standby"; 122 }; 123 124 register cm_pda_cpui_clkctrl addr(base, 0x14) "This register manages the CPU clocks." { 125 _ 31 mbz; 126 stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]"; 127 }; 128 129 constants clktrctrl_status width(2) "" { 130 CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wake-up transition may however occur."; 131 CLKTRCTRL_1_r = 1 "Reserved"; 132 CLKTRCTRL_2 = 2 "Start a software forced wake-up transition on the domain. The software forced wake-up transition allows the software to wakeup a powered-down CPU by a method other than an externally triggered interrupt."; 133 CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wake-up transition are based upon hardware conditions. WFI triggers the sleep transition based on settings in and registers."; 134 }; 135 136 register cm_pda_cpui_clkstctrl addr(base, 0x18) "This register enables the CPU domain power state transition. It controls the hardware-supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 137 _ 30 mbz; 138 clktrctrl 2 rw type(clktrctrl_status) "Controls the full domain transition of the CPU domain."; 139 }; 140};