1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_core_cm2.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_core_cm2 msbfirst ( addr base ) "" { 29 30 31 constants clkactivity_l3_1_iclk_status width(1) "" { 32 CLKACTIVITY_L3_1_ICLK_0_r = 0 "Corresponding clock is definitely gated"; 33 CLKACTIVITY_L3_1_ICLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing"; 34 }; 35 36 constants clktrctrl_status width(2) "" { 37 CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 38 CLKTRCTRL_1_r = 1 "Reserved"; 39 CLKTRCTRL_2_r = 2 "Reserved"; 40 CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 41 }; 42 43 register cm_l3_1_clkstctrl addr(base, 0x0) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 44 _ 23 mbz; 45 clkactivity_l3_1_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_1_ICLK clock in the domain. [warm reset insensitive]"; 46 _ 6 mbz; 47 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L3_1 clock domain."; 48 }; 49 50 constants l4cfg_dyndep_status width(1) "" { 51 L4CFG_DYNDEP_1_r = 1 "Dependency is enabled"; 52 }; 53 54 register cm_l3_1_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from L3_1 domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 55 _ 4 mbz; 56 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 57 _ 11 mbz; 58 l4cfg_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L4CFG clock domain"; 59 _ 5 mbz; 60 l3_2_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_2 clock domain"; 61 _ 1 mbz; 62 memif_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards MEMIF clock domain"; 63 abe_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards ABE clock domain"; 64 _ 3 mbz; 65 }; 66 67 constants idlest_status width(2) "" { 68 IDLEST_0_r = 0 "Module is fully functional, including INTRCONN"; 69 IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 70 IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock"; 71 IDLEST_3_r = 3 "Module is disabled and cannot be accessed"; 72 }; 73 74 constants modulemode_status width(2) "" { 75 MODULEMODE_1_r = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 76 }; 77 78 register cm_l3_1_l3_1_clkctrl addr(base, 0x20) "This register manages the L3_1 clocks." { 79 _ 14 mbz; 80 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 81 _ 14 mbz; 82 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 83 }; 84 85 register cm_l3_2_clkstctrl addr(base, 0x100) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 86 _ 23 mbz; 87 clkactivity_l3_2_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_2_ICLK clock in the domain. [warm reset insensitive]"; 88 _ 6 mbz; 89 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L3_2 clock domain."; 90 }; 91 92 constants cam_dyndep_status width(1) "" { 93 CAM_DYNDEP_0_r = 0 "Dependency is disabled"; 94 }; 95 96 register cm_l3_2_dynamicdep addr(base, 0x108) "This register controls the dynamic domain dependencies from L3_2 domain towards 'target' domains. It is relevant only for domain having INTERCONN master port(s)." { 97 _ 4 mbz; 98 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 99 _ 9 mbz; 100 l4sec_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L4SEC clock domain"; 101 l4per_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L4PER clock domain"; 102 _ 2 mbz; 103 sgx_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards SGX clock domain"; 104 cam_dyndep 1 ro type(cam_dyndep_status) "Dynamic dependency towards ISS clock domain"; 105 dss_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards DSS clock domain"; 106 l3_init_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3INIT clock domain"; 107 _ 1 mbz; 108 l3_1_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_1 clock domain"; 109 _ 2 mbz; 110 ivahd_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards IVAHD clock domain"; 111 _ 1 mbz; 112 mpu_m3_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards CORTEXM3 clock domain"; 113 }; 114 115 register cm_l3_2_l3_2_clkctrl addr(base, 0x120) "This register manages the L3_2 clocks." { 116 _ 14 mbz; 117 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 118 _ 14 mbz; 119 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 120 }; 121 122 constants modulemode_status1 width(2) "" { 123 MODULEMODE_0 = 0 "Module is temporarily disabled by software. Interconnect access to module are stalled. Can be used to change timing parameter of GPMC module."; 124 MODULEMODE_1 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 125 MODULEMODE_2_r = 2 "Reserved"; 126 MODULEMODE_3_r = 3 "Reserved"; 127 }; 128 129 register cm_l3_2_gpmc_clkctrl addr(base, 0x128) "This register manages the GPMC clocks." { 130 _ 14 mbz; 131 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 132 _ 14 mbz; 133 modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed."; 134 }; 135 136 register cm_l3_2_ocmc_ram_clkctrl addr(base, 0x130) "This register manages the OCMC_RAM clocks." { 137 _ 14 mbz; 138 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 139 _ 14 mbz; 140 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 141 }; 142 143 constants clktrctrl_status1 width(2) "" { 144 CLKTRCTRL_0_2 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 145 CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain."; 146 CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 147 CLKTRCTRL_3_2 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 148 }; 149 150 register cm_mpu_m3_clkstctrl addr(base, 0x200) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 151 _ 23 mbz; 152 clkactivity_mpu_m3_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the MPU_M3_CLK clock in the domain. [warm reset insensitive]"; 153 _ 6 mbz; 154 clktrctrl 2 rw type(clktrctrl_status1) "Controls the clock state transition of the MPU_A3 clock domain."; 155 }; 156 157 constants l4wkup_statdep_status width(1) "" { 158 L4WKUP_STATDEP_0 = 0 "Dependency is disabled"; 159 L4WKUP_STATDEP_1 = 1 "Dependency is enabled"; 160 }; 161 162 register cm_mpu_m3_staticdep addr(base, 0x204) "This register controls the static domain dependencies from MPU_M3 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." { 163 _ 15 mbz; 164 alwoncore_statdep 1 ro type(cam_dyndep_status) "Static dependency towards ALWONCORE clock domain"; 165 l4wkup_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4WKUP clock domain"; 166 l4sec_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4SEC clock domain"; 167 l4per_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4PER clock domain"; 168 l4cfg_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4CFG clock domain"; 169 sdma_statdep 1 ro type(l4wkup_statdep_status) "Static dependency towards SDMA clock domain"; 170 sgx_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards SGX clock domain"; 171 iss_statdep 1 ro type(l4wkup_statdep_status) "Static dependency towards ISS clock domain"; 172 dss_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards DSS clock domain"; 173 l3init_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3INIT clock domain"; 174 l3_2_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_2 clock domain"; 175 l3_1_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_1 clock domain"; 176 memif_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MEMIF clock domain"; 177 abe_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards ABE clock domain"; 178 ivahd_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards IVAHD clock domain"; 179 dsp_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards DSP clock domain"; 180 _ 1 mbz; 181 }; 182 183 register cm_mpu_m3_dynamicdep addr(base, 0x208) "This register controls the dynamic domain depedencies from MPU_A3 domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 184 _ 4 mbz; 185 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 186 _ 14 mbz; 187 cam_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards ISS clock domain"; 188 _ 2 mbz; 189 l3_2_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_2 clock domain"; 190 _ 6 mbz; 191 }; 192 193 constants stbyst_status width(1) "" { 194 STBYST_0_r = 0 "Module is functional (not in standby)"; 195 STBYST_1_r = 1 "Module is in standby"; 196 }; 197 198 constants modulemode_status2 width(2) "" { 199 MODULEMODE_0_1 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup)."; 200 MODULEMODE_1_1 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 201 MODULEMODE_2_r_1 = 2 "Reserved"; 202 MODULEMODE_3_r_1 = 3 "Reserved"; 203 }; 204 205 register cm_mpu_m3_mpu_m3_clkctrl addr(base, 0x220) "This register manages the MPU_A3 clocks." { 206 _ 13 mbz; 207 stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]"; 208 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 209 _ 14 mbz; 210 modulemode 2 rw type(modulemode_status2) "Control the way mandatory clocks are managed."; 211 }; 212 213 constants clktrctrl_status2 width(2) "" { 214 CLKTRCTRL_0_3 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 215 CLKTRCTRL_1_r_2 = 1 "Reserved"; 216 CLKTRCTRL_2_1 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 217 CLKTRCTRL_3_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 218 }; 219 220 register cm_sdma_clkstctrl addr(base, 0x300) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 221 _ 23 mbz; 222 clkactivity_dma_l3_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMA_L3_ICLK clock in the domain. [warm reset insensitive]"; 223 _ 6 mbz; 224 clktrctrl 2 rw type(clktrctrl_status2) "Controls the clock state transition of the SDMA clock domain."; 225 }; 226 227 register cm_sdma_staticdep addr(base, 0x304) "This register controls the static domain dependencies from SDMA domain towards 'target' domains. It is relevant only for domain having system initiator(s)." { 228 _ 16 mbz; 229 l4wkup_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4WKUP clock domain"; 230 l4sec_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4SEC clock domain"; 231 l4per_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4PER clock domain"; 232 l4cfg_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4CFG clock domain"; 233 _ 2 mbz; 234 iss_statdep 1 ro type(l4wkup_statdep_status) "Static dependency towards ISS clock domain"; 235 dss_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards DSS clock domain"; 236 l3init_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3INIT clock domain"; 237 l3_2_statdep 1 ro type(l4cfg_dyndep_status) "Static dependency towards L3_2 clock domain"; 238 l3_1_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_1 clock domain"; 239 memif_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MEMIF clock domain"; 240 abe_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards ABE clock domain"; 241 ivahd_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards IVAHD clock domain"; 242 _ 1 mbz; 243 mpu_m3_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MPU_A3 clock domain"; 244 }; 245 246 register cm_sdma_dynamicdep addr(base, 0x308) "This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 247 _ 25 mbz; 248 l3_2_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards L3_2 clock domain"; 249 _ 6 mbz; 250 }; 251 252 register cm_sdma_sdma_clkctrl addr(base, 0x320) "This register manages the SDMA clocks." { 253 _ 13 mbz; 254 stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]"; 255 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 256 _ 14 mbz; 257 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 258 }; 259 260 register cm_memif_clkstctrl addr(base, 0x400) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 261 _ 21 mbz; 262 clkactivity_phy_root_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PHY_ROOT_CLK clock in the domain. [warm reset insensitive]"; 263 clkactivity_dll_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DLL_CLK clock in the domain. [warm reset insensitive]"; 264 clkactivity_l3_emif_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_EMIF_ICLK clock in the domain. [warm reset insensitive]"; 265 _ 6 mbz; 266 clktrctrl 2 rw type(clktrctrl_status2) "Controls the clock state transition of the MEMIF clock domain."; 267 }; 268 269 register cm_memif_dmm_clkctrl addr(base, 0x420) "This register manages the DMM clocks." { 270 _ 14 mbz; 271 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 272 _ 14 mbz; 273 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 274 }; 275 276 register cm_memif_emif_fw_clkctrl addr(base, 0x428) "This register manages the EMIF_FW clocks." { 277 _ 14 mbz; 278 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 279 _ 14 mbz; 280 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 281 }; 282 283 constants modulemode_status3 width(2) "" { 284 MODULEMODE_0_2 = 0 "Module is temporarily disabled by software. Interconnect access to module are stalled. Can be used to change timing parameter of EMIF1 module."; 285 MODULEMODE_1_2 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 286 MODULEMODE_2_r_2 = 2 "Reserved"; 287 MODULEMODE_3_r_2 = 3 "Reserved"; 288 }; 289 290 register cm_memif_emif_1_clkctrl addr(base, 0x430) "This register manages the EMIF_1 clocks." { 291 _ 14 mbz; 292 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 293 _ 14 mbz; 294 modulemode 2 rw type(modulemode_status3) "Control the way mandatory clocks are managed."; 295 }; 296 297 constants modulemode_status4 width(2) "" { 298 MODULEMODE_0_3 = 0 "Module is temporarily disabled by software. Interconnect access to module are stalled. Can be used to change timing parameter of EMIF2 module."; 299 MODULEMODE_1_3 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 300 MODULEMODE_2_r_3 = 2 "Reserved"; 301 MODULEMODE_3_r_3 = 3 "Reserved"; 302 }; 303 304 register cm_memif_emif_2_clkctrl addr(base, 0x438) "This register manages the EMIF_2 clocks." { 305 _ 14 mbz; 306 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 307 _ 14 mbz; 308 modulemode 2 rw type(modulemode_status4) "Control the way mandatory clocks are managed."; 309 }; 310 311 constants optfclken_dll_clk_status width(1) "" { 312 OPTFCLKEN_DLL_CLK_0 = 0 "Optional functional clock is disabled. DLL_CLK can be gated when MEMIF domain performs sleep transition"; 313 OPTFCLKEN_DLL_CLK_1 = 1 "Optional functional clock is enabled. DLL_CLK is garantied to not be gated if already running."; 314 }; 315 316 register cm_memif_dll_clkctrl addr(base, 0x440) "This register manages the DLL clock." { 317 _ 23 mbz; 318 optfclken_dll_clk 1 rw type(optfclken_dll_clk_status) "Optional functional clock control."; 319 _ 8 mbz; 320 }; 321 322 register cm_c2c_clkstctrl addr(base, 0x500) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 323 _ 21 mbz; 324 clkactivity_l3x2_c2c_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the C2C_L3X2_ICLK clock in the domain. [warm reset insensitive]"; 325 clkactivity_l4_c2c_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L4_C2C_ICLK clock in the domain. [warm reset insensitive]"; 326 clkactivity_l3_c2c_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_C2C_ICLK clock in the domain. [warm reset insensitive]"; 327 _ 6 mbz; 328 clktrctrl 2 rw type(clktrctrl_status2) "Controls the clock state transition of the C2C clock domain."; 329 }; 330 331 register cm_c2c_staticdep addr(base, 0x504) "This register controls the static domain depedencies from C2C domain towards 'target' domains. It is relevant only for domain having system initiator(s)." { 332 _ 18 mbz; 333 l4per_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4PER clock domain"; 334 l4cfg_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4CFG clock domain"; 335 _ 4 mbz; 336 l3init_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3INIT clock domain"; 337 l3_2_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_2 clock domain"; 338 l3_1_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_1 clock domain"; 339 memif_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MEMIF clock domain"; 340 abe_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards ABE clock domain"; 341 ivahd_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards IVAHD clock domain"; 342 _ 2 mbz; 343 }; 344 345 register cm_c2c_dynamicdep addr(base, 0x508) "This register controls the dynamic domain depedencies from C2C domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 346 _ 4 mbz; 347 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 348 _ 17 mbz; 349 l3_2_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_2 clock domain"; 350 _ 1 mbz; 351 memif_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards MEMIF clock domain"; 352 _ 4 mbz; 353 }; 354 355 constants idlest_status1 width(2) "" { 356 IDLEST_0_r_10 = 0 "C2C interface is in functional state"; 357 IDLEST_1_r_10 = 1 "C2C interface is in a transitory state"; 358 IDLEST_2_r_10 = 2 "C2C interface is in IDLE state"; 359 }; 360 361 register cm_c2c_c2c_clkctrl addr(base, 0x520) "This register manages the C2C clocks." { 362 _ 13 mbz; 363 stbyst 1 ro type(stbyst_status) "C2C module standby status. [warm reset insensitive]"; 364 idlest 2 ro type(idlest_status1) "C2C interface idle status. [warm reset insensitive]"; 365 _ 14 mbz; 366 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 367 }; 368 369 register cm_c2c_c2c_fw_clkctrl addr(base, 0x530) "This register manages the C2C_FW clocks." { 370 _ 14 mbz; 371 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 372 _ 14 mbz; 373 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 374 }; 375 376 constants clkactivity_cfg_l4_iclk_status width(1) "" { 377 CLKACTIVITY_CFG_L4_ICLK_0_r = 0 "Corresponding clock is gated."; 378 CLKACTIVITY_CFG_L4_ICLK_1_r = 1 "Corresponding clock is running or gating/ungating; transition is ongoing."; 379 }; 380 381 register cm_l4cfg_clkstctrl addr(base, 0x600) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 382 _ 22 mbz; 383 clkactivity_core_ts_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the CORE_TS_FCLK clock in the domain. [warm reset insensitive]"; 384 clkactivity_cfg_l4_iclk 1 ro type(clkactivity_cfg_l4_iclk_status) "This field indicates the state of the CFG_L4_ICLK clock in the domain. [warm reset insensitive]"; 385 _ 6 mbz; 386 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L4CFG clock domain."; 387 }; 388 389 register cm_l4cfg_dynamicdep addr(base, 0x608) "This register controls the dynamic domain depedencies from L4_CFG domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 390 _ 4 mbz; 391 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 392 _ 4 mbz; 393 mpu_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards MPU clock domain"; 394 c2c_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards C2C clock domain"; 395 _ 1 rsvd; 396 alwoncore_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards ALWONCORE clock domain"; 397 l4wkup_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L4WKUP clock domain"; 398 _ 3 mbz; 399 sdma_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards SDMA clock domain"; 400 _ 1 mbz; 401 cam_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards ISS clock domain"; 402 dss_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards DSS clock domain"; 403 l3_init_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3INIT clock domain"; 404 l3_2_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_2 clock domain"; 405 l3_1_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards L3_1 clock domain"; 406 memif_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards MEMIF clock domain"; 407 _ 2 mbz; 408 dsp_dyndep 1 ro type(l4cfg_dyndep_status) "Dynamic dependency towards DSP clock domain"; 409 _ 1 mbz; 410 }; 411 412 register cm_l4cfg_l4_cfg_clkctrl addr(base, 0x620) "This register manages the L4_CFG clocks." { 413 _ 14 mbz; 414 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 415 _ 14 mbz; 416 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 417 }; 418 419 register cm_l4cfg_spinlock_clkctrl addr(base, 0x628) "This register manages the HW_SEM clocks." { 420 _ 14 mbz; 421 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 422 _ 14 mbz; 423 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 424 }; 425 426 register cm_l4cfg_mailbox_clkctrl addr(base, 0x630) "This register manages the MAILBOX clocks." { 427 _ 14 mbz; 428 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 429 _ 14 mbz; 430 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 431 }; 432 433 register cm_l4cfg_sar_rom_clkctrl addr(base, 0x638) "This register manages the SAR_ROM clocks." { 434 _ 14 mbz; 435 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 436 _ 14 mbz; 437 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 438 }; 439 440 register cm_l3instr_clkstctrl addr(base, 0x700) "This register enables the domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 441 _ 23 mbz; 442 clkactivity_l3_instr_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_INSTR_GICLK clock in the domain. [warm reset insensitive]"; 443 _ 6 mbz; 444 clktrctrl 2 ro type(clktrctrl_status) "Controls the clock state transition of the L3INSTR clock domain."; 445 }; 446 447 register cm_l3instr_l3_3_clkctrl addr(base, 0x720) "This register manages the L3_3 clocks. [warm reset insensitive]" { 448 _ 14 mbz; 449 idlest 2 ro type(idlest_status) "Module idle status."; 450 _ 14 mbz; 451 modulemode 2 rw type(modulemode_status2) "Control the way mandatory clocks are managed."; 452 }; 453 454 register cm_l3instr_l3_instr_clkctrl addr(base, 0x728) "This register manages the L3 INSTRUMENTATION clocks. [warm reset insensitive]" { 455 _ 14 mbz; 456 idlest 2 ro type(idlest_status) "Module idle status."; 457 _ 14 mbz; 458 modulemode 2 rw type(modulemode_status2) "Control the way mandatory clocks are managed."; 459 }; 460 461 constants idlest_status2 width(2) "" { 462 IDLEST_3_r_17 = 3 "Module is disabled and cannot be accessed"; 463 IDLEST_2_r_18 = 2 "Module is in idle mode (only Interconnect part). It is functional if using separate functional clock"; 464 IDLEST_1_r_18 = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 465 IDLEST_0_r_18 = 0 "Module is fully functional, including Interconnect"; 466 }; 467 468 constants modulemode_status5 width(2) "" { 469 MODULEMODE_0_6 = 0 "Module is disable by software. Any Interconnect access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup)."; 470 MODULEMODE_1_6 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any Interconnect access to module is always granted. Module clocks may be gated according to the clock domain state."; 471 MODULEMODE_2_r_6 = 2 "Reserved"; 472 MODULEMODE_3_r_6 = 3 "Reserved"; 473 }; 474 475 register cm_l3instr_ocp_wp1_clkctrl addr(base, 0x740) "This register manages the OCP_WP1 clocks. [warm reset insensitive]" { 476 _ 14 mbz; 477 idlest 2 ro type(idlest_status2) "Module idle status."; 478 _ 14 mbz; 479 modulemode 2 rw type(modulemode_status5) "Control the way mandatory clocks are managed."; 480 }; 481};