1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_clk3_statcoll_lat0.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_clk3_statcoll_lat0 msbfirst ( addr base ) "" { 29 30 31 constants stdhosthdr_corereg_vendorcode_status width(1) "" { 32 STDHOSTHDR_COREREG_VENDORCODE_0_r = 0 "Third-party vendor."; 33 STDHOSTHDR_COREREG_VENDORCODE_1_r = 1 ""; 34 }; 35 36 register l3_stcol_stdhosthdr_corereg addr(base, 0x0) "" { 37 _ 10 mbz; 38 stdhosthdr_corereg_corecode 6 ro "The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A."; 39 _ 15 mbz; 40 stdhosthdr_corereg_vendorcode 1 ro type(stdhosthdr_corereg_vendorcode_status) "The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1."; 41 }; 42 43 register l3_stcol_stdhosthdr_versionreg addr(base, 0x4) "" { 44 stdhosthdr_versionreg_revisionid 8 ro "The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0."; 45 stdhosthdr_versionreg_coreparamschecksum 24 ro "Reserved. Type: Reserved. Reset value: Reserved."; 46 }; 47 48 register l3_stcol_en addr(base, 0x8) "" { 49 _ 31 mbz; 50 en 1 rw "Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0."; 51 }; 52 53 register l3_stcol_soften addr(base, 0xC) "" { 54 _ 31 mbz; 55 soften 1 rw "Software enable for performance monitoring Type: Control. Reset value: 0x0."; 56 }; 57 58 register l3_stcol_trigen addr(base, 0x14) "" { 59 _ 31 mbz; 60 trigen 1 rw "TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0."; 61 }; 62 63 constants reqevt_status width(4) "" { 64 REQEVT_0 = 0 "Collect is disabled default value"; 65 REQEVT_1 = 1 "Collect all event: hit always (cycle)"; 66 REQEVT_2 = 2 "Collect transfers: actually used cycle for transferring aN NTTP word"; 67 REQEVT_3 = 3 "Collect wait cycle: transfer has been delayed by source"; 68 REQEVT_4 = 4 "Collect busy: transfer has been delayed by destination"; 69 REQEVT_5 = 5 "Collect packet: new packet start"; 70 REQEVT_6 = 6 "Collect data: data cycle transfer, write for requests, read for responses"; 71 REQEVT_7 = 7 "Collect idles: transfer is not initiated by source"; 72 REQEVT_8 = 8 "Collect latency: hit when actually detecting debug bit on response links"; 73 }; 74 75 register l3_stcol_reqevt addr(base, 0x18) "" { 76 _ 28 mbz; 77 reqevt 4 rw type(reqevt_status) "Req event select Type: Control. Reset value: 0x0."; 78 }; 79 80 register l3_stcol_rspevt addr(base, 0x1C) "" { 81 _ 28 mbz; 82 rspevt 4 rw type(reqevt_status) "Rsp event select Type: Control. Reset value: 0x0."; 83 }; 84 85 register l3_stcol_evtmux_sel0 addr(base, 0x20) "" { 86 _ 29 mbz; 87 evtmux_sel0 3 rw "The select of the mux 0 Type: Control. Reset value: 0x0."; 88 }; 89 90 register l3_stcol_evtmux_sel1 addr(base, 0x24) "" { 91 _ 29 mbz; 92 evtmux_sel1 3 rw "The select of the mux 1 Type: Control. Reset value: 0x0."; 93 }; 94 95 register l3_stcol_evtmux_sel2 addr(base, 0x28) "" { 96 _ 29 mbz; 97 evtmux_sel2 3 rw "The select of the mux 2 Type: Control. Reset value: 0x0."; 98 }; 99 100 register l3_stcol_evtmux_sel3 addr(base, 0x2C) "" { 101 _ 29 mbz; 102 evtmux_sel3 3 rw "The select of the mux 3 Type: Control. Reset value: 0x0."; 103 }; 104 105 register l3_stcol_dump_identifier addr(base, 0x40) "" { 106 _ 30 mbz; 107 dump_identifier 2 ro "Probe identifier Type: Control. Reset value: 0x0."; 108 }; 109 110 register l3_stcol_dump_collecttime addr(base, 0x44) "" { 111 _ 16 mbz; 112 dump_collecttime 16 rw "Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0."; 113 }; 114 115 register l3_stcol_dump_slvaddr addr(base, 0x48) "" { 116 _ 27 mbz; 117 dump_slvaddr 5 ro "Dump slave address Type: Control. Reset value: 0x19."; 118 }; 119 120 register l3_stcol_dump_mstaddr addr(base, 0x4C) "" { 121 _ 24 mbz; 122 dump_mstaddr 8 ro "Dump master address Type: Control. Reset value: 0xE0."; 123 }; 124 125 register l3_stcol_dump_slvofs rw addr(base, 0x50) "" type(uint32); 126 127 register l3_stcol_dump_manual addr(base, 0x54) "" { 128 _ 31 mbz; 129 dump_manual 1 rw "Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0."; 130 }; 131 132 register l3_stcol_dump_send addr(base, 0x58) "" { 133 _ 31 mbz; 134 dump_send 1 rw "In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0."; 135 }; 136 137 register l3_stcol_filter_i_globalen addr(base, 0xAC) "" { 138 _ 31 mbz; 139 filter_i_globalen 1 rw "Filter global enable Type: Control. Reset value: 0x0."; 140 }; 141 142 register l3_stcol_filter_i_en_k addr(base, 0xBC) "" { 143 _ 31 mbz; 144 filter_i_en0 1 rw "Enable filter stage 0 Type: Control. Reset value: 0x0."; 145 }; 146 147 register l3_stcol_filter_i_mask_m_rd addr(base, 0xC0) "" { 148 _ 31 mbz; 149 filter_i_mask_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0."; 150 }; 151 152 register l3_stcol_filter_i_mask_m_wr addr(base, 0xC4) "" { 153 _ 31 mbz; 154 filter_i_mask_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0."; 155 }; 156 157 register l3_stcol_filter_i_mask_m_mstaddr addr(base, 0xC8) "" { 158 _ 24 mbz; 159 filter_i_mask_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0."; 160 }; 161 162 register l3_stcol_filter_i_mask_m_err addr(base, 0xD0) "" { 163 _ 31 mbz; 164 filter_i_mask_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0."; 165 }; 166 167 register l3_stcol_filter_i_match_m_rd addr(base, 0xE0) "" { 168 _ 31 mbz; 169 filter_i_match_m_rd 1 rw "Mask/Match of Rd Type: Control. Reset value: 0x0."; 170 }; 171 172 register l3_stcol_filter_i_match_m_wr addr(base, 0xE4) "" { 173 _ 31 mbz; 174 filter_i_match_m_wr 1 rw "Mask/Match of Wr Type: Control. Reset value: 0x0."; 175 }; 176 177 register l3_stcol_filter_i_match_m_mstaddr addr(base, 0xE8) "" { 178 _ 24 mbz; 179 filter_i_match_m_mstaddr 8 rw "Mask/Match of MstAddr Type: Control. Reset value: 0x0."; 180 }; 181 182 register l3_stcol_filter_i_match_m_err addr(base, 0xF0) "" { 183 _ 31 mbz; 184 filter_i_match_m_err 1 rw "Mask/Match of Err Type: Control. Reset value: 0x0."; 185 }; 186 187 register l3_stcol_op_i_threshold_minval addr(base, 0x1F0) "" { 188 _ 20 mbz; 189 op_i_threshold_minval 12 rw "Min value Type: Control. Reset value: 0x0."; 190 }; 191 192 register l3_stcol_op_i_threshold_maxval addr(base, 0x1F4) "" { 193 _ 20 mbz; 194 op_i_threshold_maxval 12 rw "Max value Type: Control. Reset value: 0x0."; 195 }; 196 197 constants op_i_evtinfosel_status width(2) "" { 198 OP_i_EVTINFOSEL_0 = 0 "Select len from event info list"; 199 OP_i_EVTINFOSEL_1 = 1 "Select pressure if available from event info list"; 200 OP_i_EVTINFOSEL_2 = 2 "Select latency if available from event info list"; 201 }; 202 203 register l3_stcol_op_i_evtinfosel addr(base, 0x1F8) "" { 204 _ 30 mbz; 205 op_i_evtinfosel 2 rw type(op_i_evtinfosel_status) "Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0."; 206 }; 207 208 constants op_i_sel_status width(4) "" { 209 OP_i_SEL_0 = 0 "Increment counter on each mask/match filter hit"; 210 OP_i_SEL_1 = 1 "Increment counter on each min/max level hit"; 211 OP_i_SEL_2 = 2 "Add to counter the selected event info value (len/press or latency)"; 212 OP_i_SEL_3 = 3 "increment counter when all filter event hits (And(Fi))"; 213 OP_i_SEL_4 = 4 "Increment counter if any of filter event hits (Or(Fi))"; 214 OP_i_SEL_5 = 5 "Add to counter the number of current request event that hit"; 215 OP_i_SEL_6 = 6 "Add to counter the number of current response event that hit"; 216 OP_i_SEL_7 = 7 "Add to counter the number of all event that hit"; 217 OP_i_SEL_8 = 8 "Increment counter on each selected external event hit"; 218 }; 219 220 register l3_stcol_op_i_sel addr(base, 0x1FC) "" { 221 _ 28 mbz; 222 op_i_sel 4 rw type(op_i_sel_status) "Select logical operation Type: Control. Reset value: 0x0."; 223 }; 224};