1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_ckgen_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_ckgen_prm msbfirst ( addr base ) "" { 29 30 31 constants clksel_status width(1) "" { 32 CLKSEL_0 = 0 "Select SYS_CLK divided by 1"; 33 CLKSEL_1 = 1 "Select SYS_CLK divided by 2 Must be used for SYS_CLK > 26 MHz"; 34 }; 35 36 register cm_abe_dss_sys_clksel addr(base, 0x0) "Select the SYS CLK for ABE and DSS subsystems. [warm reset insensitive]" { 37 _ 31 mbz; 38 clksel 1 rw type(clksel_status) "Selects the divider value"; 39 }; 40 41 constants clksel_status1 width(1) "" { 42 CLKSEL_0_1 = 0 "Selects SYS_CLK for L4WKUP_ICLK Selects SYS_CLK for ABE_DPLL_BYPASS_CLK"; 43 CLKSEL_1_1 = 1 "Selects ABE_LP_CLK for L4WKUP_ICLK Selects 32K_FCLK for ABE_DPLL_BYPASS_CLK"; 44 }; 45 46 register cm_l4_wkup_clksel addr(base, 0x8) "Control the functional clock source of L4_WKUP, PRM and Smart Reflex functional clock." { 47 _ 31 mbz; 48 clksel 1 rw type(clksel_status1) "Select the clock source for L4WKUP_ICLK and for ABE_DPLL_BYPASS_CLK clocks."; 49 }; 50 51 constants clksel_status2 width(1) "" { 52 CLKSEL_0_2 = 0 "Selects SYS_CLK"; 53 CLKSEL_1_2 = 1 "Selects SYS_32K"; 54 }; 55 56 register cm_abe_pll_ref_clksel addr(base, 0xC) "Control the source of the reference clock for DPLL_ABE" { 57 _ 31 mbz; 58 clksel 1 rw type(clksel_status2) "Select the source for the DPLL_ABE reference clock."; 59 }; 60 61 constants sys_clksel_status width(3) "" { 62 SYS_CLKSEL_0 = 0 "Uninitialized"; 63 SYS_CLKSEL_1 = 1 "Input clock is 12 MHz"; 64 SYS_CLKSEL_2 = 2 "Reserved"; 65 SYS_CLKSEL_3 = 3 "Input clock is 16.8 MHz"; 66 SYS_CLKSEL_4 = 4 "Input clock is 19.2 MHz"; 67 SYS_CLKSEL_5 = 5 "Input clock is 26 MHz"; 68 SYS_CLKSEL_6 = 6 "Reserved"; 69 SYS_CLKSEL_7 = 7 "Input clock is 38.4 MHz"; 70 }; 71 72 register cm_sys_clksel addr(base, 0x10) "Software sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK. [warm reset insensitive]" { 73 _ 29 mbz; 74 sys_clksel 3 rw type(sys_clksel_status) "System clock input selection."; 75 }; 76};