1/*
2 * Copyright (c) 2014, University of Washington. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * megaraid.dev
11 *
12 * DESCRIPTION: LSI MegaRAID Controller
13 *
14 * From the FreeBSD driver.
15 */
16
17device megaraid msbfirst ( addr base ) "LSI MegaRAID Controller" {
18       register doorbell rw addr(base, 0x0) "Doorbell" type(uint32);
19       register fusion_seq_offset rw addr(base, 0x4) "Fusion SEQ Offset" type (uint32);
20       register fusion_host_diag rw addr(base, 0x8) "Fusion Host Diag" type (uint32);
21
22       register inbound_msg_0 rw addr(base, 0x10) "Inbound msg 0" type (uint32);
23       register inbound_msg_1 rw addr(base, 0x14) "Inbound msg 0" type (uint32);
24       register outbound_msg_0 rw addr(base, 0x18) "Outbound msg 0" type (uint32);
25       register outbound_msg_1 rw addr(base, 0x1c) "Outbound msg 1" type (uint32);
26
27       register inbound_doorbell rw addr(base, 0x20) "Inbound doorbell" type (uint32);
28       register inbound_intr_status rw addr(base, 0x24) "Inbound interrupt status" type (uint32);
29       register inbound_intr_mask rw addr(base, 0x28) "Inbound interrupt mask" type (uint32);
30       register outbound_doorbell rw addr(base, 0x2c) "Outbound doorbell" type (uint32);
31       register outbound_intr_status rw addr(base, 0x30) "Outbound interrupt status" type (uint32);
32       register outbound_intr_mask rw addr(base, 0x34) "Outbound interrupt mask" type (uint32);
33
34       register inbound_queue_port rw addr(base, 0x40) "Inbound queue port" type (uint32);
35       register outbound_queue_port rw addr(base, 0x44) "Outbound queue port" type (uint32);
36
37       register reply_post_host_index rw addr(base, 0x6c) "Reply post host index" type (uint32);
38
39       register outbound_doorbell_clear rw addr(base, 0xa0) "Outbound doorbell clear" type (uint32);
40
41       constants state "Controller state" {
42         state_undefined	   = 0x0  "Undefined";
43	 state_bb_init		   = 0x1  "BB Init";
44	 state_fw_init		   = 0x4  "FW Init";
45	 state_wait_handshake	   = 0x6  "Wait handshake";
46	 state_fw_init_2	   = 0x7  "FW Init 2";
47	 state_device_scane	   = 0x8  "Device scan";
48	 state_boot_msg_pending	   = 0x9  "Boot message pending";
49	 state_flush_cache	   = 0xa  "Flush cache";
50	 state_ready		   = 0xb  "Ready";
51	 state_operational	   = 0xc  "Operational";
52	 state_fault		   = 0xf  "Fault";
53       };
54
55       register status ro addr(base, 0xb0) "Device status" {
56         state	     4  type(state) "Controller status";
57	 _	     4;
58	 sge	     8;
59	 max_cmds    16 "Max. # of commands";
60       };
61
62       register outbound_scratch_pad_2 rw addr(base, 0xb4) "Outbound scratch pad #2" type (uint32);
63
64       register inbound_low_queue_port rw addr(base, 0xc0) "Inbound low queue port" type (uint32);
65       register inbound_high_queue_port rw addr(base, 0xc4) "Inbound high queue port" type (uint32);
66};
67