1/*
2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * lpc_rtc.dev
11 *
12 * DESCRIPTION: Legacy real-time clock registers on the LPC (low pin count, or
13 *              legacy PC) bridge function of a typical Intel IHC
14 *              (Southbridge).    
15 * 
16 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
17 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 
18 * 
19 */
20
21device lpc_rtc (io base) "LPC Real-Time Clock and CMOS RAM" {
22  
23  // 21.6
24  register ndx rw io(base, 0x70) "Standard index" type(uint8);
25  register target rw io(base, 0x71) "Standard target" type(uint8);
26
27  register endx rw io(base, 0x72) "Extended index" type(uint8);
28  register etarget rw io(base, 0x73) "Extended target" type(uint8);
29
30  // 21.6.2
31  constants sndx "Standard index values" { 
32    seconds	= 0x0 "Seconds";
33    al_seconds	= 0x1 "Seconds alarm";
34    minutes	= 0x2 "Minutes";
35    al_minutes	= 0x3 "Minutes Alarm";
36    hours	= 0x4 "Hours";
37    al_hours	= 0x5 "Hours Alarm";
38    weekday	= 0x6 "Day of Week";
39    date	= 0x7 "Day of Month";
40    month	= 0x8 "Month";
41    year	= 0x9 "Year";
42    rega	= 0xa "Register A";
43    regb	= 0xb "Register B";
44    regc	= 0xc "Register C";
45    regd	= 0xd "Register D";
46  };
47
48  // 21.6.2.1
49  constants dcs "Division chain select" {
50    normal	= 0b010 "Normal operation";
51    divreset	= 0b110 "Divider reset";
52    divreset2	= 0b111 "Divider reset";
53    bypass15	= 0b101 "Bypass 15 stages";
54    bypass10	= 0b100 "Bypass 10 stages";
55    bypass5	= 0b011 "Bypass 5 stages";
56  };
57  
58  constants rate "Rate select" {
59    never	= 0b0000 "Interrupt never toggles";
60    ms3_90625_	= 0b0001 "3.90625 ms (duplicate)";
61    ms7_8125_	= 0b0010 "7.8125 ms (duplicate)";
62    us122_070	= 0b0011 "122.070 us";
63    us244_141	= 0b0100 "244.141 us";
64    us488_281	= 0b0101 "488.281 us";
65    us976_5625	= 0b0110 "976.5625 us";
66    ms1_953125	= 0b0111 "1.953125 ms";
67    ms3_906251	= 0b1000 "3.906251 ms";
68    ms7_8125	= 0b1001 "7.8125 ms";
69    ms15_625	= 0b1010 "15.625 ms";
70    ms31_25	= 0b1011 "31.25 ms";
71    ms62_5	= 0b1100 "62.5 ms";
72    ms125	= 0b1101 "125 ms";
73    ms250	= 0b1110 "250 ms";
74    ms500	= 0b1111 "500 ms";
75  };
76
77  register rega rw also io(base, 0x71) "Register A" {
78    rs		4 type(rate) "Rate select";
79    dv		3 type(dcs) "Divisioin chain select";
80    uip		1 "Update in progress";
81  };
82
83  // 26.6.2.2
84  register regb rw also io(base, 0x71) "General configuration" {
85    dse		1 "Daylight savings enable";
86    hourform	1 "Hour format";
87    dm		1 "Data mode (BCD/binary)";
88    sqwe	1 "Square wave enable";
89    uie		1 "Update-ended interrupt enable";
90    aie		1 "Alarm interrupt enable";
91    pie		1 "Periodic interrupt enable";
92    set		1 "Update cycle inhibit";
93  };
94
95  // 26.6.2.3
96  register regc ro also io(base, 0x71) "Flag register C" {
97    _		4;
98    uf		1 "Update-ended";
99    af		1 "Alarm";
100    pf		1 "Periodic interrupt";
101    irqf	1 "Interrupt request flag";
102  };
103
104  // 26.6.2.4
105  register regd rw also io(base, 0x71) "Flag register D" {
106    al_date	6 "Date alarm";
107    _		1;
108    vrt		1 mbz "Valid RAM and time";
109  };
110
111};
112
113
114  
115