1/* 2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpc_bridge.dev 11 * 12 * DESCRIPTION: this maps to the PCI configuration space of the LPC bridge 13 * and maps currently only the RCBA register, so that we can 14 * access the base of the chipset configuration which we need 15 * to implement the HPET timer 16 * 17 */ 18 19 20device lpc_bridge msbfirst ( pci base ) "LPC bridge PCI config space" { 21 register rcba rw pci( base, 0xf0 ) "RCBA" { 22 baseaddr 18 "Base Address"; 23 _ 13; 24 enable 1 "Enable"; 25 }; 26}; 27