1/*
2 * Copyright (c) 2009, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * ixp2800_icp_pic.dev
11 *
12 * DESCRIPTION: Primary interrupt controller for integrator/cp
13 *
14 * This is derived from:
15 *
16 * This is derived from the Intel IXP2400/IXP2800 Network Processor 
17 * Programmer's Reference Manual (November 2003), p. 541ff
18 *
19 */
20
21device ixp2800_icp_pic0 msbfirst ( addr base ) "IXP2800 Integrator Primary PIC"
22{
23   regtype source "Interrupt controller sources" {
24    _            4  "Reserved";
25    THD96_127_B  1  "THD_RAW_STATUS_B_3";
26    THD64_95_B	 1  "THD_RAW_STATUS_B_2";
27    THD32_63_B	 1  "THD_RAW_STATUS_B_1";
28    TH0_31_B 	 1  "THD_RAW_STATUS_B_0";
29    _		 4 "Reserved";
30    THD96_127_A  1  "THD_RAW_STATUS_A_3";
31    THD64_95_A	 1  "THD_RAW_STATUS_A_2";
32    THD32_63_A	 1  "THD_RAW_STATUS_A_1";
33    THD0_31_A 	 1  "THD_RAW_STATUS_A_0";
34    PCI_INT 	 1  "External PCI interrupt A & B";
35    ME_ATTN 	 1  "Microengine attention register";
36    PCI_DOORBELL 1  "A PCI device has set the doorbell interrupt";
37    DMA2_DONE 	 1  "Completion status from the DMA2 engine";
38    _		 1  "Reserved";
39    DMA0_DONE	 1  "Completion status from the DMA0 engine";
40    SP_FINT 	 1  "Slow Port interrupt";
41    PMU_INT 	 1  "PMU interrupt";
42    TIMER_UFLW	 4  "Timer underflow indicator";
43    GPIO_INT 	 1  "interrupt request from the GPIO unit";
44    UART_INT 	 1  "UART interrupt request";
45    ERROR_SUM 	 1  "OR of all interrupt bits in the ErrorStatus register";
46    SOFTINT 	 1  "Software Interrupt";
47   };
48
49   register IRQ_STATUS ro addr (base, 0x08) "IRQ masked interrupt status"
50       type(source);
51
52   register IRQ_RAW_STATUS ro addr (base, 0x00) "IRQ un-masked interrupt status"
53       type(source);
54
55   register IRQ_ENABLE ro addr (base, 0x10) "Return enabled IRQs"
56       type(source);
57
58   register IRQ_ENABLE_SET wo also addr (base, 0x10) "IRQ enable set"
59       type(source);
60
61   register IRQ_ENABLE_CLR wo addr (base, 0x18) "IRQ enable clear"
62       type(source);
63
64   register SOFT_INT addr (base, 0x54) "Software interrupt set" {
65     _	    	     31 ro "Reserved";
66     set	     1	rw "Set or read software interrupt";
67   };
68
69
70   register FIQ_STATUS ro addr (base, 0x04) "FIQ masked interrupt status"
71       type(source);
72
73   register FIQ_RAW_STATUS ro also addr (base, 0x00) "FIQ un-masked interrupt status"
74       type(source);
75
76   register FIQ_ENABLE ro also addr (base, 0x0c) "Return enabled FIQs"
77       type(source);
78
79   register FIQ_ENABLE_SET wo also addr (base, 0x0c) "FIQ enable set"
80       type(source);
81
82   register FIQ_ENABLE_CLR wo addr (base, 0x14) "FIQ enable clear"
83       type(source);
84
85};
86