1/* 2 * Copyright (c) 2014, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6 CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * ioat_dma.dev 11 * 12 * DESCRIPTION: Crystal Beach DMA Engine register descriptor 13 * 14 * This is derived from the "Intel (R) Xeon (R) Processor E5 v2 Product Family", 15 * chapter 8.4 & 8.5, "Device 4, Function 0-7, Crystal Beach DMA". 16 * 17 */ 18 19device ioat_dma_chan msbfirst ( addr chan_base ) "IOAT DMA (Crystal Beach) Channel registers" { 20 21 constants cmpl_status_shift "Completion Status Shift Value" { 22 compl_addr_shift = 0x6 "Completion addrss shift"; 23 }; 24 25 constants cmpl_status_mask width(64) "Completion Status Mask Value" { 26 status_mask = 0x3f "Mask for the status fields"; 27 }; 28 29 datatype compl_status msbfirst (64) "Completion writeback data area" { 30 compl_desc 58 "Completed Descriptor Address"; 31 _ 1 "Reserved"; 32 soft_err 1 "Software Error"; 33 unaff_err 1 "Unaffiliated error"; 34 status 3 "Channel status field"; 35 }; 36 37 constants chanctrl_snoop "Field values for Snoop Control" { 38 chanctrl_snoop_disabled = 0x1 "Disabled snooping"; 39 chanctrl_snoop_enabled = 0x0 "Enable snooping"; 40 }; 41 42 constants chanctrl_features "Field values for Channel Features" { 43 chanctrl_f_enable = 0x1 "Feature field is enabled"; 44 chanctrl_f_disable = 0x0 "Feature field is disabled"; 45 }; 46 47 /* 48 * 8.5.12 - Channel Control Register 49 * 50 * The Channel Control register controls the behavior of the DMA 51 * channel when specific events occur such as completion or errors. 52 */ 53 register ctrl addr(chan_base, 0x00) "Channel Control Register" { 54 _ 6 rsvd "Reserved"; 55 dca_en 1 rw "Direct Cache access enabled"; 56 in_use 1 rw "Channel is in use"; 57 _ 2 rsvd "reserved"; 58 snoop_ctrl 1 rw "Descriptor address snoop control"; 59 err_int_en 1 rw "Error Interrupt Enabled"; 60 err_abort 1 rw "Any Error Abort Enbled"; 61 err_cmp_en 1 rw "Error Completion Enabled"; 62 _ 1 rsvd "Reserved"; 63 intp_dis 1 rw1c "Interrupt disable"; 64 }; 65 66 /* 67 * 8.5.13 - DMA Compatibility Register 68 */ 69 register dma_comp ro addr(chan_base, 0x02) "DMA Compatibility Register" { 70 _ 13 "Reserved"; 71 v3 1 "Compatible with CB Version 3"; 72 v2 1 "Compatible with CB Version 2"; 73 v1 1 "NOT compatible with CB Version 1"; 74 }; 75 76 /* 77 * 8.5.14 - DMA Channel Command Register 78 * 79 * Setting more than one of these bits with the same write operation 80 * will result in an Fatal error affiliated. 81 */ 82 register cmd addr(chan_base, 0x84) "DMA Channel Command Register." { 83 _ 2 rsvd "Reserved"; 84 reset 1 rw "Reset DMA channel"; 85 resume 1 rw "resume"; 86 abort 1 rw "Abort"; 87 susp 1 rw "Suspend the DMA channel"; 88 append 1 rw "Append"; 89 start 1 rw "Start"; 90 }; 91 92 /* 93 * 8.5.15 - DMA Descriptor Count Register 94 * 95 * This is the absolute value of the number of valid descriptors in 96 * the chain. The hardware sets this register and an internal counter 97 * to zero whenever the CHAINADDR register is written. When this 98 * register does not equal the value of the internal register, the 99 * DMA channel processes descriptors, incrementing the internal 100 * counter each time that it completes (or skips) a descriptor.This 101 * register is RW if CHANCNT register is 1 otherwise this register is RO. 102 */ 103 register dmacount addr(chan_base, 0x06) "DMA Descriptor Count Register" 104 type(uint16); 105 106 107 constants trans_state "DMA Transfer States" { 108 trans_state_active = 0x0 "The transfer is active"; 109 trans_state_idle = 0x1 "Idle, All DMA transfers done"; 110 trans_state_susp = 0x2 "Suspended"; 111 trans_state_halt = 0x3 "Halted, operation aborted (error)"; 112 trans_state_armed = 0x4 "Armed State"; 113 }; 114 115 /* 116 * 8.5.16 - Channel Status Lo Register. 117 * 118 * The Channel Status Register records the address of the last 119 * descriptor completed by the DMA channel. Refer to Crystal Beach 120 * Architecture Specification 2.0 Rev 1.0 for special hardware 121 * requirements when software reads this register. 122 */ 123 register sts_lo ro addr(chan_base, 0x08) "Channel Status Lo Register." { 124 cmpdscaddr 26 "Uppder address of the last descriptor processed"; 125 _ 3 "Reserved"; 126 dma_trans_state 3 "DMA transfer State"; 127 }; 128 129 /* 130 * 8.5.17 - Channel Status Hi Register. 131 * 132 * The Channel Status Register records the address of the last 133 * descriptor completed by the DMA channel. Refer to Crystal Beach 134 * Architecture Specification for special hardware requirements when 135 * software reads this register. 136 * 137 * Also stores the address of the last processed descriptor 138 */ 139 register sts_hi ro addr(chan_base, 0x0c) "Channel Status Hi Register." 140 type(uint32); 141 142 /* 143 * 8.5.18 - Descriptor Chain Address Lo Register. 144 * 145 * This register is written by the processor to specify the first 146 * descriptor to be fetched by the DMA channel. 147 * 148 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 149 */ 150 register chainaddr_lo rw addr(chan_base, 0x10) "Descriptor Chain Address Lo Register." { 151 descaddr_lo 26 rw "Address of the first descriptor"; 152 _ 6 mbz "Must be zero"; 153 }; 154 155 /* 156 * 8.5.19 - Descriptor Chain Address Hi Register. 157 * 158 * This register is written by the processor to specify the first 159 * descriptor to be fetched by the DMA channel. 160 * 161 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 162 */ 163 register chainaddr_hi rw addr(chan_base, 0x14) "Descriptor Chain Address Hi Register." 164 type(uint32); 165 166 167 /* 168 * 8.5.20 - Channel Completion Address Lo Register. 169 * 170 * This register specifies the address where the DMA channel writes 171 * the completion status upon completion or an error condition i.e. 172 * it writes the contents of the CHANSTS register to the destination 173 * as pointed by the CHANCMP register. 174 * 175 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 176 */ 177 register cmpl_lo addr(chan_base, 0x18) "Channel Completion Address Lo Register." 178 type(uint32); 179 180 /* 181 * 8.5.21 - Channel Completion Address Hi Register. 182 * 183 * This register specifies the address where the DMA channel writes 184 * the completion status upon completion or an error condition i.e. 185 * it writes the contents of the CHANSTS register to the destination 186 * as pointed by the CHANCMP register. 187 * 188 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 189 */ 190 register cmpl_hi addr(chan_base, 0x1c) "Channel Completion Address Hi Register." 191 type(uint32); 192 193 /* 194 * 8.5.22 - Channel Error Register 195 * 196 * The Channel Error Register records the error conditions occurring 197 * within a given DMA channel. 198 */ 199 register err addr(chan_base, 0x28) "Channel Error Register" { 200 _ 13 rsvd "reserved"; 201 desccnterr 1 rw1cs "Descriptor Count error"; 202 xorqerr 1 rw1cs "Xor error"; 203 crc_err 1 rw1cs "CRC test failed"; 204 unaffilerr 1 ro "Unaffiliated Error"; 205 _ 1 rsvd "Unused error"; 206 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 207 cmpaddrerr 1 rw1cs "Completion Address error"; 208 desclenerr 1 rw1cs "Description length error"; 209 descctrlerr 1 rw1cs "Description control error"; 210 wrdataerr 1 rw1cs "Write data error"; 211 rddataerr 1 rw1cs "Read Data error"; 212 dmadataerr 1 rw1cs "DMA Data Parity error"; 213 cdataerr 1 rw1cs "Data parity error"; 214 chancmderr 1 rw1cs "Channel command error"; 215 chanaddr 1 rw1cs "Channel address value error"; 216 descerr 1 rw1cs "Descriptor error"; 217 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 218 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 219 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 220 }; 221 222 /* 223 * 8.5.23 - Channel Error Mask Register. 224 */ 225 register errmsk addr(chan_base, 0x2c) "Channel Error Mask Register." { 226 _ 13 rsvd "reserved"; 227 desccnterr 1 rw1cs "Descriptor Count error"; 228 xorqerr 1 rw1cs "Xor error"; 229 crc_err 1 rw1cs "CRC test failed"; 230 unaffilerr 1 ro "Unaffiliated Error"; 231 _ 1 rsvd "Unused error"; 232 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 233 cmpaddrerr 1 rw1cs "Completion Address error"; 234 desclenerr 1 rw1cs "Description length error"; 235 descctrlerr 1 rw1cs "Description control error"; 236 wrdataerr 1 rw1cs "Write data error"; 237 rddataerr 1 rw1cs "Read Data error"; 238 dmadataerr 1 rw1cs "DMA Data Parity error"; 239 cdataerr 1 rw1cs "Data parity error"; 240 chancmderr 1 rw1cs "Channel command error"; 241 chanaddr 1 rw1cs "Channel address value error"; 242 descerr 1 rw1cs "Descriptor error"; 243 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 244 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 245 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 246 }; 247 248 constants dcactrl_targets "Target CPU Values" { 249 dca_ctr_target_any = 0xffff "Any CPU as garget"; 250 }; 251 252 /* 253 * 8.5.24 - DCA Control Register 254 * 255 * This field is RW if CHANCNT register is 1 otherwise this register is RO 256 */ 257 register dcactrl addr(chan_base, 0x30) "DCA Control Register" { 258 _ 16 rsvd "Reserved"; 259 target_cpu 16 rw "Specifies the APCI ID of the target CPU for compl writes"; 260 }; 261}; 262 263