1/* 2 * Copyright (c) 2014, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6 CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * ioat_dma.dev 11 * 12 * DESCRIPTION: Crystal Beach DMA Engine register descriptor 13 * 14 * This is derived from the "Intel (R) Xeon (R) Processor E5 v2 Product Family", 15 * chapter 8.4 & 8.5, "Device 4, Function 0-7, Crystal Beach DMA". 16 * 17 */ 18 19device ioat_dma msbfirst ( addr cfg_base, addr bar ) "IOAT DMA (Crystal Beach) registers" { 20 21 /* 22 * Section 1.2.1.3, Table 1-1: Functions Specifically Handled by the Processor 23 */ 24 constants device_ids "Crystal Beach DMA device IDs" { 25 pci_vendorid = 0x8086 "Intel Corporation"; 26 pci_deviceid_0 = 0x0E20 "DMA Channel 0"; 27 pci_deviceid_1 = 0x0E21 "DMA Channel 1"; 28 pci_deviceid_2 = 0x0E22 "DMA Channel 2"; 29 pci_deviceid_3 = 0x0E23 "DMA Channel 3"; 30 pci_deviceid_4 = 0x0E24 "DMA Channel 4"; 31 pci_deviceid_5 = 0x0E25 "DMA Channel 5"; 32 pci_deviceid_6 = 0x0E26 "DMA Channel 6"; 33 pci_deviceid_7 = 0x0E27 "DMA Channel 7"; 34 }; 35 36 /* 37 * Shift amounts vor various registers 38 */ 39 constants shifts "Crystal Beach Shift Values" { 40 shift_baraddr = 14 "Base Address shift amount"; 41 shift_descaddr = 6 "Descriptor addres shift value"; 42 }; 43 44 45 46 /* 47 * ========================================================================= 48 * PCI Configuration and DMA capability registers 49 * 50 * Section 8.4: Crystal Beach DMA Registers 51 */ 52 53 /* 54 * 8.4.1 55 */ 56 register vid ro addr(cfg_base, 0x0) "Vendor Identification Number (0x8086)" 57 type(uint16); 58 59 /* 60 * 8.4.2 61 */ 62 register did ro addr(cfg_base, 0x2) "Device Identification Number" { 63 devid 8 "Device ID always 0x0E"; 64 function 8 "Function number: 0-7"; 65 }; 66 67 /* 68 * 8.4.3 69 */ 70 register pcicmd addr(cfg_base, 0x4) "PCI Command Register" { 71 _ 5 rsvd "reserved"; 72 intx_disable 1 rw ""; 73 _ 1 rsvd "Always reads zero"; 74 serre 1 ro ""; 75 _ 1 rsvd "Always reads zero"; 76 perre 1 ro ""; 77 _ 1 rsvd "Always reads zero"; 78 mwie 1 ro ""; 79 sce 1 ro ""; 80 bme 1 rw ""; 81 mse 1 rw ""; 82 iose 1 ro ""; 83 }; 84 85 /* 86 * 8.4.4 87 */ 88 register pcists addr(cfg_base, 0x6) "PCI Status Register" { 89 dpe 1 rw1c ""; 90 sse 1 ro ""; 91 rma 1 ro ""; 92 rta 1 ro ""; 93 sta 1 rw1c ""; 94 _ 2 rsvd "Always reads zero"; 95 mdpe 1 rw1c ""; 96 _ 3 rsvd "Always reads zero"; 97 caplist 1 ro "indicates the presence of a capabilities list structure"; 98 intxsts 1 ro ""; 99 _ 3 rsvd "reserved"; 100 }; 101 102 /* 103 * 8.4.5 / 8.4.6 104 */ 105 register rid_ccr ro addr(cfg_base, 0x8) "Revision ID and PCI Class" { 106 class 8 "Base class: Generic device"; 107 subclass 8 "Sub class: Generic device"; 108 rlpi 8 "Register level programming interface (set to 00)"; 109 rid 8 "Revision ID"; 110 }; 111 112 /* 113 * 8.4.7 114 */ 115 register clsr ro addr(cfg_base, 0xc) "Cache Line Size (always 64b)" 116 type(uint8); 117 118 /* 119 * 8.4.8 120 */ 121 register hdr ro addr(cfg_base, 0xe) "PCI Header Register" { 122 mfd 1 ro "Multifunction device (always 1)"; 123 cfglayout 1 ro "Configuration layout (always 0, endpoint)"; 124 _ 6 rsvd "reserved"; 125 }; 126 127 /* 128 * 8.4.9 Crystal Beach Base Address Register. 129 */ 130 register cb_bar addr(cfg_base, 0x10) "Crystal Beach Base Address Register" { 131 bar 50 rw "16 KB aligned 64-bit base address for MMIO regs"; 132 _ 10 rsvd "reserved"; 133 prefetch 1 ro "DMA registers are non-prefetchable (always 0)"; 134 bartype 2 ro "The DMA registers is 64-bit address space"; 135 memspace 1 ro "This Base Address Register indicates memory space."; 136 }; 137 138 /* 139 * 8.4.10 140 */ 141 register svid ro addr(cfg_base, 0x2c) "Vendor Identification Number (0x8086)" 142 type(uint16); 143 144 /* 145 * 8.4.11 146 */ 147 register sdid ro addr(cfg_base, 0x2e) "Subsystem Identification Number" 148 type(uint16); 149 150 /* 151 * 8.4.12 152 */ 153 register capptr ro addr(cfg_base, 0x34) "Capability Pointer (first cap structure)" 154 type(uint8); 155 156 /* 157 * 8.4.13 158 */ 159 register intl rw addr(cfg_base, 0x3c) "Interrupt Line (N/A)" 160 type(uint8); 161 162 /* 163 * 8.4.14 164 * 165 * The value of this register depends on the function number 166 * 0x1-0x4 167 */ 168 register intpin rw addr(cfg_base, 0x3d) "Interrupt pin (Function dependent)" 169 type(uint8); 170 171 /* 172 * 8.4.15 - This DEVCFG is for Function 0 only 173 */ 174 register devcfg addr(cfg_base, 0x60) "Device Configuration Register" { 175 numrd_xor 4 rw "Number of outstanding requests (set to 0 for max)"; 176 f1extop 1 rw "switches in the Function 1 Device ID"; 177 f0extop 1 rw "switches in the Function 0 Device ID"; 178 no_snoop 1 rw "Disable snooping (not recommendend)"; 179 _ 1 rsvd "Reserved"; 180 numrd 4 rw "Number of outstanding requests"; 181 numrfo 4 rw "Number of outstanding RFOs"; 182 }; 183 184 /* 185 * 8.4.16 186 */ 187 register msixcapid ro addr(cfg_base, 0x80) "MSI-X Capability ID" 188 type(uint8); 189 190 /* 191 * 8.4.17 192 */ 193 register msixnxtptr ro addr(cfg_base, 0x81) "MSI-X Next Pointer" 194 type(uint8); 195 196 constants msixctrl "MSI-X Control values" { 197 msix_use_intx = 0 "INTx method is used"; 198 msix_use_msix = 1 "MSI-X method is used"; 199 }; 200 201 /* 202 * 8.4.18 203 */ 204 register msixmsgctl addr(cfg_base, 0x82) "MSI-X Message Control" { 205 msi_x_en 1 rw "Select MSI-X instead of INTx method"; 206 function_mask 1 rw "Vector mask control"; 207 _ 3 rsvd "reserved"; 208 table_size 11 ro "Table size of MSI-X"; 209 }; 210 211 /* 212 * 8.4.19 - MSI-X Table Offset and BAR Indicator. 213 */ 214 register tableoff_bir ro addr(cfg_base, 0x84) "MSI-X Table Offset and BAR Indicator" { 215 offset 29 "Offset of the MSI-X structure from the CB_BAR base"; 216 bir 3 "Offset of the CB BAR in the Config Space"; 217 }; 218 219 /* 220 * 8.4.20 221 */ 222 register pbaoff_bir ro addr(cfg_base, 0x88) "MSI-X PBA Offset" { 223 offset 29 "Offset of the MSI-X PBA structure from the CB_BAR base"; 224 bir 3 "Offset of the CB BAR in the Config Space"; 225 }; 226 227 /* 228 * 8.4.21 - The PCI Express Capability List register enumerates the PCI 229 * Express Capability structure in the PCI 3.0 cfg_baseuration space 230 */ 231 register capid ro addr(cfg_base, 0x90) "Capability ID" 232 type(uint8); 233 234 /* 235 * 8.4.22 - The PCI Express Capability List register enumerates the PCI 236 * Express Capability structure in the PCI 3.0 cfg_baseuration space 237 */ 238 register nextptr addr(cfg_base, 0x91) "Capability Next Pointer" 239 type(uint8); 240 241 /* 242 * 8.4.23 - The PCI Express Capabilities register identifies the PCI Express 243 * device type and associated capabilities 244 */ 245 register expcap ro addr(cfg_base, 0x92) "PCI Express Device Type" { 246 _ 2 "Reserved"; 247 irq_msg_num 5 "N/A" ; 248 slot_impl 1 "N/A"; 249 port_type 4 "Type of the Device"; 250 version 4 "Version of the PCI Express capability structure"; 251 }; 252 253 /* 254 * 8.4.24 - The PCI Express Device Capabilities register identifies device 255 * specific information for the device. 256 */ 257 register devcap ro addr(cfg_base, 0x94) "PCI Express Device Capability Register" { 258 _ 3 "Reserved"; 259 flr 1 "FLR supported"; 260 pwr_scale 2 "Captured slot power limit scale"; 261 pwr_limit 8 "Captured slot power limit value"; 262 _ 2 "reserved"; 263 err_rep 1 "Role based error reporting"; 264 pwr_ind 1 "Power indicator present on device"; 265 att_ind 1 "Attention indicator present on device"; 266 att_btn 1 "Attention button present on device"; 267 ep_latency_1 3 "Endpoint L1 acceptable latency"; 268 ep_latency_0 3 "Endpoint L0 acceptable latency"; 269 ext_tag 1 "Extended tag supported"; 270 phantom 2 "Phantom functions supported"; 271 max_payload 3 "Maximum PCIe payload size"; 272 }; 273 274 /* 275 * 8.4.25 - The PCI Express Device Control register controls PCI Express 276 * specific capabilities parameters associated with the device. 277 */ 278 register devcon addr(cfg_base, 0x98) "The PCI Express Device Control register" { 279 flr 1 rw "Initiate FLR: reset only per FLR ECN"; 280 max_rd_sz 3 ro "Maximum read request size"; 281 no_snoop 1 rw "Enable the no-snoop functionality"; 282 aux_pwr_en 1 ro "Enable Auxiliary power managmenet"; 283 phantom_en 1 ro "Enable phantom functions"; 284 ext_tag_en 1 ro "Enable extended tab field"; 285 max_palyoad 3 ro "Maximum payload size"; 286 relaxed_ord 1 rw "Enable Relaxed ordering"; 287 unsup_rep 1 ro "Enable unsupported request reporting"; 288 fatal_err 1 ro "Enable fatal error reporting"; 289 non_fat_err 1 ro "Enable non-fatal error reporting"; 290 corr_err 1 ro "Enable correctable error reporting"; 291 }; 292 293 /* 294 * 8.4.26 - The PCI Express Device Status register provides information about 295 * 296 * PCI Express device specific parameters associated with the device 297 */ 298 register devsts ro addr(cfg_base, 0x9a) "Device Status Register" { 299 _ 10 "reserved"; 300 tr_pending 1 "Transaction pending"; 301 aux_power 1 "Auxiliary power detected"; 302 unsup_req 1 "Unsupported request detected"; 303 fatal_err 1 "fatal error detected"; 304 non_fat_err 1 "non-fatal error detected"; 305 corr_err 1 "correctable error detected"; 306 }; 307 308 /* 309 * 8.4.27 - Device Capability register 2 310 */ 311 register devcap2 ro addr(cfg_base, 0xb4) "Device Capability Register 2" { 312 _ 27 "Reserved"; 313 compl_timeout_disable 1 "Completion timeout disable supported"; 314 compl_timeout_values 4 "Completion timeout values supported"; 315 316 }; 317 318 /* 319 * 8.4.28 - Device Configuration Register 2 320 */ 321 register devcon2 addr(cfg_base, 0xb8) "Device Configuration Register 2" { 322 _ 11 rsvd "Reserved"; 323 compl_timeout_disable 1 rw "Completion timeout disable"; 324 compl_timeout_values 4 ro "Completion timeout values"; 325 }; 326 327 /* 328 * 8.4.29 - Power Management Capability. 329 * 330 * The PM Capabilities Register defines the capability ID, next pointer 331 * and other power management related support. The following PM 332 * registers / capabilities are added for software compliance. 333 */ 334 register pmcap ro addr(cfg_base, 0xe0) "Power Management Capability" { 335 _ 5 "Reserved"; 336 d2_sup 1 "D2 om state supported"; 337 d1_sup 1 "D2 om state supported"; 338 aux_current 3 "Auxiliary current"; 339 dev_init 1 "Device specific initialization"; 340 _ 1 "Reserved"; 341 pme_clock 1 "Power management clock"; 342 version 3 "Power management version"; 343 next 8 "Pointer to the next capability field"; 344 capid 8 "Capability ID (PM cap ID)"; 345 }; 346 347 constants power_st "Power States" { 348 pwr_st_d0 = 0 ""; 349 pwr_st_d1 = 1 ""; 350 pwr_st_d2 = 2 ""; 351 pwr_st_d3 = 3 ""; 352 }; 353 354 /* 355 * 8.4.30 - Power Management Control and Status. 356 * 357 * This register provides status and control information for PM events 358 * in the PCI Express port of the IIO. 359 */ 360 register pmcsr addr(cfg_base, 0xe4) "Power Management Control and Status." { 361 data 8 ro "Data field"; 362 clk_ctrl_en 1 ro "Bus power clock control enabled"; 363 b2_b3_sup 1 ro "B2-B3 Support"; 364 _ 6 rsvd "reserved"; 365 pme_status 1 ro "PME Status"; 366 data_scale 2 ro "Data Scale"; 367 data_select 4 ro "Data Select"; 368 pme_en 1 ro "Power Management Enabled"; 369 _ 4 rsvd "reserved"; 370 no_soft_rst 1 ro "No Softreset"; 371 _ 1 rsvd "reserved"; 372 pwr_state 2 rw "Powerstate to set"; 373 }; 374 375 /* 376 * 8.4.31 - DMA Cluster Uncorrectable Error Status (for function 0 only) 377 */ 378 register dmauncerrsts addr(cfg_base, 0x148) "DMA Cluster Uncorrectable Error Status" { 379 _ 19 rsvd "reserved"; 380 syndrome 1 rw1cs "Syndrome multiple errors"; 381 _ 1 rsvd "reserved"; 382 addr_dec 1 rw1cs "Read address decode error statuts"; 383 _ 2 rsvd "reserved"; 384 compl_hdr 1 rw1cs "Read completion error staturs"; 385 _ 3 rsvd "reserved"; 386 hw_parity 1 rw1cs "DMA internal HW parity error"; 387 dp_status 1 rw1cs "Received poisoned data from dp status"; 388 _ 2 rsvd "reserved"; 389 }; 390 391 /* 392 * 8.4.32 - DMA Cluster Uncorrectable Error Mask. (for function 0 only) 393 */ 394 register dmauncerrmsk addr(cfg_base, 0x14c) "DMA Cluster Uncorrectable Error Mask" { 395 _ 19 rsvd "reserved"; 396 syndrome 1 rw "Syndrome multiple errors"; 397 _ 1 rsvd "reserved"; 398 addr_dec 1 rw "Read address decode error statuts"; 399 _ 2 rsvd "reserved"; 400 compl_hdr 1 rw "Read completion error staturs"; 401 _ 3 rsvd "reserved"; 402 hw_parity 1 rw "DMA internal HW parity error"; 403 dp_status 1 rw "Received poisoned data from dp status"; 404 _ 2 rsvd "reserved"; 405 }; 406 407 /* 408 * 8.4.33 - DMA Cluster Uncorrectable Error Severity. (for function 0 only) 409 * 410 * This register controls severity of uncorrectable DMA unit errors 411 * between fatal and non-fatal. 412 */ 413 register dmauncerrsev addr(cfg_base, 0x150) "DMA Cluster Uncorrectable Error Severity." { 414 _ 19 rsvd "reserved"; 415 syndrome 1 rw "Syndrome multiple errors"; 416 _ 1 rsvd "reserved"; 417 addr_dec 1 rw "Read address decode error statuts"; 418 _ 2 rsvd "reserved"; 419 compl_hdr 1 rw "Read completion error staturs"; 420 _ 3 rsvd "reserved"; 421 hw_parity 1 rw "DMA internal HW parity error"; 422 dp_status 1 rw "Received poisoned data from dp status"; 423 _ 2 rsvd "reserved"; 424 }; 425 426 /* 427 * 8.4.34 - DMA Cluster Uncorrectable Error Pointer. (for function 0 only) 428 */ 429 register dmauncerrptr ro addr(cfg_base, 0x154) "DMA Cluster Uncorrectable Error Pointer" { 430 _ 3 "Reserved"; 431 uncerrptr 5 "oints to the first uncorrectable error logged in the DMAUNCERRSTS register."; 432 }; 433 434 /* 435 * 8.4.35 - DMA Cluster Global Error Pointe(for function 0 only) 436 */ 437 register dmaglberrptr addr(cfg_base, 0x160) "DMA Cluster Global Error Pointer" { 438 _ 4 "Reserved"; 439 glbl_err 4 "Points to 8 possible sources of uncorrectable rrors"; 440 441 }; 442 443 /* 444 * 8.4.36 - Internal DMA Channel Error Status Registers. 445 * 446 * R1CS for function 0, otherwise RO 447 */ 448 register chanerr_int addr(cfg_base, 0x180) "Internal DMA Channel Error Status Registers." { 449 _ 13 rsvd "reserved"; 450 desccnterr 1 rw1cs "Descriptor Count error"; 451 xorqerr 1 rw1cs "Xor error"; 452 crc_err 1 rw1cs "CRC test failed"; 453 unaffilerr 1 ro "Unaffiliated Error"; 454 _ 1 rsvd "Unused error"; 455 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 456 cmpaddrerr 1 rw1cs "Completion Address error"; 457 desclenerr 1 rw1cs "Description length error"; 458 descctrlerr 1 rw1cs "Description control error"; 459 wrdataerr 1 rw1cs "Write data error"; 460 rddataerr 1 rw1cs "Read Data error"; 461 dmadataerr 1 rw1cs "DMA Data Parity error"; 462 cdataerr 1 rw1cs "Data parity error"; 463 chancmderr 1 rw1cs "Channel command error"; 464 chanaddr 1 rw1cs "Channel address value error"; 465 descerr 1 rw1cs "Descriptor error"; 466 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 467 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 468 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 469 }; 470 471 constants chanerr_int_val "Values for enabling/disabling the error intr" { 472 chanerr_int_disabled = 1 "Disable the interrupt"; 473 chanerr_int_enabled = 0 "Enable the interrupt"; 474 }; 475 476 /* 477 * 8.4.37 - Internal DMA Channel Error Mask Registers. 478 * 479 * R1CS for function 0, otherwise RO 480 */ 481 register chanerrmsk_int addr(cfg_base, 0x184) "Internal DMA Channel Error Mask Registers." { 482 _ 13 rsvd "reserved"; 483 desccnterr 1 rw1cs "Descriptor Count error"; 484 xorqerr 1 rw1cs "Xor error"; 485 crc_err 1 rw1cs "CRC test failed"; 486 unaffilerr 1 ro "Unaffiliated Error"; 487 _ 1 rsvd "Unused error"; 488 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 489 cmpaddrerr 1 rw1cs "Completion Address error"; 490 desclenerr 1 rw1cs "Description length error"; 491 descctrlerr 1 rw1cs "Description control error"; 492 wrdataerr 1 rw1cs "Write data error"; 493 rddataerr 1 rw1cs "Read Data error"; 494 dmadataerr 1 rw1cs "DMA Data Parity error"; 495 cdataerr 1 rw1cs "Data parity error"; 496 chancmderr 1 rw1cs "Channel command error"; 497 chanaddr 1 rw1cs "Channel address value error"; 498 descerr 1 rw1cs "Descriptor error"; 499 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 500 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 501 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 502 }; 503 504 /* 505 * 8.4.38 - Internal DMA Channel Error Severity Registers. 506 * 507 * R1CS for function 0, otherwise RO 508 */ 509 register chanerrsev_int addr(cfg_base, 0x188) "Internal DMA Channel Error Severity Registers." { 510 _ 13 rsvd "reserved"; 511 desccnterr 1 rw1cs "Descriptor Count error"; 512 xorqerr 1 rw1cs "Xor error"; 513 crc_err 1 rw1cs "CRC test failed"; 514 unaffilerr 1 ro "Unaffiliated Error"; 515 _ 1 rsvd "Unused error"; 516 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 517 cmpaddrerr 1 rw1cs "Completion Address error"; 518 desclenerr 1 rw1cs "Description length error"; 519 descctrlerr 1 rw1cs "Description control error"; 520 wrdataerr 1 rw1cs "Write data error"; 521 rddataerr 1 rw1cs "Read Data error"; 522 dmadataerr 1 rw1cs "DMA Data Parity error"; 523 cdataerr 1 rw1cs "Data parity error"; 524 chancmderr 1 rw1cs "Channel command error"; 525 chanaddr 1 rw1cs "Channel address value error"; 526 descerr 1 rw1cs "Descriptor error"; 527 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 528 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 529 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 530 }; 531 532 /* 533 * 8.4.39 - DMA Channel Error Pointer 534 */ 535 register chanerrptr ro addr(cfg_base, 0x18c) "DMA Channel Error Pointer." { 536 _ 3 "reserved"; 537 chan_err_ptr 5 "DMA Channel error pointer"; 538 }; 539 540 541 /* 542 * ========================================================================= 543 * PCI Function Regsters 544 * 545 * Section 8.5: Crystal Beach DMA Registers 546 * 547 * Crystal Beach MMIO Register used to control the DMA functionality. The 548 * CB_BAR register points to the based address to these registers. 549 * All of these registers are accessible from only the processor. The IIO 550 * supports accessing the Crystal Beach device memory-mapped registers via 551 * QWORD reads and writes. The offsets indicated in the following table are 552 * from the CB_BAR value. 553 */ 554 555 /* 556 * 8.5.1 - Channel Count 557 * 558 * The Channel Count register specifies the number of channels that 559 * are implemented. 560 * 561 * Note: This will always reads 8, since there are 1 channel per 562 * function, but 8 functions per device 563 */ 564 register chancnt ro addr(bar, 0x0) "Channel Count" { 565 _ 3 rsvd "reserved"; 566 num 5 ro "Number of channels present"; 567 }; 568 569 /* 570 * 8.5.2 - Transfer Capacity 571 * 572 * The Transfer Capacity specifies the minimum of the maximum DMA 573 * transfer size supported on all channels. This is in bits. 574 * CPU supports maximum 1MB (default value 0x14) 575 */ 576 register xfercap ro addr(bar, 0x1) "Transfer Capacity"{ 577 _ 3 rsvd "reserved"; 578 max 5 ro "Maximum transfer capability"; 579 }; 580 581 /* 582 * 8.5.3 - DMA General Control 583 * 584 * The DMA Control register provides for general control operations. 585 */ 586 register genctrl addr(bar, 0x2) "DMA General Control" { 587 _ 7 rsvd "reserved"; 588 dbgen 1 rw "DB Generation"; 589 }; 590 591 /* 592 * 8.5.4 - The Interrupt Control register provides control of DMA interrupts. 593 */ 594 register intrctrl addr(bar, 0x3) "Interrupt Control Register" { 595 _ 4 rsvd "reserved"; 596 msix_vec 1 rw "MSI-X Vector Control. (Ignored by CB)"; 597 intp 1 ro "Interrupt. Set when status bit in attention is set"; 598 intp_sts 1 ro "Interrupt status. (not used in MSI-X model)"; 599 intp_en 1 rw "Master interrupt enable bit. (not used in MSI-X model)"; 600 }; 601 602 /* 603 * 8.5.5 - Attention Status 604 */ 605 register attnstatus ro addr(bar, 0x4) "Attention Status Register" { 606 _ 31 "Reserved"; 607 chanattn 1 "Channel Attention. Represents the interrupt status"; 608 }; 609 610 constants cbversions "Crystal Beach Major Versions" { 611 cbver_1x = 0x1 "Crystal Beach Version 1.xx"; 612 cbver_2x = 0x2 "Crystal Beach Version 2.xx"; 613 cbver_3x = 0x3 "Crystal Beach Version 3.xx"; 614 }; 615 616 /* 617 * 8.5.6 - Crystal Beach Version Number 618 * 619 * The CB version register field indicates the version of the CB 620 * specification that the IIO implements. The most significant 4-bits 621 * (range 7:4) are the major version number and the least significant 622 * 4-bits (range 3:0) are the minor version number. The IIO 623 * implementation for this Crystal Beach version is 3.2 encoded as 624 * 0b0011 0010. 625 */ 626 register cbver ro addr(bar, 0x8) "Crystal Beach Version Number" { 627 major 4 "Major Version Number"; 628 minor 4 "Minor Version Number"; 629 }; 630 631 /* 632 * 8.5.7 - Interrupt Delay Register 633 */ 634 register intrdelay addr(bar, 0xc) "Interrupt Delay Register" { 635 coalesc 1 ro "Interrupt Coalescing is supported"; 636 _ 1 rsvd "reserved"; 637 delay_us 14 rw "Interrupt delay time in micro seconds"; 638 }; 639 640 /* 641 * 8.5.8 - Chipset Status Register 642 */ 643 register cs_status ro addr(bar, 0xe) "Chipset Status Register" { 644 _ 12 "Reserved"; 645 addr_remap 1 "Address Remapping: reflects the TE bit of VT-d"; 646 mem_bypass 1 "Memory bypass"; 647 mmio_restrict 1 "MMIO Restriction"; 648 _ 1 "Reserved"; 649 }; 650 651 /* 652 * 8.5.9 - DMA Capability 653 */ 654 register dmacapability addr(bar, 0x10) "DMA Capability Register" { 655 _ 22 rsvd "Reserved"; 656 pq 1 ro "Parity and Quotient Opcodes for RAID 5 / 6"; 657 xor 1 ro "Only XOR for RAID 5 / 6 supported"; 658 ext_apic_id 1 ro "32bit APIC IDs are supported (otherwise 8bit APIC)"; 659 block_fill 1 ro "Block fill OP code is supported"; 660 move_crc 1 ro "Move and CRC op codes are supported"; 661 dca 1 rw "Direct Cache Access is supported"; 662 _ 1 rsvd "These opcodes have been deprecated in CB DMA v3"; 663 markerskip 1 ro "Marker skipping is supported"; 664 crc 1 ro "CRC generation supported"; 665 pagebreak 1 ro "Transfers crossing physical pages supported"; 666 }; 667 668 /* 669 * 8.5.10 - DCA offset 670 */ 671 register dcaoffset ro addr(bar, 0x14) "DCA Offset Register" 672 type(uint16); 673 674 /* 675 * 8.5.11 - CB DMA Priority Register (unused) 676 */ 677 register cbprio ro addr(bar, 0x40) "CB DMA Priority Register" 678 type(uint8); 679 680 constants chanctrl_snoop "Field values for Snoop Control" { 681 chanctrl_snoop_disabled = 0x1 "Disabled snooping"; 682 chanctrl_snoop_enabled = 0x0 "Enable snooping"; 683 }; 684 685 constants chanctrl_features "Field values for Channel Features" { 686 chanctrl_f_enable = 0x1 "Feature field is enabled"; 687 chanctrl_f_disable = 0x0 "Feature field is disabled"; 688 }; 689 690 /* 691 * 8.5.12 - Channel Control Register 692 * 693 * The Channel Control register controls the behavior of the DMA 694 * channel when specific events occur such as completion or errors. 695 */ 696 register chanctrl addr(bar, 0x80) "Channel Control Register" { 697 _ 6 rsvd "Reserved"; 698 dca_en 1 rw "Direct Cache access enabled"; 699 in_use 1 rw "Channel is in use"; 700 _ 2 rsvd "reserved"; 701 snoop_ctrl 1 rw "Descriptor address snoop control"; 702 err_int_en 1 rw "Error Interrupt Enabled"; 703 err_abort 1 rw "Any Error Abort Enbled"; 704 err_cmp_en 1 rw "Error Completion Enabled"; 705 _ 1 rsvd "Reserved"; 706 intp_dis 1 rw1c "Interrupt disable"; 707 }; 708 709 /* 710 * 8.5.13 - DMA Compatibility Register 711 */ 712 register dma_comp ro addr(bar, 0x82) "DMA Compatibility Register" { 713 _ 13 "Reserved"; 714 v3 1 "Compatible with CB Version 3"; 715 v2 1 "Compatible with CB Version 2"; 716 v1 1 "NOT compatible with CB Version 1"; 717 }; 718 719 /* 720 * 8.5.14 - DMA Channel Command Register 721 * 722 * Setting more than one of these bits with the same write operation 723 * will result in an Fatal error affiliated. 724 */ 725 register chancmd addr(bar, 0x84) "DMA Channel Command Register." { 726 _ 2 rsvd "Reserved"; 727 reset 1 rw "Reset DMA channel"; 728 resume 1 rw "resume"; 729 abort 1 rw "Abort"; 730 susp 1 rw "Suspend the DMA channel"; 731 append 1 rw "Append"; 732 start 1 rw "Start"; 733 }; 734 735 /* 736 * 8.5.15 - DMA Descriptor Count Register 737 * 738 * This is the absolute value of the number of valid descriptors in 739 * the chain. The hardware sets this register and an internal counter 740 * to zero whenever the CHAINADDR register is written. When this 741 * register does not equal the value of the internal register, the 742 * DMA channel processes descriptors, incrementing the internal 743 * counter each time that it completes (or skips) a descriptor.This 744 * register is RW if CHANCNT register is 1 otherwise this register is RO. 745 */ 746 register dmacount addr(bar, 0x86) "DMA Descriptor Count Register" 747 type(uint16); 748 749 750 constants trans_state "DMA Transfer States" { 751 trans_state_idle = 0x1 "Idle, All DMA transfers done"; 752 trans_state_susp = 0x2 "Suspended"; 753 trans_state_halt = 0x3 "Halted, operation aborted (error)"; 754 trans_state_armed = 0x4 "Armed State"; 755 }; 756 757 /* 758 * 8.5.16 - Channel Status Lo Register. 759 * 760 * The Channel Status Register records the address of the last 761 * descriptor completed by the DMA channel. Refer to Crystal Beach 762 * Architecture Specification 2.0 Rev 1.0 for special hardware 763 * requirements when software reads this register. 764 */ 765 register chansts_lo ro addr(bar, 0x88) "Channel Status Lo Register." { 766 cmpdscaddr 26 "Uppder address of the last descriptor processed"; 767 _ 3 "Reserved"; 768 dma_trans_state 3 "DMA transfer State"; 769 }; 770 771 /* 772 * 8.5.17 - Channel Status Hi Register. 773 * 774 * The Channel Status Register records the address of the last 775 * descriptor completed by the DMA channel. Refer to Crystal Beach 776 * Architecture Specification for special hardware requirements when 777 * software reads this register. 778 * 779 * Also stores the address of the last processed descriptor 780 */ 781 register chansts_hi ro addr(bar, 0x8c) "Channel Status Hi Register." 782 type(uint32); 783 784 /* 785 * 8.5.18 - Descriptor Chain Address Lo Register. 786 * 787 * This register is written by the processor to specify the first 788 * descriptor to be fetched by the DMA channel. 789 * 790 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 791 */ 792 register chainaddr_lo rw addr(bar, 0x90) "Descriptor Chain Address Lo Register." { 793 descaddr_lo 26 rw "Address of the first descriptor"; 794 _ 6 mbz "Must be zero"; 795 }; 796 797 /* 798 * 8.5.19 - Descriptor Chain Address Hi Register. 799 * 800 * This register is written by the processor to specify the first 801 * descriptor to be fetched by the DMA channel. 802 * 803 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 804 */ 805 register chainaddr_hi rw addr(bar, 0x94) "Descriptor Chain Address Hi Register." 806 type(uint32); 807 808 809 /* 810 * 8.5.20 - Channel Completion Address Lo Register. 811 * 812 * This register specifies the address where the DMA channel writes 813 * the completion status upon completion or an error condition i.e. 814 * it writes the contents of the CHANSTS register to the destination 815 * as pointed by the CHANCMP register. 816 * 817 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 818 */ 819 register chancmp_lo addr(bar, 0x98) "Channel Completion Address Lo Register." 820 type(uint32); 821 822 /* 823 * 8.5.21 - Channel Completion Address Hi Register. 824 * 825 * This register specifies the address where the DMA channel writes 826 * the completion status upon completion or an error condition i.e. 827 * it writes the contents of the CHANSTS register to the destination 828 * as pointed by the CHANCMP register. 829 * 830 * This register is RW if CHANCNT register is 1 otherwise this register is RO. 831 */ 832 register chancmp_hi addr(bar, 0x9c) "Channel Completion Address Hi Register." 833 type(uint32); 834 835 /* 836 * 8.5.22 - Channel Error Register 837 * 838 * The Channel Error Register records the error conditions occurring 839 * within a given DMA channel. 840 */ 841 register chanerr addr(bar, 0xa8) "Channel Error Register" { 842 _ 13 rsvd "reserved"; 843 desccnterr 1 rw1cs "Descriptor Count error"; 844 xorqerr 1 rw1cs "Xor error"; 845 crc_err 1 rw1cs "CRC test failed"; 846 unaffilerr 1 ro "Unaffiliated Error"; 847 _ 1 rsvd "Unused error"; 848 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 849 cmpaddrerr 1 rw1cs "Completion Address error"; 850 desclenerr 1 rw1cs "Description length error"; 851 descctrlerr 1 rw1cs "Description control error"; 852 wrdataerr 1 rw1cs "Write data error"; 853 rddataerr 1 rw1cs "Read Data error"; 854 dmadataerr 1 rw1cs "DMA Data Parity error"; 855 cdataerr 1 rw1cs "Data parity error"; 856 chancmderr 1 rw1cs "Channel command error"; 857 chanaddr 1 rw1cs "Channel address value error"; 858 descerr 1 rw1cs "Descriptor error"; 859 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 860 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 861 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 862 }; 863 864 /* 865 * 8.5.23 - Channel Error Mask Register. 866 */ 867 register chanerrmsk addr(bar, 0xac) "Channel Error Mask Register." { 868 _ 13 rsvd "reserved"; 869 desccnterr 1 rw1cs "Descriptor Count error"; 870 xorqerr 1 rw1cs "Xor error"; 871 crc_err 1 rw1cs "CRC test failed"; 872 unaffilerr 1 ro "Unaffiliated Error"; 873 _ 1 rsvd "Unused error"; 874 intcfgerr 1 rw1cs "Interrupt confiuguratio error"; 875 cmpaddrerr 1 rw1cs "Completion Address error"; 876 desclenerr 1 rw1cs "Description length error"; 877 descctrlerr 1 rw1cs "Description control error"; 878 wrdataerr 1 rw1cs "Write data error"; 879 rddataerr 1 rw1cs "Read Data error"; 880 dmadataerr 1 rw1cs "DMA Data Parity error"; 881 cdataerr 1 rw1cs "Data parity error"; 882 chancmderr 1 rw1cs "Channel command error"; 883 chanaddr 1 rw1cs "Channel address value error"; 884 descerr 1 rw1cs "Descriptor error"; 885 nxtdescerr 1 rw1cs "Next Descriptor Address error"; 886 dmaxfererr 1 rw1cs "DMA Transfer Destination address error"; 887 dmatranserr 1 rw1cs "DMA Transfer Source address error"; 888 }; 889 890 /* 891 * 8.5.24 - DCA Control Register 892 * 893 * This field is RW if CHANCNT register is 1 otherwise this register is RO 894 */ 895 register dcactrl addr(bar, 0xb0) "DCA Control Register" { 896 _ 16 rsvd "Reserved"; 897 target_cpu 16 rw "Specifies the APCI ID of the target CPU for compl writes"; 898 }; 899 900 /* 901 * 8.5.25 - DCA Version Number Register 902 */ 903 register dca_ver ro addr(bar, 0x100) "DCA Version Number Register" { 904 major 4 "Major Revision Number"; 905 minor 4 "Major Revision Number"; 906 }; 907 908 /* 909 * 8.5.26 - DCA Request ID Offset Register 910 */ 911 register dca_reqid_offset ro addr(bar, 0x102) "DCA Request ID Offset Register" 912 type(uint16); 913 914 /* 915 * 8.5.27 - Intel QPI Compability Register 916 */ 917 register csi_capability addr(bar, 0x108) "Intel QPI Compability Register" { 918 _ 15 rsvd "Reserved"; 919 prefetch_hint 1 ro "Prefetch hint"; 920 }; 921 922 /* 923 * 8.5.28 - PCI Express Cabability Register 924 * 925 * When set in function 0, DCA on PCIe is enabled, else disabled. 926 * IIO hardware does not use this bit from functions 1-7. In these 927 * functions, this bit is provided primarily for BIOS to communicate 928 * to driver that DCA is enabled in the IIO. 929 */ 930 register pcie_capability addr(bar, 0x10a) "PCI Express Cabability Register" { 931 _ 15 rsvd "Reserved"; 932 memwr_en 1 ro "Enable Memory Writes on PCI Express"; 933 }; 934 935 /* 936 * 8.5.29 - Intel QPI Compability Enable Register 937 */ 938 register csi_cap_enable addr(bar, 0x10c) "Intel QPI Compability Enable Register" { 939 _ 15 rsvd "Reserved"; 940 prefetch_hint 1 rw "Prefetch hint"; 941 }; 942 943 /* 944 * 8.5.30 - 945 */ 946 register pcie_cap_enable addr(bar, 0x10e) "PCI Express Cabability Enable Register" { 947 _ 15 rsvd "Reserved"; 948 memwr_en 1 rw "Enable Memory Writes on PCI Express"; 949 }; 950 951 constants tag_maps "APICID to Tag Map Values" { 952 tag_map_0 = 0x0 "Tag_Map[0]"; 953 tag_map_apic = 0x1 "APICID[ Tag_Map[3:0] ]"; 954 tag_map_apicneg = 0x2 "NOT( APICID [Tag_Map_4[3:0] ] )"; 955 tag_map_res = 0x3 "reserved"; 956 }; 957 958 datatype tag_map "Tag Map datatype" { 959 maptype 2 rw "Type as specified in tag_map_* values"; 960 _ 2 rsvd "reserved"; 961 map 4 rw "Map values"; 962 }; 963 964 /* 965 * 8.5.31 - APICID to Tag Map Register. 966 * 967 * When DCA is disabled, DMA engine uses all 1s in the tag field of 968 * the write. This register is setup by BIOS for the CB driver to read. 969 * BIOS will map APICID[7:5] to bits Tag[2:0]. BIOS should set Tag[4] to 970 * prevent implicit TPH cache target unless it is intended. 971 */ 972 register apicid_tag_map addr(bar, 0x110 ) "APICID to Tag Map Register." { 973 _ 24 rsvd "Reserved"; 974 tag_map_4 8 "Tag Map 4"; 975 tag_map_3 8 "Tag Map 3"; 976 tag_map_2 8 "Tag Map 2"; 977 tag_map_1 8 "Tag Map 1"; 978 tag_map_0 8 "Tag Map 0"; 979 }; 980 981 982 /* 983 * 8.5.32 - Global DCA Requester ID Table Registers. 984 */ 985 register dca_reqid0 addr(bar, 0x180) "Global DCA Requester ID Table Registers." { 986 last 1 ro "Last Requested ID register"; 987 _ 1 rsvd "reserved"; 988 valid 1 rw "If set, bits 15:0 are used for DCA identification"; 989 ignore 1 rw "If set, function number is ignore for DCA identification"; 990 _ 12 rsvd "reserved"; 991 bus 8 rw "PCI Bus number"; 992 dev 5 rw "PCI Device Id"; 993 fun 3 rw "PCI Device Function"; 994 }; 995 996 /* 997 * 8.5.33 - Global DCA Requester ID Table Registers. 998 */ 999 register dca_reqid1 addr(bar, 0x184) "Global DCA Requester ID Table Registers." { 1000 last 1 ro "Last Requested ID register"; 1001 _ 1 rsvd "reserved"; 1002 valid 1 rw "If set, bits 15:0 are used for DCA identification"; 1003 ignore 1 rw "If set, function number is ignore for DCA identification"; 1004 _ 12 rsvd "reserved"; 1005 bus 8 rw "PCI Bus number"; 1006 dev 5 rw "PCI Device Id"; 1007 fun 3 rw "PCI Device Function"; 1008 }; 1009 1010 /* 1011 * 8.5.34 - MSI-X Lower Address Registers. 1012 */ 1013 register msgaddr_lo addr(bar, 0x2000) "MSI-X Lower Address Registers." { 1014 chmsgaddr 30 rw "Specifies the local APIC to which this MSI-X interrupt needs to be sent"; 1015 chmsgaddr_const 2 ro ""; 1016 }; 1017 1018 /* 1019 * 8.5.35 - MSI-X Upper Address Registers. 1020 * 1021 * Reserved to 0 because does not apply to IA. This field is RW for 1022 * compatibility reason only. 1023 */ 1024 register msgaddr_hi ro addr(bar, 0x2004) "MSI-X Upper Address Registers." 1025 type(uint32); 1026 1027 /* 1028 * 8.5.36 - MSI-X Data Registers. 1029 * 1030 * Specifies the vector that needs to be used for interrupts from 1031 * the DMA engine. IIO uses the lower 16 bits of this field to form 1032 * the data portion of the interrupt on the coherent interface. The 1033 * upper 16 bits are not used by IIO and left as RW only for 1034 * compatibility reasons. 1035 */ 1036 register msgdata rw addr(bar, 0x2008) "MSI-X Data Registers." 1037 type(uint32); 1038 1039 /* 1040 * 8.5.37 - MSI-X Vector Control Registers. 1041 */ 1042 register vecctrl addr(bar, 0x200c) "MSI-X Vector Control Registers." { 1043 chvecctrlcnst 31 ro "chvecctrlcnst"; 1044 chmask 1 rw "When a bit is set, the channel is prohibited from sending a message"; 1045 }; 1046 1047 /* 1048 * 8.5.38 - MSI-X Interrupt Pending Bits Registers. 1049 */ 1050 register pendingbits addr(bar, 0x3000) "MSI-X Interrupt Pending Bits Registers." { 1051 chmsipendcnst 31 ro "Unused"; 1052 chmsipend 1 rw "Pending Bit (when set) indicates that the DMA engine has a pending MSI-X"; 1053 }; 1054 1055 1056 1057 /* 1058 * Descriptor types derrived from the Linux IOAT implementation 1059 */ 1060 1061 /* 1062 * Descriptor sizes 1063 * 1064 * XXX: there are super extended descriptors which are longer in size... 1065 */ 1066 constants desc_sizes "IOAT DMA Descriptor Sizes" { 1067 descriptor_size = 64 "Size of the DMA descriptor"; 1068 }; 1069 1070 /* 1071 * Possible opcodes 1072 */ 1073 constants desc_opcodes "IOAT DMA Descriptor OP Codes" { 1074 desc_op_copy = 0x00 "Copy Operation"; 1075 desc_op_memset = 0x01 "Memset Operation"; 1076 desc_op_xor = 0x87 "For Xor Descriptor"; 1077 desc_op_xor_val = 0x88 "For Xor descriptor"; 1078 }; 1079 1080 datatype desc_ctrl lsbfirst(32) "IOAT DMA Descriptor control field" { 1081 int_en 1 "Interrupt enable"; 1082 src_snoop_dis 1 "Disable snooping of source address"; 1083 dest_snoop_dis 1 "Disable snooping of destination address"; 1084 compl_write 1 ""; 1085 fence 1 ""; 1086 null 1 ""; 1087 src_brk 1 ""; 1088 dest_brk 1 ""; 1089 bundle 1 ""; 1090 dest_dca 1 ""; 1091 hint 1 ""; 1092 _ 13 "Reserved"; 1093 op 8 "OP Code to execute"; 1094 }; 1095 1096 datatype desc lsbfirst(32) "IOAT DMA Descriptor" { 1097 size 32 "Size of the transfer"; 1098 ctrl 32 "Descriptor control field"; 1099 src 64 "Physical address of the source"; 1100 dst 64 "Physical address of the destination"; 1101 next 64 "Physical address of the next descriptor"; 1102 _ 64 "Reserved"; 1103 _ 64 "Reserved"; 1104 user1 64 ""; 1105 user2 64 ""; 1106 }; 1107}; 1108 1109