1/* 2 * Copyright (c) 2008, 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * ia32.dev 11 * 12 * DESCRIPTION: ia32 Architectural definitions, including Architectural MSRs 13 * 14 * Numbers in comments refer to the Intel Architecture Manual, August 2007 15 */ 16 17device ia32 lsbfirst () "ia32 / Intel64 core architecture" { 18 19 /* 20 * *********************** 21 * Exception vectors 22 * *********************** 23 */ 24 constants exc_vec width(8) "Exception vectors" { 25 vec_de = 0 "divide error"; 26 vec_db = 1 "debug exception"; 27 vec_nmi = 2 "non-maskable interrupt"; 28 vec_bp = 3 "breakpoint"; 29 vec_of = 4 "overflow"; 30 vec_br = 5 "BOUND range exceeded"; 31 vec_ud = 6 "invalid opcode"; 32 vec_nm = 7 "device not available"; 33 34 vec_df = 8 "double fault"; 35 vec_cso = 9 "coprocessor segment overrun"; 36 vec_ts = 10 "invalid TSS"; 37 vec_np = 11 "segment not present"; 38 vec_ss = 12 "stack fault"; 39 vec_gp = 13 "general protection fault"; 40 vec_pf = 14 "page fault"; 41 // 15 reserved to intel 42 43 vec_mf = 16 "x87 FPU floating-point error"; 44 vec_ac = 17 "alignment check"; 45 vec_mc = 18 "machine check"; 46 vec_xf = 19 "SIMD floating-point exception"; 47 }; 48 49 /* 50 * *********************** 51 * Address space for model-Specific registers 52 * *********************** 53 */ 54 space msr(index) valuewise "Model-specific Registers"; 55 56 /* 57 * *********************** 58 * Architectural MSRs 59 * *********************** 60 */ 61 62 // 7.11.5 63 register mon_filter_size msr(0x06) "Monitor/Mwait filter size" type(uint64); 64 65 // Appendix B.1 66 register platform_id ro msr(0x17) "Platform ID" { 67 _ 50; 68 id 3 "platform id"; 69 _ 11; 70 }; 71 72 register apic_base msr(0x1b) "APIC base" { 73 _ 8; 74 bsp 1 ro "BSP flag"; 75 _ 2; 76 global 1 rw "APIC global enable"; 77 base 52 rw "APIC base"; 78 }; 79 80 register feature_cntl rw msr(0x3a) "Feature control" { 81 lock 1 rwo "lock"; 82 vmxinsmx 1 rwl "enable VMX inside SMX"; 83 vmxoutsmx 1 rwl "enable VMX outside SMX"; 84 _ 5; 85 senter_loc 7 rwl "SENTER local function"; 86 senter_glob 1 rwl "SENTER global enable"; 87 _ 48; 88 }; 89 90 register vmx_basic ro msr(0x480) "Basic VMX Capabilities" { 91 vmcs_rev_id 31 "VMCS Revision Identifier"; 92 _ 1 mbz; 93 region_size 13 "Bytes that should be allocated for VMXON and VMCS regions"; 94 _ 3; 95 paddr_width 1 "Physical address width Limited to 32 Bits"; 96 dual_mon 1 "Dual-monitor treatment supported"; 97 mem_type 4 "Memory tpe used to access VMCS with VMREAD/VMWRITE"; 98 instr_info_io 1 "INS/OUTS info is reported in VM-exit instruction-information"; 99 ctls_clear 1 "Controls that default to 1 may be cleared to 0"; 100 _ 8; 101 }; 102 103 // Capability Reporting Registers for VMX Controls 104 register vmx_pinbased_ctls ro msr(0x481) "Pin-based Controls" type(uint64); 105 register vmx_ppbased_ctls ro msr(0x482) "Primary Processor-based Controls" type(uint64); 106 register vmx_exit_ctls ro msr(0x483) "VM-exit Controls" type(uint64); 107 register vmx_entry_ctls ro msr(0x484) "VM-entry Controls" type(uint64); 108 register vmx_spbased_ctls ro msr(0x48b) "Secondary Processor-based Controls" type(uint64); 109 110 // Capability Reporting Registers for VMX Flex Controls 111 register vmx_true_pinbased_ctls ro msr(0x48d) "Pin-based Flex Controls" type(uint64); 112 register vmx_true_ppbased_ctls ro msr(0x48e) "Primary Processor-based Flex Controls" type(uint64); 113 register vmx_true_exit_ctls ro msr(0x48f) "VM-exit Flex Controls" type(uint64); 114 register vmx_true_entry_ctls ro msr(0x490) "VM-entry Flex Controls" type(uint64); 115 116 // Capability Reporting Registers of CR0 and CR4 bits 117 register vmx_cr0_fixed0 ro msr(0x486) "CR0 Bits Fixed to 0" type(uint64); 118 register vmx_cr0_fixed1 ro msr(0x487) "CR0 Bits Fixed to 1" type(uint64); 119 register vmx_cr4_fixed0 ro msr(0x488) "CR4 Bits Fixed to 0" type(uint64); 120 register vmx_cr4_fixed1 ro msr(0x489) "CR4 Bits Fixed to 1" type(uint64); 121 122 register vmx_ept_vpid ro msr(0x48c) "EPT and VPID Capabilities" { 123 eot 1 "Support execute-only translation"; 124 _ 5; 125 pwl4 1 "Support page-walk length of 4"; 126 _ 1; 127 ucmt 1 "Support uncacheable memory type"; 128 _ 5; 129 wbmt 1 "Support write-back memory type"; 130 _ 1; 131 ps21 1 "Support EPT PDE mapping to 2MB page"; 132 ps30 1 "Support EPT PDE mapping to 1GB page"; 133 _ 2; 134 invept_instr 1 "Support the instruction INVEPT"; 135 ept_adf 1 "Support EPT accessed and dirty flags"; 136 _ 3; 137 invept_sct 1 "Support single-context INVEPT type"; 138 invept_act 1 "Support all-context INVEPT type"; 139 _ 5; 140 invvpid_instr 1 "Support the instruction INVVPID"; 141 _ 7; 142 invvpid_iat 1 "Support individual-address INVVPID type"; 143 invvpid_sct 1 "Support single-context INVVPID type"; 144 invvpid_act 1 "Support all-context INVVPID type"; 145 invvpid_scrgt 1 "Support single-context-retaining-globals INVVPID type"; 146 _ 20; 147 }; 148 149 register bios_updt_trig rw msr(0x79) "BIOS update trigger" type(uint64); 150 register bios_sign_id rw msr(0x8b) "BIOS update signature" type(uint64); 151 register smm_monitor_ctl rw msr(0x9b) "SMM Monitor config" type(uint64); 152 153 register misc_enable rw msr(0x1a0) "Enable misc. features" { 154 fse 1 rw "Fast-Strings enable"; 155 _ 2; 156 atcce 1 rw "Automatic thermal control circuit enable"; 157 _ 3; 158 pma 1 ro "Performance monitoring available"; 159 _ 1; 160 hpd 1 rw "Hardware prefetcher disable"; 161 feme 1 rw "FERR# multiplexing enable"; 162 btsu 1 ro "Branch trace storage unavailable"; 163 pebsu 1 ro "Precise event-based sampling unavailable"; 164 tm2e 1 rw "Thermal monitor 2 enable"; 165 _ 2; 166 eiste 1 rw "Enhanced Intel SpeedStep tech enable"; 167 _ 1; 168 emfsm 1 rw "Enable monitor FSM"; 169 aclpd 1 rw "Adjacent cache line prefetch disable"; 170 eistsl 1 rwo "Enhanced SpeedStep select lock"; 171 _ 1; 172 lcmax 1 rw "Limit CPUID max val"; 173 xmd 1 rw "xTPR message disable"; 174 _ 10; 175 xdbd 1 rw "XD bit disable"; 176 _ 2; 177 dcupd 1 rw "DCU prefetcher disable"; 178 idad 1 rw "IDA disable"; 179 ippd 1 rw "IP prefetcher disable"; 180 _ 24; 181 }; 182 183 /* 184 * *********************** 185 * Machine check MSRs 186 * *********************** 187 */ 188 189 // 14.8.3 190 register p5_mc_addr msr(0x0) "P5 MC ADDR" type(uint64); 191 register p5_mc_type msr(0x1) "P5 MC Type" type(uint64); 192 193 // 14.3.1.1 194 register mcg_cap ro msr(0x179) "Global machine check capabilities" { 195 count 8 "Num. reporting banks available"; 196 ctl_p 1 "Implements MCG_CTL MSR"; 197 exp_p 1 "Implements extended MC regs"; 198 _ 1; 199 tes_p 1 "Threshold-based error status present"; 200 _ 4; 201 ext_cnt 8 "Num. extended MC regs present"; 202 _ 40; 203 }; 204 205 // 14.3.1.2 206 register mcg_status msr(0x17a) "Global machine check status" { 207 ripv 1 ro "Restart IP valid"; 208 eipv 1 ro "Error IP valid"; 209 mcip 1 rw "Machine check in progress"; 210 _ 61; 211 }; 212 213 // 14.3.1.3 214 constants mcg_ctl_val width(64) "Global MC control values" { 215 mc_enable = 1s; 216 mc_disable = 0x0; 217 }; 218 register mcg_ctl rw msr(0x17b) "Global machine check control" 219 type(mcg_ctl_val); 220 221 // 14.3.2.5 222 register mcg_rax rwzc msr(0x180) "State of RAX at MC" type(uint64); 223 register mcg_rbx rwzc msr(0x181) "State of RBX at MC" type(uint64); 224 register mcg_rcx rwzc msr(0x182) "State of RCX at MC" type(uint64); 225 register mcg_rdx rwzc msr(0x183) "State of RDX at MC" type(uint64); 226 register mcg_rsi rwzc msr(0x184) "State of RSI at MC" type(uint64); 227 register mcg_rdi rwzc msr(0x185) "State of RDI at MC" type(uint64); 228 register mcg_rbp rwzc msr(0x186) "State of RBP at MC" type(uint64); 229 register mcg_rsp rwzc msr(0x187) "State of RSP at MC" type(uint64); 230 register mcg_rflags rwzc msr(0x188) "State of RFLAGS at MC" type(uint64); 231 register mcg_rip rwzc msr(0x189) "State of RIP at MC" type(uint64); 232 register mcg_misc rwzc msr(0x18a) "Page fault/assist during DS" type(uint64); 233 register mcg_r8 rwzc msr(0x190) "State of R8 at MC" type(uint64); 234 register mcg_r9 rwzc msr(0x191) "State of R9 at MC" type(uint64); 235 register mcg_r10 rwzc msr(0x192) "State of R10 at MC" type(uint64); 236 register mcg_r11 rwzc msr(0x193) "State of R11 at MC" type(uint64); 237 register mcg_r12 rwzc msr(0x194) "State of R12 at MC" type(uint64); 238 register mcg_r13 rwzc msr(0x195) "State of R13 at MC" type(uint64); 239 register mcg_r14 rwzc msr(0x196) "State of R14 at MC" type(uint64); 240 register mcg_r15 rwzc msr(0x197) "State of R15 at MC" type(uint64); 241 242 // 14.3.2 243 constants tbtrk "Threshold-based error status" { 244 notrack = 0b00 "No hw status tracking"; 245 green = 0b01 "current status green"; 246 yellow = 0b10 "current status yellow"; 247 }; 248 249 regarray mc_ctl rw msr(0x400)[5; 4] "Machine check control" type(uint64); 250 regarray mc_status rwzc msr(0x401)[5; 4] "Machine check unit status" { 251 mca_ec 16 "MCA error code"; 252 ms_ec 16 "Model-specific error code"; 253 other 21 "Other information"; 254 tbes 2 type(tbtrk) "Threshold-based error status"; 255 _ 2 mbz; // Seems to need to be written zero to 256 // work (otherwise a GPF) but doesn't 257 // always read as zero on 258 // some AMD-based processors. 259 pcc 1 "Processor context corrupt"; 260 addrv 1 "MCi_ADDR register valid"; 261 miscv 1 "MCi_MISC register valid"; 262 en 1 "Error enabled"; 263 uc 1 "Error uncorrected"; 264 over 1 "Error overflow"; 265 val 1 "MCi_STATUS register valid"; 266 }; 267 regarray mc_addr rwzc msr(0x402)[5; 4] "Machine check addr" type(uint64); 268 regarray mc_misc rwzc msr(0x403)[5; 4] "Machine check misc" type(uint64); 269 270 271 /* 272 * *********************** 273 * Debugging and performance 274 * *********************** 275 */ 276 277 // 18.5.1 278 register debugctl rw msr(0x1d9) "Debug control" { 279 lbr 1 "Last branch/int/exception"; 280 btf 1 "Single-step on branches"; 281 _ 4; 282 tr 1 "Trace messages enable"; 283 bts 1 "Branch trace store"; 284 btint 1 "Branch trace interrupt"; 285 bts_off_os 1 "BTS off in OS"; 286 bts_off_usr 1 "BTS off in user code"; 287 freeze_lbrs_on_pmi 1; 288 freeze_perfmon_on_pmi 1; 289 _ 19; 290 }; 291 292 // 18.10 293 register tsc msr(0x10) "Time stamp counter" type(uint64); 294 295 // 18.12.1.1 296 regtype perfevtsel "Perfmon event select" { 297 evsel 8 "Event select"; 298 umask 8 "Unit mask"; 299 usr 1 "User mode"; 300 os 1 "OS mode"; 301 e 1 "Edge detect"; 302 pc 1 "Pin control"; 303 intr 1 "APIC interrupt enable"; 304 _ 1; 305 en 1 "Enable counters"; 306 inv 1 "Invert counter mask"; 307 cmask 8 "Counter mask"; 308 _ 32; 309 }; 310 register pmc0 msr(0xc1) "Perfmon counter 0" type(uint64); 311 register pmc1 msr(0xc2) "Perfmon counter 1" type(uint64); 312 register perfevtsel0 also msr(0x186) "Perfmon event select 0" type(perfevtsel); 313 register perfevtsel1 also msr(0x187) "Perfmon event select 1" type(perfevtsel); 314 315 // 18.14.1 316 regtype fixed_ctr "Fixed counter" { 317 v 40 "Value"; 318 _ 24; 319 }; 320 register fixed_ctr0 rw msr(0x309) "Fixed-funct. counter 0" type(fixed_ctr); 321 register fixed_ctr1 rw msr(0x30a) "Fixed-funct. counter 1" type(fixed_ctr); 322 register fixed_ctr2 rw msr(0x30b) "Fixed-funct. counter 2" type(fixed_ctr); 323 324 //345 perf_capabilities 325 326 //18.12.2.1 327 register fixed_ctr_ctl msr(0x38d) "Fixed counter control" { 328 enos0 1 "Enable 0 for OS"; 329 enusrs0 1 "Enable 0 for user"; 330 _ 1; 331 pmi0 1 "Enable PMI on overflow 0"; 332 enos1 1 "Enable 1 for OS"; 333 enusrs1 1 "Enable 1 for user"; 334 _ 1; 335 pmi1 1 "Enable PMI on overflow 1"; 336 enos2 1 "Enable 2 for OS"; 337 enusrs2 1 "Enable 2 for user"; 338 _ 1; 339 pmi2 1 "Enable PMI on overflow 2"; 340 _ 52; 341 }; 342 343 regtype perf_global "Perfmon global status/overflow" { 344 pmc0 1 "PMC0 overflow"; 345 pmc1 1 "PMC1 overflow"; 346 _ 30; 347 ctr0 1 "Fixed CTR0 overflow"; 348 ctr1 1 "Fixed CTR1 overflow"; 349 ctr2 1 "Fixed CTR2 overflow"; 350 _ 27; 351 ovfbuf 1 "Overflow buffer"; 352 condchgd 1 "Condition changed"; 353 }; 354 355 register perf_global_status ro msr(0x38e) "Perfmon global status" 356 type(perf_global); 357 register perf_global_over rwzc msr(0x390) "Perfmon global overlflow control" 358 type(perf_global); 359 360 register perf_global_ctrl msr(0x38f) "Perfmon global control" { 361 pmc0 1 "PMC0 enable"; 362 pmc1 1 "PMC1 enable"; 363 _ 30; 364 ctr0 1 "Fixed CTR0 enable"; 365 ctr1 1 "Fixed CTR1 enable"; 366 ctr2 1 "Fixed CTR2 enable"; 367 _ 29; 368 }; 369 370 // 18.14.4.1 371 register pebs_enable rw msr(0x3f1) "Precise event-based sampling enable" { 372 en 1 "enable"; 373 _ 63; 374 }; 375 376 /* 377 * *********************** 378 * Long mode operation 379 * *********************** 380 */ 381 382 // 4.13 383 register efer msr(0xc0000080) "Extended features enable" { 384 sce 1 rw "SYSCALL enable"; 385 _ 7; 386 lme 1 rw "Long mode enable"; 387 _ 1; 388 lma 1 rw "Long mode active"; // Should be rw, but must be 389 // preserved in practice! 390 nxe 1 rw "No-execute enable"; 391 _ 52; 392 }; 393 394 // 4.8.8 395 register star msr(0xc0000081) "Syscall target address" { 396 _ 32; 397 call 16 "SYSCALL CS and SS"; 398 ret 16 "SYSRET CS and SS"; 399 }; 400 401 register lstar msr(0xc0000082) "Long mode Syscall target address" 402 type(uint64); 403 404 register cstar msr(0xc0000083) "Compatibility mode Syscall target address" 405 type(uint64); 406 407 register fmask msr(0xc0000084) "SYSCALL EFLAGS mask" { 408 v 32 "Value"; 409 _ 32; 410 }; 411 register fs_base msr(0xc0000100) "FS base" type(uint64); 412 register gs_base msr(0xc0000101) "GS base" type(uint64); 413 register kernel_gs_base msr(0xc0000102) "Swap target of GS base" type(uint64); 414 415 416 /* 417 * *********************** 418 * Memory type range registers 419 * *********************** 420 */ 421 422 // 10.11.1 423 register mtrrcap ro msr(0xfe) "MTRR Capabilities" { 424 vcnt 8 "Number of variable range registers"; 425 fix 1 "Fixed range registers supported"; 426 _ 1; 427 wc 1 "Write-combining memory type supported"; 428 _ 53; 429 }; 430 431 // 10.11.2 432 register mtrr_def_type rw msr(0x2ff) "MTRR type definition" { 433 tpe 8 "Default memory type"; 434 _ 2; 435 fe 1 "Fixed-range MTRRs enable/disable"; 436 e 1 "MTRR enable/disable"; 437 _ 52; 438 }; 439 440 regarray mtrr_physbase rw msr(0x200)[8;2] "MTRR physical base" { 441 tpe 8 "Type"; 442 _ 4; 443 base 52 "Physical base address"; 444 }; 445 446 regarray mtrr_physmask rw msr(0x201)[8;2] "MTRR physical mask" { 447 _ 11; 448 v 1 "Valid"; 449 mask 52 "Physical mask"; 450 }; 451 452 register mtrr_fix64k_00000 rw msr(0x250) "MTRR fix64k_00000" type(uint64); 453 register mtrr_fix16k_80000 rw msr(0x258) "MTRR fix16k_80000" type(uint64); 454 register mtrr_fix16k_a0000 rw msr(0x259) "MTRR fix16k_a0000" type(uint64); 455 register mtrr_fix4k_c0000 rw msr(0x268) "MTRR fix4k_c0000" type(uint64); 456 register mtrr_fix4k_c8000 rw msr(0x269) "MTRR fix4k_c8000" type(uint64); 457 register mtrr_fix4k_d0000 rw msr(0x26a) "MTRR fix4k_d0000" type(uint64); 458 register mtrr_fix4k_d8000 rw msr(0x26b) "MTRR fix4k_d8000" type(uint64); 459 register mtrr_fix4k_e0000 rw msr(0x26c) "MTRR fix4k_e0000" type(uint64); 460 register mtrr_fix4k_e8000 rw msr(0x26d) "MTRR fix4k_e8000" type(uint64); 461 register mtrr_fix4k_f0000 rw msr(0x26e) "MTRR fix4k_f0000" type(uint64); 462 register mtrr_fix4k_f8000 rw msr(0x26f) "MTRR fix4k_f8000" type(uint64); 463 464 // 10.12 465 constants pat_val "Page attribute table values" { 466 uc = 0x00 "Uncacheable"; 467 wc = 0x01 "Write combining"; 468 wt = 0x04 "Write through"; 469 wp = 0x05 "Write protected"; 470 wb = 0x06 "Write back"; 471 ucd = 0x07 "Uncached"; 472 }; 473 register cr_pat rw msr(0x277) "Page attribute table control" { 474 pa0 8 type(pat_val); 475 pa1 8 type(pat_val); 476 pa2 8 type(pat_val); 477 pa3 8 type(pat_val); 478 pa4 8 type(pat_val); 479 pa5 8 type(pat_val); 480 pa6 8 type(pat_val); 481 pa7 8 type(pat_val); 482 }; 483 484 485 /* 486 * *********************** 487 * Power and thermal 488 * *********************** 489 */ 490 491 // 13.2 492 register mperf rw msr(0xe7) "Measured performance" type(uint64); 493 register aperf rw msr(0xe8) "Actual performance" type(uint64); 494 495 // 13.3 496 regtype perf_pnt "Performance point" { 497 eist 16 "EIST transition target"; 498 _ 16; 499 ida 1 "IDA disengage"; 500 _ 31; 501 }; 502 register perf_ctl rw msr(0x198) "Performance control" type(perf_pnt); 503 register perf_status ro msr(0x199) "Performance status" type(perf_pnt); 504 505 // 13.5.3 506 register clock_modulation rw msr(0x19a) "Clock modulation" { 507 _ 1; 508 dc 2 "On-Demand clock modulation duty cycle (x12.5%)"; 509 en 1 "Enable"; 510 _ 60; 511 }; 512 513 // 13.5.5.2 514 register therm_interrupt rw msr(0x19b) "Thermal monitor interrupt" { 515 ht 1 "High-temperature enable"; 516 lt 1 "Low-temperature enable"; 517 prochot 1 "PROCHOT# enable"; 518 forcpr 1 "FORCEPR# enable"; 519 over 1 "Overheat enable"; 520 _ 3; 521 tt1 7 "Thermal threshold 1 value"; 522 tt1int 1 "Thermal threshold 1 enable"; 523 tt2 7 "Thermal threshold 2 value"; 524 tt2int 1 "Thermal threshold 2 enable"; 525 _ 40; 526 }; 527 register therm_status msr(0x19c) "Thermal status" { 528 therm 1 ro "Status flag"; 529 thermlg 1 rwzc "Log flag"; 530 porf 1 ro "PROCHOT# or FORCEPR# asserted"; 531 porflg 1 rwzc "PROCHOT# or FORCEPR# log"; 532 cts 1 ro "Critical temperature status"; 533 ctslg 1 rwzc "Critical temperature log"; 534 tt1 1 ro "Thermal threshold status 1"; 535 tt1lg 1 rwzc "Thermal threshold log 1"; 536 tt2 1 ro "Thermal threshold status 2"; 537 tt2lg 1 rwzc "Thermal threshold log 2"; 538 _ 6; 539 dig 7 ro "Digital readout in Celsius"; 540 _ 4; 541 res 4 ro "Resolution in degrees Celsius"; 542 rv 1 ro "Reading valid"; 543 _ 32; 544 }; 545 546 547 /* 548 * *********************** 549 * AMD Performance Monitoring (Family 10h CPUs) 550 * *********************** 551 */ 552 553 // 3.12 554 regtype amd_perfevtsel "Perfmon event select" { 555 evsel 8 "Event select"; 556 umask 8 "Unit mask"; 557 usr 1 "User mode"; 558 os 1 "OS mode"; 559 e 1 "Edge detect"; 560 _ 1; 561 intr 1 "APIC interrupt enable"; 562 _ 1; 563 en 1 "Enable counters"; 564 inv 1 "Invert counter mask"; 565 cmask 8 "Counter mask"; 566 evsel_hi 4 "Event select Hi"; 567 _ 4; 568 guestonly 1 "Guest only counter"; 569 hostonly 1 "Host only counter"; 570 _ 22; 571 }; 572 573 // 10.1 574 register perfctr0 msr(0xc0010004) "Performance Counter 0" type(uint64); 575 register perfctr1 msr(0xc0010005) "Performance Counter 1" type(uint64); 576 register perfctr2 msr(0xc0010006) "Performance Counter 2" type(uint64); 577 register perfctr3 msr(0xc0010007) "Performance Counter 3" type(uint64); 578 579 // 10.2 580 register amd_perfevtsel0 msr(0xc0010000) "Performance Event Select 0" type(amd_perfevtsel); 581 register amd_perfevtsel1 msr(0xc0010001) "Performance Event Select 1" type(amd_perfevtsel); 582 register amd_perfevtsel2 msr(0xc0010002) "Performance Event Select 2" type(amd_perfevtsel); 583 register amd_perfevtsel3 msr(0xc0010003) "Performance Event Select 3" type(amd_perfevtsel); 584 585 /* 586 * AMD Hardware Configuration (Athlon XP and Opteron) 587 * 588 * BIOS and Kernel Developer's Guide for AMD NPT Family 0fh Processors 589 * BIOS and Kernel Developer's Guide for AMD NPT Family 10h Processors 590 */ 591 592 // 14.2.1.3 593 register amd_hwcr msr(0xc0010015) "Hardware Configuration" { 594 smmlock 1 "SMM code lock"; 595 slowfence 1 "Slow SFENCE Enable"; 596 _ 1 mbz; 597 tlbcachedis 1 "Cacheable Memory Disable"; 598 invd_wbinvd 1 "INVD to WBINVD conversion"; 599 _ 1; 600 ffdis 1 "TLB flush filter disable"; 601 dislock 1 "Disable x86 LOCK prefix functionality"; 602 ignneem 1 "IGNNE port emulation enable"; 603 monmwaitdis 1 "MONITOR and MWAIT disable"; 604 monmwaituseren 1 "MONITOR/MWAIT user mode enable"; 605 limitcpuidstdmaxval 1 "Limit CPUID standard maximum value"; 606 hltxspcycen 1 "Halt-exit special bus cycle enable"; 607 smispcycdis 1 "SMI special bus cycle disable"; 608 rsmspcycdis 1 "RSM special bus cycle disable"; 609 ssedis 1 "SSE instructions disable"; 610 _ 1; 611 wrap32dis 1 "32-bit address wrap disable"; 612 mcstatuswren 1 "Machine check status write enable"; 613 _ 1; 614 iocfggpfault 1 "IO-space configuration cause GP fault"; 615 misalignssedis 1 "Misaligned SSE mode disable"; 616 _ 1; 617 forceusrdwrszprb 1 "Force probes for upstream RdSized/WrSized"; 618 tscfreqsel 1 "TSC frequency select"; 619 _ 39; 620 }; 621 622 /* 623 * *********************** 624 * Not yet typed in! 625 * *********************** 626 */ 627 628 //600 ds_area 629 630 /* 631 * *********************** 632 * AND64/Intel64 paged virtual memory 633 * *********************** 634 */ 635 636 datatype vaddr_4k "4kB virtual address (long mode)" { 637 ppo 12 "Physical page offset"; 638 pto 9 "Page-table offset"; 639 pdo 9 "Page-directory offset"; 640 pdpo 9 "Page-directory-pointer offset"; 641 pml4o 9 "Page-map-level-4 offset"; 642 se 16 "Sign extend"; 643 }; 644 645 datatype pte_4k "Any-level page table entry, 4kB mapping" { 646 p 1 "Present"; 647 rw 1 "Read/write"; 648 us 1 "User/Supervisor"; 649 pwt 1 "Page-level writethrough"; 650 pcd 1 "Page-level cache disable"; 651 a 1 "Accessed"; 652 d 1 "Dirty"; 653 ps 1 "Page size"; 654 g 1 "Global page"; 655 base 42 "Base address of next level"; 656 avail 12 "Available"; 657 nx 1 "Np execute"; 658 }; 659 660 datatype pde_2M "Page directory entry, 2MB mapping" { 661 p 1 "Present"; 662 rw 1 "Read/write"; 663 us 1 "User/Supervisor"; 664 pwt 1 "Page-level writethrough"; 665 pcd 1 "Page-level cache disable"; 666 a 1 "Accessed"; 667 d 1 "Dirty"; 668 ps 1 "Page size (must be 1)"; 669 g 1 "Global page"; 670 _ 3; 671 pat 1 "Page-attribute table"; 672 _ 8; 673 base 30 "Physical page base address"; 674 avail 12 "Available"; 675 nx 1 "Np execute"; 676 }; 677 678 datatype pdpe_1G "Page directory ptr entry, 1GB mapping" { 679 p 1 "Present"; 680 rw 1 "Read/write"; 681 us 1 "User/Supervisor"; 682 pwt 1 "Page-level writethrough"; 683 pcd 1 "Page-level cache disable"; 684 a 1 "Accessed"; 685 d 1 "Dirty"; 686 ps 1 "Page size (must be 1)"; 687 g 1 "Global page"; 688 _ 3; 689 pat 1 "Page-attribute table"; 690 _ 16; 691 base 22 "Physical page base address"; 692 avail 12 "Available"; 693 nx 1 "Np execute"; 694 }; 695 696 register tsc_deadline rw msr(0x6e0) "TSC deadline" type(uint64); 697 698}; 699