1/* 2 * Memory mapped GIC v2 CPU Interface. sysreg mapped (GICv3) CPU interfaces 3 * should use definitions in armv8.dev. 4 * Source: ARM IHI 0069B, page 8-560 5 */ 6device gic_v2_cpu msbfirst (addr cpuif) "MMIO mapped GIC CPU interface" { 7 8 register CTLR rw addr(cpuif, 0x0) "CPU Interface Control Register - secure" { 9 _ 21 mbz; 10 EOImodeNS 1; 11 EOImodeS 1; 12 IRQBypDisGrp1 1; 13 FIQBypDisGrp1 1; 14 IRQBypDisGrp0 1; 15 FIQBypDisGrp0 1; 16 CBPR 1; 17 FIQEn 1; 18 _ 1 mbz; 19 EnableGrp1 1; 20 EnableGrp0 1; 21 }; 22 23 register CTLR_NS rw also addr(cpuif, 0x0) "CPU Interface Control Register - Non-secure" { 24 _ 22 mbz; 25 EOImodeNS 1; 26 RES0 2; 27 IRQBypDisGrp1 1; 28 FIQBypDisGrp1 1; 29 _ 4 mbz; 30 EnableGrp1 1; 31 }; 32 33 register PMR rw addr(cpuif, 0x0004) "Interrupt Controller Interrupt Priority Mask Register" { 34 _ 24; 35 priority 8 "Priority mask level"; 36 }; 37 38 register BPR rw addr(cpuif, 0x0008) "Interrupt Controller Binray Point Register" { 39 _ 29; 40 binary_point 3; 41 }; 42 43 register IAR rw addr(cpuif, 0x000C) "Interrupt Controller Interrupt Acknowledge Register" { 44 _ 8; 45 intid 24 "INTID of the signaled interrupt"; 46 }; 47 48 register EOIR wo addr(cpuif, 0x0010) "Interrupt Controller End Of Interrupt Register" { 49 _ 8; 50 intid 24 "INTID from the corresponding ICC_IAR0_EL1 access"; 51 }; 52 53 54 register RPR ro addr(cpuif, 0x0014) "Running Priority Register" { 55 56 _ 24; 57 priority 8 "Running priority"; 58 }; 59 60 61 register HPPIR ro addr(cpuif, 0x0018) "Highest Priority Pending Interrupt Register" { 62 _ 8; 63 intid 24 "INTID of the highest priority pending interrupt"; 64 }; 65 66 register ABPR rw addr(cpuif, 0x001c) "Aliased Binary Point Register" { 67 _ 29; 68 binary_point 3; 69 }; 70 71 register AIAR ro addr(cpuif, 0x0020) "Aliased Interrupt Acknowledge Register" { 72 _ 8; 73 intid 24 "INTID of the signaled interrupt"; 74 }; 75 76 register AEOIR wo addr(cpuif, 0x0024) "Aliased End of Interrupt Register" { 77 _ 8; 78 intid 24 "INTID from the corresponding ICC_IAR0_EL1 access"; 79 }; 80 81 register AHPPIR ro addr(cpuif, 0x0028) "Aliased Highest Priority Pending Interrupt Register" { 82 _ 8; 83 intid 24 "INTID of the highest priority pending interrupt"; 84 }; 85 86 register STATUSR rw addr(cpuif, 0x002C) "Error Reporting Status Register" { 87 _ 27; 88 asv 1 "Attempted security violation"; 89 wrod 1 "Write to an RO location"; 90 rwod 1 "Read of a WO location"; 91 wrd 1 "Write to a reserved location"; 92 rrd 1 "Read of a reserved location"; 93 }; 94 95 register APR1 rw addr(cpuif, 0x00D0) "CPU Interface Active Priorities Registers" { 96 impl 32; 97 }; 98 99 register APR2 rw addr(cpuif, 0x00D4) "CPU Interface Active Priorities Registers" { 100 impl 32; 101 }; 102 103 register APR3 rw addr(cpuif, 0x00D8) "CPU Interface Active Priorities Registers" { 104 impl 32; 105 }; 106 107 register APR4 rw addr(cpuif, 0x00DC) "CPU Interface Active Priorities Registers" { 108 impl 32; 109 }; 110 111 register NSAPR1 rw addr(cpuif, 0x00E0) "Non-secure CPU Interface Active Priorities Registers" { 112 impl 32; 113 }; 114 115 register NSAPR2 rw addr(cpuif, 0x00E4) "Non-secure CPU Interface Active Priorities Registers" { 116 impl 32; 117 }; 118 119 register NSAPR3 rw addr(cpuif, 0x00E8) "Non-secure CPU Interface Active Priorities Registers" { 120 impl 32; 121 }; 122 123 register NSAPR4 rw addr(cpuif, 0x00EC) "Non-secure CPU Interface Active Priorities Registers" { 124 impl 32; 125 }; 126 127 register IIDR ro addr(cpuif, 0x00FC) "CPU Interface Identification Register" { 128 ProductID 8 "Product identifier"; 129 _ 4 mbz; 130 Variant 4 "Variant number"; 131 Revision 4 "Revision number"; 132 Implementer 12 "JEP106 code of implementing company"; 133 }; 134 135 register DIR wo addr(cpuif, 0x1000) "Deactivate Interrupt Register" { 136 _ 8; 137 intid 24 "INTID of the highest priority pending interrupt"; 138 }; 139 140}; 141