1/* 2 * Copyright (c) 2011, 2013, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * e10k.dev 11 * 12 * DESCRIPTION: Intel 82599 10 GbE Controller 13 * 14 * Numbers in comments refer to the Intel 82599 10 GbE Controller Datasheet 15 * 322429-007, Revison 2.6, December 2010 16 */ 17 18device e10k lsbfirst ( addr base ) "Intel 82599 10 GbE Controller" { 19 20 /************************************ 21 * 8.2.3.1 General control registers 22 ***********************************/ 23 24 // 8.2.3.1 25 register ctrl rw addr(base, 0x00000) "Device control" { 26 _ 2 mbz; 27 pcie_md 1 "PCIe Master Disable"; 28 lrst 1 "Link reset"; 29 _ 22 rsvd; 30 rst 1 "Device reset"; 31 _ 5 rsvd; 32 }; 33 34 constants lanid "LAN ID" { 35 lan_0 = 0b00 "LAN 0"; 36 lan_1 = 0b01 "LAN 1"; 37 lan_not_u1 = 0b10 "LAN ID not used"; 38 lan_not_u2 = 0b11 "LAN ID not used"; 39 }; 40 41 // 8.2.3.1.1 42 register status ro addr(base, 0x00008) "Device status" { 43 _ 2; 44 lan_id 2 type(lanid) "LAN ID"; 45 _ 3; 46 link_up 1 "Linkup Status Indication"; 47 _ 2; 48 num_vfs 8 "Num VFs"; 49 iov_active 1 "IOV Active"; 50 pcie_mes 1 "PCIe Master Enable Status"; 51 _ 12; 52 }; 53 54 // 8.2.3.1.2 55 register ctrl_ext rw addr(base, 0x00018) "Extended Device Control Register" { 56 _ 14 rsvd; 57 pfrstd 1 "PF Reset Done"; 58 _ 1 rsvd; 59 ns_dis 1 "NO Snoop Disable"; /* Not in spec, but set by FBSD/Linux */ 60 ro_dis 1 "Relaxed Ordering Disable"; 61 _ 8 rsvd; 62 ext_vlan 1 "Extended VLAN"; 63 _ 1 rsvd; 64 drv_load 1 "Driver loaded "; 65 _ 3 rsvd; 66 }; 67 68 // 8.2.3.1.3 69 register esdp rw addr(base, 0x00020) "Extended SDP Control" { 70 sdp0_data 1 "SDP0 Data Value"; 71 sdp1_data 1 "SDP1 Data Value"; 72 sdp2_data 1 "SDP2 Data Value"; 73 sdp3_data 1 "SDP3 Data Value"; 74 sdp4_data 1 "SDP4 Data Value"; 75 sdp5_data 1 "SDP5 Data Value"; 76 sdp6_data 1 "SDP6 Data Value"; 77 sdp7_data 1 "SDP7 Data Value"; 78 sdp0_iodir 1 "SDP0 Pin Directionality"; 79 sdp1_iodir 1 "SDP1 Pin Directionality"; 80 sdp2_iodir 1 "SDP2 Pin Directionality"; 81 sdp3_iodir 1 "SDP3 Pin Directionality"; 82 sdp4_iodir 1 "SDP4 Pin Directionality"; 83 sdp5_iodir 1 "SDP5 Pin Directionality"; 84 sdp6_iodir 1 "SDP6 Pin Directionality"; 85 sdp7_iodir 1 "SDP7 Pin Directionality"; 86 sdp0_native 1 "SDP0 Operating Mode"; 87 sdp1_native 1 "SDP1 Operating Mode"; 88 sdp2_native 1 "SDP2 Operating Mode"; 89 sdp3_native 1 "SDP3 Operating Mode"; 90 sdp4_native 1 "SDP4 Operating Mode"; 91 sdp5_native 1 "SDP5 Operating Mode"; 92 sdp6_native 1 "SDP6 Operating Mode"; 93 sdp7_native 1 "SDP7 Operating Mode"; 94 _ 2 rsvd; 95 sdp2_ts_tt1 1 "SDP2 Native Mode Functionality"; 96 sdp3_ts_tt0 1 "SDP3 Native Mode Functionality"; 97 sdp4_func 1 "SDP4 Native Mode Functionality"; 98 sdp5_func 1 "SDP5 Native Mode Functionality"; 99 sdp6_ts_tt1 1 "SDP6 Native Mode Functionality"; 100 sdp7_ts_tt0 1 "SDP7 Native Mode Functionality"; 101 }; 102 103 // 8.2.3.1.4 104 register i2cctl rw addr(base, 0x00028) "I2C Control" { 105 i2c_clkin 1 "I2C_CLK In Value"; 106 i2c_clkout 1 "I2C_CLK Out Value"; 107 i2c_datain 1 "I2C_DATA In Value"; 108 i2c_dataout 1 "I2C_DATA Out Value"; 109 _ 28 rsvd; 110 }; 111 112 constants ledmode "LED Mode" { 113 link_up = 0b0000 "Link established and maintained"; 114 link_10g = 0b0001 "10G Link established and maintained"; 115 mac_act = 0b0010 "MAC activity"; 116 filter_act = 0b0011 "MAC activity that passed MAC filters"; 117 link_act = 0b0100 "Steady when link good, blinking on activity"; 118 link_1g = 0b0101 "1G Link established and maintained"; 119 link_100 = 0b0110 "100M Link established and maintained"; 120 led_on = 0b1110 "LED on"; 121 led_off = 0b1111 "LED off"; 122 }; 123 124 // 8.2.3.1.5 125 register ledctl rw addr(base, 0x00200) "LED Control" { 126 led0_mode 4 type(ledmode) "LED0 Mode"; 127 _ 1 rsvd; 128 glob_blmode 1 "GLOBAL blink mode"; 129 led0_ivrt 1 "LED0 Invert"; 130 led0_blink 1 "LED0 Blink"; 131 132 led1_mode 4 type(ledmode) "LED1 Mode"; 133 _ 2 rsvd; 134 led1_ivrt 1 "LED1 Invert"; 135 led1_blink 1 "LED1 Blink"; 136 137 led2_mode 4 type(ledmode) "LED2 Mode"; 138 _ 2 rsvd; 139 led2_ivrt 1 "LED2 Invert"; 140 led2_blink 1 "LED2 Blink"; 141 142 led3_mode 4 type(ledmode) "LED3 Mode"; 143 _ 2 rsvd; 144 led3_ivrt 1 "LED3 Invert"; 145 led3_blink 1 "LED3 Blink"; 146 }; 147 148 // 8.2.3.1.6 149 register exvet rw addr(base, 0x05078) "Extended VLAN Ether Type " { 150 _ 16 rsvd; 151 vet_ext 16 "Outer-VLAN Ether Type"; 152 }; 153 154 155 /************************************ 156 * 8.2.3.2 EEPROM/Flash Registers 157 ***********************************/ 158 159 constants fwe_control "Flash Write Enable Control" { 160 fwe_erase = 0b00 "Flash erase"; 161 fwe_nowrite = 0b01 "Flash writes disabled"; 162 fwe_write = 0b10 "Flash writes enabled"; 163 }; 164 165 constants eeprom_size "EEPROM Size" { 166 eesz_16K = 0b0100 "16Kb, 2B Address Size"; 167 eesz_32K = 0b0101 "32Kb, 2B Address Size"; 168 eesz_64K = 0b0110 "64Kb, 2B Address Size"; 169 eesz_128K = 0b0111 "128Kb, 2B Address Size"; 170 eesz_256K = 0b1000 "256Kb, 2B Address Size"; 171 }; 172 173 // 8.2.3.2.1 174 register eec rw addr(base, 0x10010) "EEPROM/Flash Control Register" { 175 ee_sk 1 "Clock input to the EEPROM"; 176 ee_cs 1 "Chip select input to the EEPROM"; 177 ee_di 1 "Data input to the EEPROM"; 178 ee_do 1 ro "Data output bit from the EEPROM"; 179 fwe 2 type(fwe_control) "Flash Write Enable Control"; 180 ee_req 1 "Request EEPROM Access"; 181 ee_gnt 1 ro "Grant EEPROM Access"; 182 ee_pres 1 ro "EEPROM Present"; 183 auto_rd 1 ro "EEPROM Auto-Read Done"; 184 _ 1 rsvd; 185 ee_size 4 ro type(eeprom_size) "EEPROM Size"; 186 pci_anadon 1 ro "PCIe Analog Done"; 187 pci_cordon 1 ro "PCIe Core Done"; 188 pci_gendon 1 ro "PCIe General Done"; 189 pci_fundon 1 ro "PCIe Function Done"; 190 core_done 1 ro "Core Done"; 191 core_csrdon 1 ro "Core CSR Done"; 192 mac_done 1 ro "MAC Done"; 193 _ 10 rsvd; 194 }; 195 196 // 8.2.3.2.2 197 register eerd rw addr(base, 0x10014) "EEPROM Read Register" { 198 start 1 "Start Read"; 199 done 1 "Read Done"; 200 addr 14 "Read Address"; 201 data 16 "Read Data"; 202 }; 203 204 // 8.2.3.2.3 (page 462) 205 register fla rw addr(base, 0x1001C) "Flash Access Register" { 206 fl_sck 1 "Clock input to the Flash"; 207 fl_ce 1 "Chip select input to the Flash"; 208 fl_si 1 "Data input to the Flash"; 209 fl_so 1 ro "Data output bit from the Flash"; 210 fl_req 1 "Request Flash Access"; 211 fl_gnt 1 "Grant Flash Access"; 212 _ 24 mbz; 213 fl_busy 1 ro "Flash Busy"; 214 fl_er 1 "Flash Erase Command"; 215 }; 216 217 // 8.2.3.2.4 218 register eemngctl rw addr(base, 0x10110) "Manageability EEPROM Control Register" { 219 addr 15 "EEPROM address to read or write"; 220 start 1 "Start"; 221 write 1 "Write"; 222 eebusy 1 "EPROM Busy"; 223 _ 13 rsvd; 224 done 1 "Transaction Done"; 225 }; 226 227 // 8.2.3.2.5 228 register eemngdata rw addr(base, 0x10114) "Manageability EEPROM Read/Write Data" { 229 wrdata 16 "Data to be written to the EEPROM"; 230 rddata 16 ro "Data returned from the EEPROM read"; 231 }; 232 233 constants flmng_command "Commands to access flash" { 234 fl_read = 0b00 "Read command"; 235 fl_write = 0b01 "Write command"; 236 fl_secerase = 0b10 "Sector erase"; 237 fl_erase = 0b11 "Erase"; 238 }; 239 240 // 8.2.3.2.6 241 register flmngctl rw addr(base, 0x10118) "Manageability Flash Control Register" { 242 addr 24 "Flash address to read or write"; 243 cmd 2 type(flmng_command) "Command"; 244 cmdv 1 "Command Valid"; 245 flbusy 1 "Flash Busy"; 246 _ 2 rsvd; 247 done 1 rc "Read Done"; 248 wrdone 1 "Global Done"; 249 }; 250 251 // 8.2.3.2.7 252 register flmngdata rw addr(base, 0x1011C) "Manageability Flash Read Data" { 253 data 32 "Read/Write Data"; 254 }; 255 256 // 8.2.3.2.8 257 register flop rw addr(base, 0x1013C) "Flash Opcode Register" { 258 serase 8 "Flash Block Erase Instruction"; 259 derase 8 "Flash Device Erase Instruction"; 260 _ 16 rsvd; 261 }; 262 263 // 8.2.3.2.9 264 register grc rw addr(base, 0x10200) "General Receive Control" { 265 mng_en 1 ro "Manageability Enable"; 266 apme 1 "Advance Power Management Enable"; 267 _ 30 rsvd; 268 }; 269 270 /************************************ 271 * 8.2.3.3 Flow Control Registers 272 ***********************************/ 273 274 // 8.2.3.3.1 275 register pfctop rw addr(base, 0x03008) "Priority Flow Control Type Opcode" { 276 fct 16 "Priority Flow Control EtherType"; 277 fcop 16 "Priority Flow Control Opcode"; 278 }; 279 280 // 8.2.3.3.2 281 regarray fcttv rw addr(base, 0x03200) [4] "Flow Control Transmit Timer Value" { 282 ttv0 16 "Transmit Timer Value 2n"; 283 ttv1 16 "Transmit Timer Value 2n+1"; 284 }; 285 286 // 8.2.3.3.3 287 regarray fcrtl rw addr(base, 0x03220) [8] "Flow Control Receive Threshold Low" { 288 _ 5 rsvd; 289 rtl 14 "Receive Threshold Low n"; 290 _ 12 rsvd; 291 xone 1 "XON Enable n"; 292 }; 293 294 // 8.2.3.3.4 295 regarray fcrth rw addr(base, 0x03260) [8] "Flow Control Receive Threshold High" { 296 _ 5 rsvd; 297 rth 14 "Receive Threshold High n"; 298 _ 12 rsvd; 299 fcen 1 "Transmit flow control enable for packet buffer n"; 300 }; 301 302 // 8.2.3.3.5 303 register fcrtv rw addr(base, 0x032A0) "Flow Control Refresh Threshold Value" { 304 fc_refth 16 "Flow Control Refresh Threshold"; 305 _ 16 rsvd; 306 }; 307 308 // 8.2.3.3.6 309 register tfcs ro addr(base, 0x0CE00) "Transmit Flow Control Status" { 310 tc_xon 8 "Set if flow control is in XON state"; 311 _ 24 rsvd; 312 }; 313 314 constants tfc_status "Transmit Flow Control Status" { 315 tfc_dis = 0b00 "Transmit flow control disabled"; 316 lfc_en = 0b01 "Link flow control enabled"; 317 pfc_en = 0b10 "Priority flow control enabled"; 318 }; 319 320 // 8.2.3.3.7 321 register fccfg rw addr(base, 0x03D00) "Flow Control Configuration" { 322 _ 3 rsvd; 323 tfce 2 type(tfc_status) "Transmit Flow Control Enable"; 324 _ 27 rsvd; 325 }; 326 327 328 /************************************ 329 * 8.2.3.4 PCIe Registers 330 ***********************************/ 331 332 constants pcie_capability_version "PCIe Capability Version" { 333 ver1 = 0b0 "Capability version: 0x1"; 334 ver2 = 0b1 "Capability version: 0x2"; 335 }; 336 337 // 8.2.3.4.1 338 register gcr rw addr(base, 0x11000) "PCIe Control Register" { 339 _ 9 rsvd; 340 ctrsen 1 "Completion Timeout resend enable"; 341 _ 1 rsvd; 342 no_resend 2 "Number of resends"; 343 _ 5 rsvd; 344 pcie_capver 1 type(pcie_capability_version) "PCIe Capability Version"; 345 _ 2 rsvd; 346 hdrlog_inv 1 "hdr_log inversion"; 347 _ 10 rsvd; 348 }; 349 350 // 8.2.3.4.2 351 register gscl_1 rw addr(base, 0x11010) "PCIe Statistic Control Register #1" { 352 gio_cnt_en0 1 "Enables PCIe statistic counter number 0"; 353 gio_cnt_en1 1 "Enables PCIe statistic counter number 1"; 354 gio_cnt_en2 1 "Enables PCIe statistic counter number 2"; 355 gio_cnt_en3 1 "Enables PCIe statistic counter number 3"; 356 lbc_en0 1 "LBC Enable 0"; 357 lbc_en1 1 "LBC Enable 1"; 358 lbc_en2 1 "LBC Enable 2"; 359 lbc_en3 1 "LBC Enable 3"; 360 _ 19 rsvd; 361 gio_cnt_tst 1 "Test Bit"; 362 gio_64bit 1 "Enables two 64-bit counters instead of four 32-bit counters"; 363 gio_cnt_rst 1 "Reset indication of PCIe statistic counters"; 364 gio_cnt_stp 1 "Stop indication of PCIe statistic counters."; 365 gio_cnt_sta 1 "Start indication of PCIe statistic counters."; 366 }; 367 368 constants pcie_statenc "PCIe Statistic Events Encoding" { 369 bad_tlp = 0x00 "Bad TLP from LL"; 370 no_req_tout = 0x10 "Requests that reached timeout"; 371 nack_dllp = 0x20 "NACK DLLP received"; 372 repl_tout = 0x21 "Replay happened in retry buffer"; 373 recv_error = 0x22 "Receive error"; 374 repl_rollov = 0x23 "Replay roll over"; 375 resnd_pkg = 0x24 "Re-sending packets"; 376 sp_linkdown = 0x25 "Surprise link down"; 377 ltssm_l0_rt = 0x30 "LTSSM in L0s in both Rx and Tx"; 378 ltssm_l0_rx = 0x31 "LTSSM in L0s in Rx"; 379 ltssm_l0_tx = 0x32 "LTSSM in L0s in Tx"; 380 ltssm_l1act = 0x33 "LTSSM in L1 active"; 381 ltssm_l1sft = 0x34 "LTSSM in L1 software"; 382 ltssm_recov = 0x35 "LTSSM in recovery"; 383 }; 384 385 // 8.2.3.4.3 386 register gscl_2 rw addr(base, 0x11014) "PCIe Statistic Control Register #2" { 387 gio_evcnt0 8 type(pcie_statenc) "Event number that counter 0 counts"; 388 gio_evcnt1 8 type(pcie_statenc) "Event number that counter 1 counts"; 389 gio_evcnt2 8 type(pcie_statenc) "Event number that counter 2 counts"; 390 gio_evcnt3 8 type(pcie_statenc) "Event number that counter 3 counts"; 391 }; 392 393 // 8.2.3.4.4 394 regarray gscl5_8 rw addr(base, 0x11030) [4] "PCIe Statistic Control Register #5...#8" { 395 lbc_thr 16 "Threshold for the leaky bucket counter n."; 396 lbc_timer 16 "Time period between decrementing value in leaky bucket Counter n."; 397 }; 398 399 // 8.2.3.4.5 400 regarray gscn ro addr(base, 0x11020) [4] "PCIe Statistic Counter Registers #0...#3" 401 type(uint32); 402 403 constants power_state "Power State indication" { 404 ps_dr = 0b00 "DR"; 405 ps_d0u = 0b01 "D0u"; 406 ps_d0a = 0b10 "D0a"; 407 ps_d3 = 0b11 "D3"; 408 }; 409 410 // 8.2.3.4.6 411 register factps ro addr(base, 0x10150) "Function Active and Power State to Manageability" { 412 f0_pstate 2 type(power_state) "Func0 Power State"; 413 lan0_valid 1 "LAN0 Valid"; 414 f0_auxen 1 "Function 0 Auxiliary (AUX) Power PM Enable "; 415 _ 2 rsvd; 416 f1_pstate 2 type(power_state) "Func1 Power State"; 417 lan1_valid 1 "LAN1 Valid"; 418 f1_auxen 1 "Function 1 Auxiliary (AUX) Power PM Enable "; 419 _ 19 rsvd; 420 mngcg 1 "Manageability Clock Gated"; 421 lan_fsel 1 "LAN Function Sel"; 422 pstate_chg 1 "PM State changed"; 423 }; 424 425 // 8.2.3.4.7 426 register pciephyadr rw addr(base, 0x11040) "PCIe Analog Configuration Register" { 427 address 12 "The indirect access' address"; 428 _ 13 rsvd; 429 byte_en 4 "The indirect access' byte enable"; 430 read_en 1 "The indirect access is read transaction"; 431 write_en 1 "The indirect access is write transaction"; 432 done 1 "Acknowledge for the indirect access to the CSR"; 433 }; 434 435 // 8.2.3.4.8 436 register pciephydat rw addr(base, 0x11044) "PCIe PHY Data Register" 437 type(uint32); 438 439 // 8.2.3.4.9 440 register swsm rw addr(base, 0x10140) "Software Semaphore Register" { 441 smbi 1 rwzc "Semaphore Bit"; 442 swesmbi 1 "Software Semaphore bi"; 443 _ 30 rsvd; 444 }; 445 446 constants fw_mode "Firmware Mode" { 447 nomode = 0x0 "None (manageability off)"; 448 ptmode = 0x2 "PT mode"; 449 hien_only = 0x4 "Host interface enable only"; 450 }; 451 452 constants ext_err_ind "External Error Indication" { 453 noerr = 0x00 "No error"; 454 inv_eechs = 0x01 "Invalid EEPROM checksum"; 455 unlkd_secee = 0x02 "Unlocked secured EEPROM"; 456 clk_offcmd = 0x03 "Clock off host command"; 457 inv_flchs = 0x04 "Invalid Flash checksum"; 458 inv_c0chs = 0x05 "C0 checksum failed"; 459 inv_c1chs = 0x06 "C1 checksum failed"; 460 inv_c2chs = 0x07 "C2 checksum failed"; 461 inv_c3chs = 0x08 "C3 checksum failed"; 462 tt_exeeded = 0x09 "TLB table exceeded"; 463 dmal_failed = 0x0A "DMA load failed"; 464 bad_hwver = 0x0B "Bad hardware version in patch load"; 465 fl_notsup = 0x0C "Flash device not supported in the 82599"; 466 unspec = 0x0D "Unspecified error"; 467 }; 468 469 // 8.2.3.4.10 470 register fwsm ro addr(base, 0x10148) "Firmware Semaphore Register" { 471 fwsmbi 1 "Firmware Semaphore"; 472 fw_mode 3 type(fw_mode) "Firmware Mode"; 473 _ 2 rsvd; 474 eep_relind 1 "EEPROM Reloaded Indication"; 475 _ 8 rsvd; 476 fw_valid 1 "Firmware Valid"; 477 reset_cnt 3 "Reset Counter"; 478 exterr_ind 6 type(ext_err_ind) "External Error Indication"; 479 pcie_cfgerr 1 "PCIe Configuration Error Indication"; 480 sdes0_err 1 "PHY/SERDES0 Configuration Error Indication"; 481 sdes1_err 1 "PHY/SERDES1 Configuration Error Indication"; 482 _ 4 rsvd; 483 }; 484 485 // 8.2.3.4.11 486 register swfw_sync rw addr(base, 0x10160) "Software Firmware Synchronization" { 487 sw_eepsm 1 "EEPROM access is owned by software"; 488 sw_physm0 1 "PHY 0 access is owned by software"; 489 sw_physm1 1 "PHY 1 access is owned by software"; 490 sw_maccsrsm 1 "Software owns access to shared CSRs"; 491 sw_flsm 1 "Software Flash semaphore"; 492 fw_eepsm 1 ro "EEPROM access is owned by firmware"; 493 fw_physm0 1 ro "PHY 0 access is owned by firmware"; 494 fw_physm1 1 ro "PHY 1 access is owned by firmware"; 495 fw_maccsrsm 1 ro "Firmware owns access to shared CSRs"; 496 fw_flsm 1 ro "Firmware Flash semaphore"; 497 _ 22 rsvd; 498 }; 499 500 constants vt_mode "VT mode of operation" { 501 vt_none = 0b00 "No VT"; 502 vt_16 = 0b01 "VT16"; 503 vt_32 = 0b10 "VT32"; 504 vt_64 = 0b11 "VT64"; 505 }; 506 507 // 8.2.3.4.12 508 register gcr_ext rw addr(base, 0x11050) "PCIe Control Extended Register" { 509 vtmode 2 type(vt_mode) "VT mode of operation"; 510 _ 2 rsvd; 511 apbacd 1 "Auto PBA Clear Disable"; 512 _ 27 rsvd; 513 }; 514 515 // 8.2.3.4.13 516 register mrevid ro addr(base, 0x11064) "Mirrored Revision ID" { 517 eeprom_rev 8 "Mirroring of rev ID loaded from EEPROM"; 518 default_rev 8 "Mirroring of default rev ID, before EEPROM load"; 519 _ 16 rsvd; 520 }; 521 522 // 8.2.3.4.14 523 register picause rw1c addr(base, 0x110B0) "PCIe Interrupt Cause" { 524 ca 1 "PCI completion abort exception"; 525 ua 1 "Unsupported I/O address exception"; 526 be 1 "Wrong byte-enable exception in the FUNC unit"; 527 to 1 "PCI timeout exception in the FUNC unit"; 528 bmef 1 "Bus master enable of the PF or one of the VFs is de-asserted"; 529 _ 27 rsvd; 530 }; 531 532 // 8.2.3.4.15 533 register piena rw addr(base, 0x110B8) "PCIe Interrupt Enable" { 534 ca 1 "Enable PCI completion abort interrupt"; 535 ua 1 "Enable unsupported I/O address interrupt"; 536 be 1 "Enable wrong byte-enable interrupt"; 537 to 1 "Enable PCI timeout interrupt"; 538 bmef 1 "Enable bus master enable interrupt"; 539 _ 27 rsvd; 540 }; 541 542 // Undocumented 543 register ciaa rw addr(base, 0x11088) "CIAA" type(uint32); 544 register ciad rw addr(base, 0x1108C) "CIAD" type(uint32); 545 546 /************************************ 547 * 8.2.3.5 Interrupt Registers 548 ***********************************/ 549 550 // 8.2.3.5.1 551 register eicr rw1c addr(base, 0x00800) "Extended Interrupt Cause Register" { 552 rtxq 16 "Receive/Transmit Queue Interrupts"; 553 flow_dir 1 "Flow Director Exception"; 554 rx_miss 1 "Rx Miss"; 555 pci_ex 1 "PCI Timeout Exception"; 556 mailbox 1 "VF to PF MailBox Interrupt"; 557 lsc 1 "Link Status Change"; 558 linksec 1 "LinkSec"; 559 mng 1 "Manageability Event Detected"; 560 _ 1 rsvd; 561 gpi_spd0 1 "General Purpose Interrupt on SDP0"; 562 gpi_spd1 1 "General Purpose Interrupt on SDP1"; 563 gpi_spd2 1 "General Purpose Interrupt on SDP2"; 564 gpi_spd3 1 "General Purpose Interrupt on SDP3"; 565 ecc 1 "Unrecoverable ECC Error"; 566 _ 1 rsvd; 567 tcp_timer 1 "TCP Timer Expired"; 568 _ 1 rsvd; 569 }; 570 571 // 8.2.3.5.2 572 register eics wo addr(base, 0x00808) "Extended Interrupt Cause Set Register" { 573 cause 31 "Interrupt Cause Set"; 574 _ 1 rsvd; 575 }; 576 577 // 8.2.3.5.3 578 register eims rw addr(base, 0x00880) "Extended Interrupt Mask Set/Read Register" { 579 cause 31 rws "Interrupt Enable"; 580 _ 1 rsvd; 581 }; 582 583 // 8.2.3.5.4 584 register eimc wo addr(base, 0x00888) "Extended Interrupt Mask Clear Register" { 585 cause 31 "Interrupt Mask"; 586 _ 1 rsvd; 587 }; 588 589 // 8.2.3.5.5 590 register eiac rw addr(base, 0x00810) "Extended Interrupt Auto Clear Register" { 591 rtxq 16 "RTxQ Auto Clear"; 592 _ 14 rsvd; 593 tcp_timer 1 "TCP Timer Auto Clear"; 594 _ 1 rsvd; 595 }; 596 597 // 8.2.3.5.6 598 register eiam rw addr(base, 0x00890) "Extended Interrupt Auto Mask Enable Register" { 599 cause 31 "Auto Mask"; 600 _ 1 rsvd; 601 }; 602 603 // 8.2.3.5.7 604 regarray eicsn wo addr(base, 0x000A90) [2] "Extended Interrupt Cause Set Registers" { 605 cause 32 "Interrupt Cause Set"; 606 }; 607 608 // 8.2.3.5.8 609 regarray eimsn addr(base, 0x000AA0) [2] "Extended Interrupt Mask Set/Read Registers" { 610 cause 32 rws "Interrupt Enable"; 611 }; 612 613 // 8.2.3.5.9 614 regarray eimcn wo addr(base, 0x000AB0) [2] "Extended Interrupt Mask Clear Registers" { 615 cause 32 "Interrupt Mask"; 616 }; 617 618 // 8.2.3.5.10 619 regarray eiamn rw addr(base, 0x000AD0) [2] "Extended Interrupt Auto Mask Enable registers" { 620 cause 32 "Auto Mask"; 621 }; 622 623 // 8.2.3.5.11 624 register eitrsel rw addr(base, 0x00894) "MSIX to EITR Select" { 625 vfselect 32 "VFSelect"; 626 }; 627 628 // 8.2.3.5.12 629 /* Since this reg-array is split over 2 different addresses we have to 630 * implement it here as two different registers. */ 631 regtype eitrn "Extended Interrupt Throttle Register Type" { 632 _ 3 rsvd; 633 itr_int 9 "Minimum inter-interrupt interval"; 634 _ 3 rsvd; 635 lli_mod 1 "LLI Moderation"; 636 lli_credit 5 "LLI Credit"; 637 itr_count 7 "ITR Counter"; 638 _ 3 rsvd; 639 cnt_wdis 1 "CNT_WDIS"; 640 }; 641 642 regarray eitr_l rw addr(base, 0x00820) [24] 643 "Extended Interrupt Throttle Registers #0-#23" 644 type(eitrn); 645 646 regarray eitr_h rw addr(base, 0x12300) [104] 647 "Extended Interrupt Throttle Registers #24-#128" 648 type(eitrn); 649 650 // 8.2.3.5.13 651 /* A read from this register seems to cause an ECC error, that's why I 652 * replaced rsvd below by mbz, so that the _wr() method don't causes a 653 * read. */ 654 regarray l34timir rw addr(base, 0x0E800) [128] "L3 L4 Tuples Immediate Interrupt Rx" { 655 _ 12 mbz; /* rsvd */ 656 size_bp 1 "Size Bypass"; 657 _ 6 mbz; 658 _ 1 mb1; 659 lli 1 "Low Latency Interrupt"; 660 rx_queue 7 "Rx Queue"; 661 _ 4 mbz; /* rsvd */ 662 }; 663 664 // 8.2.3.5.14 665 register llithresh rw addr(base, 0x0EC90) "LLI Size Threshol" { 666 sz_thresh 12 "Size Threshold"; 667 _ 20 rsvd; 668 }; 669 670 // 8.2.3.5.15 671 register imirvp rw addr(base, 0x0EC60) "Immediate Interrupt Rx VLAN Priority Register" { 672 vlan_pri 3 "VLAN Priority"; 673 vlan_pri_en 1 "VLAN Priority Enable"; 674 _ 28 rsvd; 675 }; 676 677 // 8.2.3.5.16 678 regarray ivar rw addr(base, 0x00900) [64] "Interrupt Vector Allocation Registers" { 679 i_alloc0 6 "The interrupt allocation for Rx queue 2n"; 680 _ 1 rsvd; 681 i_allocval0 1 "Interrupt allocation 0 valid"; 682 i_alloc1 6 "The interrupt allocation for Tx queue 2n"; 683 _ 1 rsvd; 684 i_allocval1 1 "Interrupt allocation 1 valid"; 685 i_alloc2 6 "The interrupt allocation for Rx queue 2n+1"; 686 _ 1 rsvd; 687 i_allocval2 1 "Interrupt allocation 2 valid"; 688 i_alloc3 6 "The interrupt allocation for Tx queue 2n+1"; 689 _ 1 rsvd; 690 i_allocval3 1 "Interrupt allocation 3 valid"; 691 }; 692 693 // 8.2.3.5.17 694 register ivar_misc rw addr(base, 0x00A00) "Miscellaneous Interrupt Vector Allocation" { 695 i_alloc0 7 "MSI-X vector assigned to the TCP timer interrupt"; 696 i_allocval0 1 "Interrupt allocation 0 valid"; 697 i_alloc1 7 "MSI-X vector assigned to the other interrupt cause"; 698 i_allocval1 1 "Interrupt allocation 1 valid"; 699 _ 16 rsvd; 700 }; 701 702 // 8.2.3.5.18 703 register gpie rw addr(base, 0x00898) "General Purpose Interrupt Enable" { 704 spd0_gpien 1 "General Purpose Interrupt Detection Enable for SDP0"; 705 spd1_gpien 1 "General Purpose Interrupt Detection Enable for SDP1"; 706 spd2_gpien 1 "General Purpose Interrupt Detection Enable for SDP2"; 707 spd3_gpien 1 "General Purpose Interrupt Detection Enable for SDP3"; 708 msix 1 "MSI-X Mode enable"; 709 ocd 1 "Other Clear Disable"; 710 eimen 1 "EICS Immediate Interrupt Enable"; 711 ll_int 4 "Low latency Credits Increment Rate"; 712 rsc_delay 3 "RSC Delay"; 713 vtmode 2 type(vt_mode) "VT_Mode"; 714 _ 14 rsvd; 715 eiame 1 "Extended Interrupt Auto Mask Enable"; 716 pba_sup 1 "BA Support"; 717 }; 718 719 720 /************************************ 721 * 8.2.3.6 MSI-X Table Registers 722 ***********************************/ 723 724 // 8.2.3.6.1 725 regarray pbacl rw addr(base, 0x110C0) [8] "MSI-X PBA Clear" { 726 penbitclr 32 rw1c "MSI-X Pending Bits Clear"; 727 }; 728 729 730 /************************************ 731 * 8.2.3.7 Receive Registers 732 ***********************************/ 733 734 // 8.2.3.7.1 735 register fctrl rw addr(base, 0x05080) "Filter Control Register" { 736 _ 1 rsvd; 737 sbp 1 "Store Bad Packets"; 738 _ 6 rsvd; 739 mpe 1 "Multicast Promiscuous Enable"; 740 upe 1 "Unicast Promiscuous Enable"; 741 bam 1 "Broadcast Accept Mode"; 742 _ 21 rsvd; 743 }; 744 745 // 8.2.3.7.2 746 register vlnctrl rw addr(base, 0x05088) "VLAN Control Register" { 747 vet 16 "VLAN Ether Type"; 748 _ 12 rsvd; 749 cfi 1 "Canonical Form Indicator Bit Value"; 750 cfien 1 "Canonical Form Indicator Enable"; 751 vfe 1 "VLAN Filter Enable"; 752 _ 1 rsvd; 753 }; 754 755 // 8.2.3.7.3 756 register mcstctrl rw addr(base, 0x05090) "Multicast Control Register" { 757 mo 2 "Multicast Offset"; 758 mfe 1 "Multicast Filter Enable"; 759 _ 29 rsvd; 760 }; 761 762 // 8.2.3.7.4 763 regarray psrtype rw addr(base, 0x0EA00) [64] "Packet Split Receive Type Register" { 764 _ 1 mbz; 765 split_nfs 1 "Split received NFS packets after NFS header"; 766 _ 2 mbz; 767 split_tcp 1 "Split received TCP packets after TCP header"; 768 split_udp 1 "Split received UDP packets after UDP header"; 769 _ 2 mbz; 770 split_ip4 1 "Split received IPv4 packets after IPv4 header"; 771 split_ip6 1 "Split received IPv6 packets after IPv6 header"; 772 _ 2 mbz; 773 split_l2 1 "Split received L2 packets after L2 header"; 774 _ 16 mbz; 775 rqpl 3 "Number of bits to use for RSS redirection"; 776 }; 777 778 // 8.2.3.7.5 779 register rxcsum rw addr(base, 0x05000) "Receive Checksum Control" { 780 _ 12 rsvd; 781 ippcse 1 "IP Payload Checksum Enable"; 782 pscd 1 "RSS/Fragment Checksum Status Selection"; 783 _ 18; 784 }; 785 786 constants nfs_version "NFS Version selection" { 787 nfs2 = 0b00 "NFS version 2"; 788 nfs3 = 0b01 "NFS version 3"; 789 nfs4 = 0b10 "NFS version 4"; 790 }; 791 792 // 8.2.3.7.6 793 register rfctl rw addr(base, 0x05008) "Receive Filter Control Register" { 794 _ 5 rsvd; /* Caution: The manuals says bits 5:0, probably typo */ 795 rsc_dis 1 "RSC Disable"; 796 nfsw_dis 1 "Disable filtering of NFS write request headers"; 797 nfsr_dis 1 "Disable filtering of NFS read reply headers"; 798 nfs_ver 2 type(nfs_version) "NFS version recognized by the hardware"; 799 ipv6_dis 1 "Disable IPv6 packet filtering"; 800 _ 1 mbz; 801 _ 2 rsvd; 802 ipfrsp_dis 1 "IP Fragment Split Disable"; 803 _ 3 rsvd; 804 _ 14 mbz; 805 }; 806 807 // 8.2.3.7.7 808 regarray mta rw addr(base, 0x05200) [128] "Multicast Table Array" { 809 bit_vec 32 "Bit Vector"; 810 }; 811 812 // 8.2.3.7.8 813 regarray ral rw addr(base, 0x0A200) [128 ; 8] "Receive Address Low" { 814 ral 32 "Receive Address Low"; /* CAUTION: BIG endian */ 815 }; 816 817 // 8.2.3.7.9 818 regarray rah rw addr(base, 0x0A204) [128 ; 8] "Receive Address High" { 819 rah 16 "Receive Address High"; /* CAUTION: BIG endian */ 820 _ 15 rsvd; 821 av 1 "Address Valid"; 822 }; 823 824 // 8.2.3.7.10 825 regarray mpsar rw addr(base, 0x0A600) [256] "MAC Pool Select Array" { 826 pool_ena 32 "Pool Enable Bit Array"; 827 }; 828 829 // 8.2.3.7.11 830 regarray vfta rw addr(base, 0x0A000) [128] "VLAN Filter Table Array" { 831 vlan_flt 32 "VLAN Filter"; 832 }; 833 834 constants mrq_mode "Defines the allocation of the Rx queues per RSS, Virt and DCB" { 835 no_rss = 0b0000 "RSS disabled"; 836 rss_only = 0b0001 "RSS only -- Single set of RSS 16 queues"; 837 dcb8_norss = 0b0010 "DCB enabled and RSS disabled -- 8 TCs, each allocated 1 queue"; 838 dcb4_norss = 0b0011 "DCB enabled and RSS disabled -- 4 TCs, each allocated 1 queue"; 839 dcb8_rss = 0b0100 "DCB and RSS -- 8 TCs, each allocated 16 RSS queues"; 840 dcb4_rss = 0b0101 "DCB and RSS -- 4 TCs, each allocated 16 RSS queues"; 841 vrt_only = 0b1000 "Virtualization only -- 64 pools, no RSS, each pool allocated 2 queue"; 842 vrt32_rss = 0b1010 "Virtualization and RSS -- 32 pools, each allocated 4 RSS queues"; 843 vrt64_rss = 0b1011 "Virtualization and RSS -- 64 pools, each allocated 2 RSS queues"; 844 vrt16_dcb = 0b1100 "Virtualization and DCB -- 16 pools, each allocated 8 TCs"; 845 vrt32_dcb = 0b1101 "Virtualization and DCB -- 32 pools, each allocated 4 TCs"; 846 }; 847 848 // 8.2.3.7.12 849 register mrqc rw addr(base, 0x0EC80) "Multiple Receive Queues Command Register" { 850 mrque 4 type(mrq_mode) "Multiple Receive Queues Enable"; 851 _ 12 rsvd; 852 en_tcpip4 1 "Enable TcpIPv4 hash function"; 853 en_ip4 1 "Enable IPv4 hash function"; 854 _ 2 rsvd; 855 en_ip6 1 "Enable IPv6 hash function"; 856 en_tcpip6 1 "Enable TcpIPv6 hash function"; 857 en_udp4 1 "Enable UdpIPV4"; 858 en_udp6 1 "Enable UdpIPV6"; 859 _ 8; 860 }; 861 862 // 8.2.3.7.13 863 register rqtc rw addr(base, 0x0EC70) "RSS Queues Per Traffic Class Register" { 864 rqtc0 3 "Number of bits to use for RSS redirection TC0"; 865 _ 1 rsvd; 866 rqtc1 3 "Number of bits to use for RSS redirection TC1"; 867 _ 1 rsvd; 868 rqtc2 3 "Number of bits to use for RSS redirection TC2"; 869 _ 1 rsvd; 870 rqtc3 3 "Number of bits to use for RSS redirection TC3"; 871 _ 1 rsvd; 872 rqtc4 3 "Number of bits to use for RSS redirection TC4"; 873 _ 1 rsvd; 874 rqtc5 3 "Number of bits to use for RSS redirection TC5"; 875 _ 1 rsvd; 876 rqtc6 3 "Number of bits to use for RSS redirection TC6"; 877 _ 1 rsvd; 878 rqtc7 3 "Number of bits to use for RSS redirection TC7"; 879 _ 1 rsvd; 880 }; 881 882 // 8.2.3.7.14 883 regarray rssrk rw addr(base, 0x0EB80) [10] "RSS Random Key Register" { 884 key 32 "RSS Key Word n (bytes 4*n to 4*n+3) of the RSS random key"; 885 }; 886 887 // 8.2.3.7.15 888 regarray reta rw addr(base, 0x0EB00) [32] "Redirection Table" { 889 entry0 4 "RSS output index for hash value 4n+0"; 890 _ 4 rsvd; 891 entry1 4 "RSS output index for hash value 4n+1"; 892 _ 4 rsvd; 893 entry2 4 "RSS output index for hash value 4n+2"; 894 _ 4 rsvd; 895 entry3 4 "RSS output index for hash value 4n+3"; 896 _ 4 rsvd; 897 }; 898 899 // 8.2.3.7.16 900 regarray saqf rw addr(base, 0x0E000) [128] "Source Address Queue Filter" { 901 src_addr 32 "IP Source Address"; 902 }; 903 904 // 8.2.3.7.17 905 regarray daqf rw addr(base, 0x0E200) [128] "Destination Address Queue Filter" { 906 dst_addr 32 "IP Destination Address"; 907 }; 908 909 // 8.2.3.7.18 910 regarray sdpqf rw addr(base, 0x0E400) [128] "Source Destination Port Queue Filter" { 911 src_port 16 "TCP/UDP Source Port"; 912 dst_port 16 "TCP/UDP Destination Port"; 913 }; 914 915 constants l4_proto "IP L4 protocol" { 916 l4tcp = 0b00; 917 l4udp = 0b01; 918 l4sctp = 0b10; 919 l4other = 0b11; 920 }; 921 922 // 8.2.3.7.19 923 /* see l34timir */ 924 regarray ftqf rw addr(base, 0x0E600) [128] "Five tuple Queue Filter" { 925 protocol 2 type(l4_proto) "IP L4 protocol"; 926 priority 3 "Priority value in case more than one 5-tuple filter matches"; 927 _ 3 mbz; /* rsvd */ 928 pool 6 "The pool Index of the pool associated with this filter"; 929 _ 11 mbz; /* rsvd */ 930 m_srcaddr 1 "Mask source address comparison"; 931 m_dstaddr 1 "Mask destination address comparison"; 932 m_srcport 1 "Mask source port comparison"; 933 m_dstport 1 "Mask destination port comparison"; 934 m_protocol 1 "Mask protocol comparison"; 935 pool_mask 1 "Mask bit for the Pool field"; 936 queue_en 1 "Queue Enable"; 937 }; 938 939 // 8.2.3.7.20 940 register synqf rw addr(base, 0x0EC30) "SYN Packet Queue Filter" { 941 queue_en 1 "Queue Enable"; 942 rx_queue 7 "Identifies an Rx queue associated with SYN packets"; 943 _ 23 rsvd; 944 synqfp 1 "Defines the priority between SYNQF and 5-tuples filter"; 945 }; 946 947 // 8.2.3.7.21 948 regarray etqf rw addr(base, 0x05128) [8] "EType Queue Filter" { 949 etype 16 "Identifies the protocol running on top of IEEE 802"; 950 uprio 3 "User Priority"; 951 uprio_en 1 "User Priority Enable"; 952 pool 6 "Determines the target pool for the packet"; 953 pool_en 1 "Pool Enable"; 954 fcoe 1 "FCoE"; 955 _ 2 rsvd; 956 timestamp 1 "IEEE 1588 time stamp"; 957 filter_en 1 "Filter Enable"; 958 }; 959 960 // 8.2.3.7.22 961 regarray etqs rw addr(base, 0x0EC00) [8] "EType Queue Select" { 962 _ 16 rsvd; 963 rx_queue 7 "Identifies the Rx queue associated with this EType"; 964 _ 6 rsvd; 965 lli 1 "When set, packets that match this filter generate a LLI"; 966 _ 1 rsvd; 967 queue_en 1 "Queue Enable"; 968 }; 969 970 // 8.2.3.7.23 971 register rxfeccerr0 addr(base, 0x051B8) "Rx Filter ECC Err Insertion 0" { 972 _ 9 rsvd; 973 eccflt_en 1 "Filter ECC Error indication Enablement"; 974 _ 22 rsvd; 975 }; 976 977 978 /************************************ 979 * 8.2.3.8 Receive DMA Registers 980 ***********************************/ 981 // Some of the following register arrays are split in two since they are 982 // allocated in two non-continuous memory regions. 983 984 // 8.2.3.8.1 985 regarray rdbal_1 rw addr(base, 0x01000) [64; 0x40] 986 "Receive Descriptor Base Address Low (#0-#63)" 987 type(uint32); 988 989 regarray rdbal_2 rw addr(base, 0x0d000) [64; 0x40] 990 "Receive Descriptor Base Address Low (#64-#127)" 991 type(uint32); 992 993 // 8.2.3.8.2 994 regarray rdbah_1 rw addr(base, 0x01004) [64; 0x40] 995 "Receive Descriptor Base Address High (#0-#63)" 996 type(uint32); 997 998 regarray rdbah_2 rw addr(base, 0x0d004) [64; 0x40] 999 "Receive Descriptor Base Address High (#64-#127)" 1000 type(uint32); 1001 1002 // 8.2.3.8.3 1003 regarray rdlen_1 rw addr(base, 0x01008) [64; 0x40] 1004 "Receive Descriptor Length (#0-#63)" 1005 type(uint32); 1006 1007 regarray rdlen_2 rw addr(base, 0x0d008) [64; 0x40] 1008 "Receive Descriptor Length (#64-#127)" 1009 type(uint32); 1010 1011 // 8.2.3.8.4 1012 regarray rdh_1 rw addr(base, 0x01010) [64; 0x40] 1013 "Receive Descriptor Head (#0-#63)" 1014 type(uint32); 1015 1016 regarray rdh_2 rw addr(base, 0x0d010) [64; 0x40] 1017 "Receive Descriptor Head (#64-#127)" 1018 type(uint32); 1019 1020 // 8.2.3.8.5 1021 regarray rdt_1 rw addr(base, 0x01018) [64; 0x40] 1022 "Receive Descriptor Tail (#0-#63)" 1023 type(uint32); 1024 1025 regarray rdt_2 rw addr(base, 0x0d018) [64; 0x40] 1026 "Receive Descriptor Tail (#64-#127)" 1027 type(uint32); 1028 1029 // 8.2.3.8.6 1030 regtype rxdctl "Receive Descriptor Control" { 1031 _ 25 rsvd; 1032 enable 1 "Receive Queue Enable"; 1033 _ 4 rsvd; 1034 vme 1 "VLAN Mode Enable"; 1035 _ 1 rsvd; 1036 }; 1037 1038 regarray rxdctl_1 rw addr(base, 0x01028) [64; 0x40] 1039 "Receive Descriptor Tail (#0-#63)" 1040 type(rxdctl); 1041 1042 regarray rxdctl_2 rw addr(base, 0x0d028) [64; 0x40] 1043 "Receive Descriptor Tail (#64-#127)" 1044 type(rxdctl); 1045 1046 // 8.2.3.8.7 1047 constants rx_desctype "RX Descriptor Type" { 1048 legacy = 0b000 "Legacy"; 1049 adv_1buf = 0b001 "Advanced descriptor one buffer"; 1050 adv_hdrsp = 0b010 "Advanced descriptor header splitting"; 1051 adv_usehb = 0b101 "Advanced descriptor header splitting always use header buffer"; 1052 }; 1053 1054 regtype srrctl "Split Receive Control Registers" { 1055 bsz_pkt 5 "Receive Buffer Size for Packet Buffer"; 1056 _ 3 mbz; 1057 bsz_hdr 6 "Receive Buffer Size for Header Buffer"; 1058 _ 8 rsvd; 1059 rdmts 3 "Receive Descriptor Minimum Threshold Size"; 1060 desctype 3 type(rx_desctype) "Define the descriptor type"; 1061 drop_en 1 "Drop Enabled"; 1062 _ 3 rsvd; 1063 }; 1064 1065 regarray srrctl_1 rw addr(base, 0x01014) [64; 0x40] 1066 "Split Receive Control Registers (#0-#63)" 1067 type(srrctl); 1068 1069 regarray srrctl_2 rw addr(base, 0x0d014) [64; 0x40] 1070 "Split Receive Control Registers (#64-#127)" 1071 type(srrctl); 1072 1073 // 8.2.3.8.8 1074 register rdrxctl rw addr(base, 0x02f00) "Receive DMA Control Register" { 1075 _ 1 rsvd; 1076 crcstrip 1 "Rx CRC Strip indication to the Rx DMA unit"; 1077 _ 1 rsvd; 1078 dma_initok 1 ro "DMA Init Done"; 1079 _ 13 rsvd; 1080 rscfrstsz 5 mbz "Defines a minimum packet size for a RSC packet"; 1081 _ 3 rsvd; 1082 rscackc 1 mb1 "RSC Coalescing on ACK Change"; 1083 fcoe_wrfix 1 mb1 "FCoE Write Exchange Fix"; 1084 _ 5 rsvd; 1085 }; 1086 1087 // 8.2.3.8.9 1088 regarray rxpbsize rw addr(base, 0x03C00) [8] "Receive Packet Buffer Size" { 1089 _ 10 rsvd; 1090 size 10 "Receive Packet Buffer Size for traffic class n"; 1091 _ 12 rsvd; 1092 }; 1093 1094 // 8.2.3.8.10 1095 register rxctrl rw addr(base, 0x03000) "Receive Control Register" { 1096 rxen 1 "Receive Enable"; 1097 _ 31 rsvd; 1098 }; 1099 1100 // 8.2.3.8.11 1101 register rxmemwrap ro addr(base, 0x03190) "Rx Packet Buffer Flush Detect" { 1102 tc0_wrap 3 "Packet Buffer 0 Wrap Around Counter"; 1103 tc0_empty 1 "Packet Buffer 0 Empty"; 1104 tc1_wrap 3 "Packet Buffer 1 Wrap Around Counter"; 1105 tc1_empty 1 "Packet Buffer 1 Empty"; 1106 tc2_wrap 3 "Packet Buffer 2 Wrap Around Counter"; 1107 tc2_empty 1 "Packet Buffer 2 Empty"; 1108 tc3_wrap 3 "Packet Buffer 3 Wrap Around Counter"; 1109 tc3_empty 1 "Packet Buffer 3 Empty"; 1110 tc4_wrap 3 "Packet Buffer 4 Wrap Around Counter"; 1111 tc4_empty 1 "Packet Buffer 4 Empty"; 1112 tc5_wrap 3 "Packet Buffer 5 Wrap Around Counter"; 1113 tc5_empty 1 "Packet Buffer 5 Empty"; 1114 tc6_wrap 3 "Packet Buffer 6 Wrap Around Counter"; 1115 tc6_empty 1 "Packet Buffer 6 Empty"; 1116 tc7_wrap 3 "Packet Buffer 7 Wrap Around Counter"; 1117 tc7_empty 1 "Packet Buffer 7 Empty"; 1118 }; 1119 1120 // 8.2.3.8.12 (Content not documented in spec, info here from FreeBSD driver) 1121 register rscdbu rw addr(base, 0x03028) "RSC Data Buffer Control Register" { 1122 _ 7 rsvd; 1123 rscackdis 1 "Disable RSC for ACK packets"; 1124 _ 24 rsvd; 1125 }; 1126 1127 // 8.2.3.8.13 1128 constants rsc_maxdesc "Maximum descriptors per Large receive" { 1129 max_1desc = 0b00 "Maximum of 1 descriptor per large receive"; 1130 max_4desc = 0b01 "Maximum of 4 descriptors per large receive"; 1131 max_8desc = 0b10 "Maximum of 8 descriptors per large receive"; 1132 max_16desc = 0b11 "Maximum of 16 descriptors per large receive"; 1133 }; 1134 1135 regtype rscctl "RSC Control" { 1136 rsc_en 1 "RSC Enable"; 1137 _ 1 rsvd; 1138 maxdesc 2 type(rsc_maxdesc) "Maximum descriptors per Large receive"; 1139 _ 28 rsvd; 1140 }; 1141 1142 regarray rscctl_1 rw addr(base, 0x0102c) [64; 0x40] 1143 "RSC Control (#0-#63)" 1144 type(rscctl); 1145 1146 regarray rscctl_2 rw addr(base, 0x0d02c) [64; 0x40] 1147 "RSC Control (#64-#127)" 1148 type(rscctl); 1149 1150 1151 /************************************ 1152 * 8.2.3.9 Transmit Registers 1153 ***********************************/ 1154 1155 // 8.2.3.9.1 1156 register dtxmxszrq rw addr(base, 0x08100) "DMA Tx TCP Max Allow Size Requests" { 1157 max_bytes 12 "Max allowed number of bytes requests"; 1158 _ 20 rsvd; 1159 }; 1160 1161 // 8.2.3.9.2 1162 register dmatxctl rw addr(base, 0x04a80) "DMA Tx Control" { 1163 txen 1 "Transmit Enable"; 1164 _ 2 rsvd; 1165 gdv 1 "Global Double VLAN Mode"; 1166 _ 12 rsvd; 1167 vlet 16 "VLAN Ether-Type"; 1168 }; 1169 1170 // 8.2.3.9.3 1171 register dtxtcpflgl rw addr(base, 0x04a88) "DMA Tx TCP Flags Control Low" { 1172 tcp_flgfsts 12 "TCP Flags First Segment"; 1173 _ 4 rsvd; 1174 tcp_flgmdls 12 "TCP Flags Middle Segments"; 1175 _ 4 rsvd; 1176 }; 1177 1178 // 8.2.3.9.4 1179 register dtxtcpflgh rw addr(base, 0x04a8c) "DMA Tx TCP Flags Control High" { 1180 tcp_flglsts 12 "TCP Flags Last Segment"; 1181 _ 20 rsvd; 1182 }; 1183 1184 // 8.2.3.9.5 1185 regarray tdbal rw addr(base, 0x06000) [128; 0x40] 1186 "Transmit Descriptor Base Address Low" 1187 type(uint32); 1188 1189 // 8.2.3.9.6 1190 regarray tdbah rw addr(base, 0x06004) [128; 0x40] 1191 "Transmit Descriptor Base Address Low" 1192 type(uint32); 1193 1194 // 8.2.3.9.7 1195 regarray tdlen rw addr(base, 0x06008) [128; 0x40] 1196 "Transmit Descriptor Length" 1197 type(uint32); 1198 1199 // 8.2.3.9.8 1200 // rw is only partially accurate here. This register must only be written 1201 // directly after reset. 1202 regarray tdh rw addr(base, 0x06010) [128; 0x40] 1203 "Transmit Descriptor Head" 1204 type(uint32); 1205 1206 // 8.2.3.9.9 1207 regarray tdt rw addr(base, 0x06018) [128; 0x40] 1208 "Transmit Descriptor Tail" 1209 type(uint32); 1210 1211 // 8.2.3.9.10 1212 regarray txdctl rw addr(base, 0x06028) [128; 0x40] "Transmit Descriptor Control" { 1213 pthresh 7 "Pre-Fetch Threshold"; 1214 _ 1 rsvd; 1215 hthresh 7 "Host Threshold"; 1216 _ 1 rsvd; 1217 wthresh 7 "Write-Back Threshold"; 1218 _ 2 rsvd; 1219 enable 1 "Transmit Queue Enable"; 1220 swflsh 1 "Transmit Software Flush"; 1221 _ 5 rsvd; 1222 }; 1223 1224 // 8.2.3.9.11 1225 regarray tdwbal rw addr(base, 0x06038) [128; 0x40] "Tx Descriptor Completion Write Back Address Low" { 1226 headwb_en 1 "Head Write-Back Enable"; 1227 _ 1 rsvd; 1228 headwb_low 30 "Lowest 32 bits of the head write-back memory location"; 1229 }; 1230 1231 // 8.2.3.9.12 1232 regarray tdwbah rw addr(base, 0x0603c) [128; 0x40] "Tx Descriptor Completion Write Back Address High" { 1233 headwb_high 32 "Highest 32 bits of the head write-back memory location"; 1234 }; 1235 1236 // 8.2.3.9.13 1237 regarray txpbsize rw addr(base, 0x0cc00) [8] "Transmit Packet Buffer Size" { 1238 _ 10 rsvd; 1239 size 10 "Transmit packet buffer size of TCn"; 1240 _ 12 rsvd; 1241 }; 1242 1243 // 8.2.3.9.14 1244 register mngtxmap rw addr(base, 0x0CD10) "Manageability Transmit TC Mapping" { 1245 map 3 "Map value indicates the TC that the transmit manageability traffic is routed to"; 1246 _ 29 rsvd; 1247 }; 1248 1249 // 8.2.3.9.15 1250 register mtqc rw addr(base, 0x08120) "Multiple Transmit Queues Command Register" { 1251 rt_en 1 "DCB Enabled Mode"; 1252 vt_en 1 "Virtualization Enabled Mode"; 1253 num_tc 2 "Number of TCs or Number of Tx Queues per Pools"; 1254 _ 28 rsvd; 1255 }; 1256 1257 // 8.2.3.9.16 1258 regarray txpbthresh rw addr(base, 0x04950) [8] "Tx Packet Buffer Threshold" { 1259 thresh 10 "Threshold used for checking room place in Tx packet buffer of TCn"; 1260 _ 22 rsvd; 1261 }; 1262 1263 1264 /************************************ 1265 * 8.2.3.10 DCB Registers 1266 ***********************************/ 1267 1268 // 8.2.3.10.1 1269 register rtrpcs rw addr(base, 0x02430) "DCB Receive Packet Plane Control and Status" { 1270 _ 1 rsvd; 1271 rrm 1 "Receive Recycle Mode"; 1272 rac 1 "Receive Arbitration Control"; 1273 _ 13 rsvd; 1274 lrpb 3 "Last Received Packet Buffer Status Indication"; 1275 _ 13 rsvd; 1276 }; 1277 1278 // 8.2.3.10.2 1279 register rttdcs rw addr(base, 0x04900) "DCP Transmit Descriptor Plane Control and Status" { 1280 tdpac 1 "TC Transmit Descriptor Plane Arbitration Control"; 1281 vmpac 1 "VM Transmit Descriptor Plane Arbitration Control"; 1282 _ 2 rsvd; 1283 tdrm 1 "TC Transmit descriptor plane recycle mode"; 1284 _ 1 rsvd; 1285 arbdis 1 "DCB Arbiters Disable"; 1286 _ 10 rsvd; 1287 lttdesc 3 ro "Last Transmitted TC"; 1288 _ 2 rsvd; 1289 bdpm 1 "Bypass data pipe Monitor"; 1290 bpbfsm 1 "Bypass Packet Buffer Free Space Monitor"; 1291 _ 7 rsvd; 1292 speed_chg 1 "Link speed has changed"; 1293 }; 1294 1295 // 8.2.3.10.3 1296 register rttpcs rw addr(base, 0x0CD00) "DCB Transmit Packet Plane Control and Status" { 1297 _ 5 rsvd; 1298 tppac 1 "Transmit Packet Plane Arbitration Control"; 1299 _ 2 rsvd; 1300 tprm 1 "Transmit packet plane recycle mode"; 1301 _ 13 rsvd; 1302 arbd 10 "ARB_delay"; 1303 }; 1304 1305 // 8.2.3.10.4 1306 register rtrup2tc rw addr(base, 0x03020) "DCB Receive User Priority to Traffic Class" { 1307 up0map 3 "Receive UP 0 to TC Mapping"; 1308 up1map 3 "Receive UP 1 to TC Mapping"; 1309 up2map 3 "Receive UP 2 to TC Mapping"; 1310 up3map 3 "Receive UP 3 to TC Mapping"; 1311 up4map 3 "Receive UP 4 to TC Mapping"; 1312 up5map 3 "Receive UP 5 to TC Mapping"; 1313 up6map 3 "Receive UP 6 to TC Mapping"; 1314 up7map 3 "Receive UP 7 to TC Mapping"; 1315 _ 8 rsvd; 1316 }; 1317 1318 // 8.2.3.10.5 1319 register rttup2tc rw addr(base, 0x0C800) "DCB Transmit User Priority to Traffic Class" { 1320 up0map 3 "Receive UP 0 to TC Mapping"; 1321 up1map 3 "Receive UP 1 to TC Mapping"; 1322 up2map 3 "Receive UP 2 to TC Mapping"; 1323 up3map 3 "Receive UP 3 to TC Mapping"; 1324 up4map 3 "Receive UP 4 to TC Mapping"; 1325 up5map 3 "Receive UP 5 to TC Mapping"; 1326 up6map 3 "Receive UP 6 to TC Mapping"; 1327 up7map 3 "Receive UP 7 to TC Mapping"; 1328 _ 8 rsvd; 1329 }; 1330 1331 // 8.2.3.10.6 1332 regarray rtrpt4c rw addr(base, 0x02140) [8] "DCB Receive Packet Plane T4 Config" { 1333 crq 9 "Credit refill quantum"; 1334 bwg 3 "Bandwidth group index"; 1335 mcl 12 "Max credit limit"; 1336 _ 6 rsvd; 1337 gsp 1 "Group strict priority"; 1338 lsp 1 "Link strict priority"; 1339 }; 1340 1341 // 8.2.3.10.9 1342 regarray rttdt2c rw addr(base, 0x04910) [8] "DCB Transmit Descriptor Plane T2 Config" { 1343 crq 9 "Credit refill quantum"; 1344 bwg 3 "Bandwidth group index"; 1345 mcl 12 "Max credit limit"; 1346 _ 6 rsvd; 1347 gsp 1 "Group strict priority"; 1348 lsp 1 "Link strict priority"; 1349 }; 1350 1351 // 8.2.3.10.10 1352 regarray rttpt2c rw addr(base, 0x0CD20) [8] "DCB Transmit Packet Plane T2 Config" { 1353 crq 9 "Credit refill quantum"; 1354 bwg 3 "Bandwidth group index"; 1355 mcl 12 "Max credit limit"; 1356 _ 6 rsvd; 1357 gsp 1 "Group strict priority"; 1358 lsp 1 "Link strict priority"; 1359 }; 1360 1361 // 8.2.3.10.13 1362 register rttdqsel rw addr(base, 0x04904) "DCB Transmit Descriptor Plane Queue Select" { 1363 txdq_idx 7 "Tx Descriptor Queue Index"; 1364 _ 25 rsvd; 1365 }; 1366 1367 // 8.2.3.10.14 1368 register rttdt1c rw addr(base, 0x04908) "DCB Transmit Descriptor Plane T1 Config" { 1369 crq 14 "Credit refill quantum"; 1370 _ 18 rsvd; 1371 }; 1372 1373 // 8.2.3.10.16 1374 register rttbcnrc rw addr(base, 0x04984) "DCB Transmit Rate-Scheduler Config" { 1375 rf_dec 14 "Tx rate-scheduler rate factor hexadecimal part"; 1376 rf_int 10 "Tx rate-scheduler rate factor integral part"; 1377 _ 7 rsvd; 1378 rs_ena 1 "Tx rate-scheduler enable"; 1379 }; 1380 1381 1382 /************************************ 1383 * 8.2.3.11 DCA Registers 1384 ***********************************/ 1385 1386 // 8.2.3.11.1 1387 regtype dca_rxctrl "Rx DCA Control Register" { 1388 _ 5 rsvd; 1389 rxdca_desc 1 "Descriptor DCA EN"; 1390 rxdca_hdr 1 "Rx Header DCA EN"; 1391 rxdca_payl 1 "Payload DCA EN"; 1392 _ 1 rsvd; 1393 rxdesc_rdro 1 "Rx Descriptor Read Relax Order Enable"; 1394 _ 1 rsvd; 1395 rxdesc_wbro 1 mbz "Rx Descriptor Write Back Relax Order Enable"; 1396 _ 1 rsvd; 1397 rxdata_wrro 1 "Rx data Write Relax Order Enable"; 1398 _ 1 rsvd; 1399 rxhdr_ro 1 "Rx Split Header Relax Order Enable"; 1400 _ 8 rsvd; 1401 cpuid 8 "Physical ID"; 1402 }; 1403 1404 regarray dca_rxctrl_1 rw addr(base, 0x0100c) [64; 0x40] 1405 "Rx DCA Control Register (#0-#63)" 1406 type(dca_rxctrl); 1407 1408 regarray dca_rxctrl_2 rw addr(base, 0x0d00c) [64; 0x40] 1409 "Rx DCA Control Register (#64-#127)" 1410 type(dca_rxctrl); 1411 1412 // 8.2.3.11.2 1413 regarray dca_txctrl rw addr(base, 0x0600c) [128; 0x40] "Tx DCA Control Registers" { 1414 _ 5 rsvd; 1415 txdesc_dca 1 "Descriptor DCA Enable"; 1416 _ 3 rsvd; 1417 txdesc_rdro 1 "Tx Descriptor Read Relax Order Enable"; 1418 _ 1 rsvd; 1419 txdesc_wbro 1 "Relax Order Enable of Tx Descriptor well as head pointer write back"; 1420 _ 1 rsvd; 1421 txdata_rdro 1 "Tx Data Read Relax Order Enable"; 1422 _ 10 rsvd; 1423 cpuid 8 "Physical ID"; 1424 }; 1425 1426 // 8.2.3.11.3 1427 register dca_id ro addr(base, 0x11070) "DCA Requester ID Information Register" { 1428 fun_no 3 "Function Number"; 1429 dev_no 5 "Device Number"; 1430 bus_no 8 "Bus Number"; 1431 _ 16 rsvd; 1432 }; 1433 1434 constants dca_mode "DCA Mode" { 1435 legacy_dca = 0b0000 "Legacy DCA is supported"; 1436 dca10 = 0b0001 "DCA 1.0 is supported"; 1437 }; 1438 1439 // 8.2.3.11.4 1440 register dca_ctrl rw addr(base, 0x11074) "DCA Control Register" { 1441 dca_dis 1 "DCA Disable"; 1442 dca_mode 4 type(dca_mode) "DCA Mode"; 1443 _ 27 rsvd; 1444 }; 1445 1446 1447 /************************************ 1448 * 8.2.3.12 - 8.2.3.18 TODO 1449 ***********************************/ 1450 1451 // 8.2.3.12.4 1452 register sectxminifg rw addr(base, 0x08810) "Security Tx Buffer Minimum IFG" { 1453 minsecifg 4 "Minimum IFG between packets"; 1454 _ 4; 1455 sectxdcb 5 "If PFC enabled, set to 0x1f, else set to 0x10"; 1456 _ 19; 1457 }; 1458 1459 // 8.2.3.12.5 1460 register secrxctrl rw addr(base, 0x08d00) "Security Rx Control" { 1461 secrx_dis 1 "Rx Security Offload Disable Bit"; 1462 rx_dis 1 "Disable Sec Rx Path"; 1463 _ 30 rsvd; 1464 }; 1465 1466 // 8.2.3.12.6 1467 register secrxstat ro addr(base, 0x08d04) "Security Rx Status" { 1468 sr_rdy 1 "Rx security block ready for mode change"; 1469 sr_off_dis 1 "Security offload is disabled by fuse or strapping pin"; 1470 eec_rxerr 1 "Unrecoverable ECC error in an Rx SA table occurred"; 1471 _ 29 rsvd; 1472 }; 1473 1474 /************************************ 1475 * 8.2.3.19 Timers Registers 1476 ***********************************/ 1477 1478 // 8.2.3.19.1 1479 register tcptimer rw addr(base, 0x0004c) "TCP Timer" { 1480 duration 8 "Duration of the TCP interrupt interval, in ms"; 1481 kickstart 1 "Counter kick-start"; 1482 tcpcnt_en 1 "TCP Count Enable"; 1483 tcpcnt_fin 1 "TCP Count Finish"; 1484 loop 1 "TCP Loop"; 1485 _ 20 rsvd; 1486 }; 1487 1488 1489 /************************************ 1490 * 8.2.3.20 FCoE Registers 1491 ***********************************/ 1492 // TODO 1493 1494 1495 /************************************ 1496 * 8.2.3.21 Flow Director Registers 1497 ***********************************/ 1498 1499 constants pballoc "Memory allocation for the flow director filters" { 1500 mem_none = 0b00; 1501 mem_64k = 0b01; 1502 mem_128k = 0b10; 1503 mem_256k = 0b11; 1504 }; 1505 1506 // 8.2.3.21.1 1507 register fdirctrl rw addr(base, 0x0EE00) "Flow Director Filters Control Register" { 1508 pballoc 2 type(pballoc) "Memory allocation for the flow director filters"; 1509 _ 1 rsvd; 1510 init_done 1 "Flow director initialization completion indication"; 1511 perf_match 1 "Flow director filters mode of operation"; 1512 rep_stat 1 "Report flow director filter's status on matching packets"; 1513 _ 1 rsvd; 1514 rep_statalw 1 "Report flow director filter's status always"; 1515 drop_queue 7 "Absolute Rx queue index used for the dropped packets"; 1516 _ 1 rsvd; 1517 flex_off 5 "Offset of a flexible 2-byte tuple in packet"; 1518 _ 3 rsvd; 1519 max_len 4 "Maximum linked list length"; 1520 full_thresh 4 "Recommended minimum number of flows that should remain unused"; 1521 }; 1522 1523 // 8.2.3.21.2 1524 register fdirhkey rw addr(base, 0x0EE68) "Flow Director Filters Lookup Table HASH Key" { 1525 key 32 "Programmable hash lookup table key"; 1526 }; 1527 1528 // 8.2.3.21.3 1529 register fdirskey rw addr(base, 0x0EE6C) "Flow Director Filters Signature Hash Key " { 1530 key 32 "rogrammable Signature Key"; 1531 }; 1532 1533 // 8.2.3.21.4 1534 register fdirdip4m rw addr(base, 0x0EE3C) "Flow Director Filters DIPv4 Mask" { 1535 ipm 32 "Mask Destination IPv4 Address"; 1536 }; 1537 1538 // 8.2.3.21.5 1539 register fdirsip4m rw addr(base, 0x0EE40) "Flow Director Filters Source IPv4 Mask" { 1540 ipm 32 "Mask Source IPv4 Address"; 1541 }; 1542 1543 // 8.2.3.21.6 1544 register fdirtcpm rw addr(base, 0x0EE44) "Flow Director Filters TCP Mask" { 1545 sportm 16 "Mask TCP Source Port"; 1546 dportm 16 "Mask TCP Destination Port"; 1547 }; 1548 1549 // 8.2.3.21.7 1550 register fdirudpm rw addr(base, 0x0EE48) "Flow Director Filters UDP Mask" { 1551 sportm 16 "Mask UDP Source Port"; 1552 dportm 16 "Mask UDP Destination Port"; 1553 }; 1554 1555 // 8.2.3.21.8 1556 register fdirip6m rw addr(base, 0x0EE74) "Flow Director Filters IPv6 Mask" { 1557 sipm 16 "Mask Source IPv6 address"; 1558 dipm 16 "Mask Destination IPv6 address"; 1559 }; 1560 1561 // 8.2.3.21.9 1562 register fdirm rw addr(base, 0x0EE70) "Flow Director Filters Other Mask" { 1563 vlanid 1 "Mask VLAN ID tag"; 1564 vlanp 1 "Mask VLAN Priority tag"; 1565 pool 1 "Mask Pool"; 1566 l4p 1 "Mask L4 Protocol"; 1567 flex 1 "Mask Flexible Tuple"; 1568 dipv6 1 "Mask Destination IPv6"; 1569 _ 26 rsvd; 1570 }; 1571 1572 // 8.2.3.21.10 1573 register fdirfree rw addr(base, 0x0EE38) "Flow Director Filters Free" { 1574 free 16 "Number of free filters in the flow director Filters logic"; 1575 coll 15 "Number of filters with collision indication"; 1576 _ 1 rsvd; 1577 }; 1578 1579 // 8.2.3.21.11 1580 register fdirlen rc addr(base, 0x0EE4C) "Flow Director Filters Length" { 1581 maxlen 6 "Longest linked list of filters in the table"; 1582 _ 2 rsvd; 1583 bucket_len 6 "The length of the linked list indicated by a query command"; 1584 _ 2 rsvd; 1585 maxhash 15 "Hash value of the filter that updated the value of the MAXLEN"; 1586 _ 1 rsvd; 1587 }; 1588 1589 // 8.2.3.21.12 1590 register fdirustat rc addr(base, 0x0EE50) "Flow Director Filters Usage Statistics" { 1591 add 16 "Number of added filters"; 1592 remove 16 "Number of removed filters"; 1593 }; 1594 1595 // 8.2.3.21.13 1596 register fdirfstat rc addr(base, 0x0EE54) "Flow Director Filters Failed Usage Statistics" { 1597 fadd 8 "Number of failed added filters"; 1598 fremove 8 "Number of failed removed filters"; 1599 _ 16 rsvd; 1600 }; 1601 1602 // 8.2.3.21.14 1603 register fdirmatch rc addr(base, 0x0EE58) "Flow Director Filters Match Statistics" { 1604 pcnt 32 "Number of packets that matched any flow director filter"; 1605 }; 1606 1607 // 8.2.3.21.15 1608 register fdirmiss rc addr(base, 0x0EE5C) "Flow Director Filters Miss Match Statistics" { 1609 pcnt 32 "Number of packets that missed matched any flow director filter"; 1610 }; 1611 1612 // 8.2.3.21.16 1613 regarray fdirsipv6 rw addr(base, 0x0EE0C) [3] "Flow Director Filters Source IPv6" { 1614 ip6sa 32 "Three MS DWords of the source IPv6 address"; 1615 }; 1616 1617 // 8.2.3.21.17 1618 register fdiripsa rw addr(base, 0x0EE18) "Flow Director Filters IP SA" { 1619 ip4sa 32 "Source IPv4 address or LS Dword of the Source IPv6 address"; 1620 }; 1621 1622 // 8.2.3.21.18 1623 register fdiripda rw addr(base, 0x0EE1C) "Flow Director Filters IP DA" { 1624 ip4da 32 "Destination IPv4 address"; 1625 }; 1626 1627 // 8.2.3.21.19 1628 register fdirport rw addr(base, 0x0EE20) "Flow Director Filters Port" { 1629 source 16 "Source Port number"; 1630 dest 16 "Destination Port number"; 1631 }; 1632 1633 // 8.2.3.21.20 1634 register fdirvlan rw addr(base, 0x0EE24) "Flow Director Filters VLAN and FLEX Bytes" { 1635 vlan 16 "Vlan Tag"; 1636 flex 16 "Flexible tuple data"; 1637 }; 1638 1639 // 8.2.3.21.21 1640 register fdirhash rw addr(base, 0x0EE28) "Flow Director Filters Hash Signature" { 1641 hash 15 "Bucket hash value that identifies a filter's linked list"; 1642 buck_valid 1 "Bucket Valid (at least 1 filter in bucket)"; 1643 sig_swidx 15 "Signature / SW Index"; 1644 _ 1 rsvd; 1645 }; 1646 1647 constants fdir_cmd "Flow Director Filter Programming Command" { 1648 no_action = 0b00 "No Action"; 1649 add_flow = 0b01 "Add Flow"; 1650 rem_flow = 0b10 "Remove Flow"; 1651 qry_cmd = 0b11 "Query Command"; 1652 }; 1653 1654 constants l4_ptype "L4 Packet Type" { 1655 l4p_ud = 0b01 "UDP"; 1656 l4p_tcp = 0b10 "TCP"; 1657 l4p_sctp = 0b11 "SCTP"; 1658 }; 1659 1660 // 8.2.3.21.22 1661 register fdircmd rw addr(base, 0x0EE2C) "Flow Director Filters Command Register" { 1662 cmd 2 type(fdir_cmd) "Flow Director Filter Programming Command"; 1663 flt_valid 1 "Valid filter is found by the query command"; 1664 flt_update 1 "Filter Update Command"; 1665 ipv6_dmatch 1 "IP Destination match to IP6AT filter"; 1666 l4type 2 type(l4_ptype); 1667 ipv6 1 "IPv6 packet type"; 1668 clearht 1 "Clear Internal Flow Director Head and Tail Registers"; 1669 drop 1 "Packet Drop Action"; 1670 int 1 "Matched packet generates a LLI"; 1671 last 1 "Last filter indication in the linked list"; 1672 collision 1 "Collision Indication"; 1673 _ 2 rsvd; 1674 queue_en 1 "Enable routing matched packet to Rx-Queue"; 1675 rx_queue 7 "Rx Queue Index"; 1676 _ 1 rsvd; 1677 pool 6 "Pool (only for VT)"; 1678 _ 2 rsvd; 1679 }; 1680 1681 1682 /************************************ 1683 * 8.2.3.22 MAC Registers 1684 ***********************************/ 1685 1686 // 8.2.3.22.1 1687 register pcs1gcfig rw addr(base, 0x04200) "PCS_1G Global Config Register 1" { 1688 _ 30 rsvd; 1689 pcs_isolate 1 "Isolates the 1 GbE PCS logic from the MAC's data path"; 1690 _ 1 rsvd; 1691 }; 1692 1693 // 8.2.3.22.2 1694 register pcs1glctl rw addr(base, 0x04208) "PCG_1G link Control Register" { 1695 flv 1 "Forced Link 1 GbE Value"; 1696 _ 4 rsvd; 1697 force1glnk 1 "Force 1 GbE Link"; 1698 lnk_latchl 1 "Link Latch Low Enable"; 1699 _ 11 rsvd; 1700 an_1gto 1 "Auto Negotiation 1 GbE Timeout Enable"; 1701 _ 6 rsvd; 1702 lnk_okfixen 1 "Link OK Fix En"; 1703 _ 6 rsvd; 1704 }; 1705 1706 // 8.2.3.22.3 1707 register pcs1glsta ro addr(base, 0x0420C) "PCS_1G Link Status Register" { 1708 _ 4 rsvd; 1709 syncok_1g 1 "Sync OK 1 GbE"; 1710 _ 11 rsvd; 1711 an_1gcompl 1 "Auto Negotiation1 GbE Complete"; 1712 an_pagercv 1 "Auto-Negotiation Page Received"; 1713 an_1gto 1 "Auto Negotiation1 GbE Timed Out"; 1714 an_remflt 1 "Auto Negotiation Remote Fault"; 1715 an_error 1 rw "Auto Negotiation Error"; 1716 _ 11 rsvd; 1717 }; 1718 1719 constants pause_cap "PAUSE Capabilities" { 1720 no_pause = 0b00 "No PAUSE"; 1721 sym_pause = 0b01 "Symmetric PAUSE"; 1722 asym_pause = 0b10 "Asymmetric PAUSE toward link partner"; 1723 both_pause = 0b11 "Both symmetric and asymmetric PAUSE toward local device"; 1724 }; 1725 1726 constants remote_fault "Remote Fault Condition" { 1727 no_error = 0b00 "No error, link good"; 1728 lnk_fail = 0b01 "Link failure"; 1729 offline = 0b10 "Offline"; 1730 an_err = 0b11 "Auto-negotiation error"; 1731 }; 1732 1733 // 8.2.3.22.4 1734 register pcs1gana rw addr(base, 0x04218) "PCS_1 Gb/s Auto Negotiation Advanced Register" { 1735 _ 5 rsvd; 1736 fdc 1 "FD: Full-Duplex"; 1737 _ 1 rsvd; 1738 asm 2 type(pause_cap) "Local PAUSE Capabilities"; 1739 _ 3 rsvd; 1740 rflt 2 type(remote_fault) "Remote Fault"; 1741 _ 1 rsvd; 1742 nextp 1 "NEXTP: Next Page Capable"; 1743 _ 16 rsvd; 1744 }; 1745 1746 // 8.2.3.22.5 1747 register pcs1ganlp ro addr(base, 0x0421C) "PCS_1GAN LP Ability Register" { 1748 _ 5 rsvd; 1749 lpfd 1 "LP Full-Duplex (SerDes)"; 1750 lphd 1 "LP Half-Duplex (SerDes)"; 1751 lpasm 2 type(pause_cap) "LP PAUSE capability"; 1752 _ 3 rsvd; 1753 prf 2 type(remote_fault) "LP Remote Fault"; 1754 ack 1 "LP acknowledged page reception"; 1755 lpnextp 1 "LP Next Page Capable"; 1756 _ 16 rsvd; 1757 }; 1758 1759 // 8.2.3.22.6 1760 register pcs1gannp rw addr(base, 0x04220) "PCS_1G Auto Negotiation Next Page Transmit Register" { 1761 code 11 "Message/Unformatted Code Field"; 1762 toggle 1 "Toggle"; 1763 ack2 1 "Acknowledge2"; 1764 pgtype 1 "Message/ Unformatted Page"; 1765 _ 1 rsvd; 1766 nxtpg 1 "Next Page"; 1767 _ 16 rsvd; 1768 }; 1769 1770 // 8.2.3.22.7 1771 register pcs1ganlpnp ro addr(base, 0x04224) "PCS_1G Auto Negotiation LP's Next Page Register" { 1772 code 11 "Message/Unformatted Code Field"; 1773 toggle 1 "Toggle"; 1774 ack2 1 "Acknowledge2"; 1775 msgpg 1 "Message Page"; 1776 ack 1 "LP has acknowledge next page reception"; 1777 nxtpg 1 "Next Page"; 1778 _ 16 rsvd; 1779 }; 1780 1781 // 8.2.3.22.8 1782 register hlreg0 rw addr(base, 0x04240) "MAC Core Control 0 Register" { 1783 txcrcen 1 "Tx CRC Enable"; 1784 rxcrcstrp 1 "Rx CRC Strip"; 1785 jumboen 1 "Jumbo Frame Enable"; 1786 _ 7 mbz; 1787 txpaden 1 "Tx Pad Frame Enable"; 1788 _ 4 rsvd; 1789 lpbk 1 "Loopback enabled"; 1790 mdcspd 1 "MDC SPEED"; 1791 contmdc 1 "Continuous MDC"; 1792 _ 2 rsvd; 1793 prepend 4 "Prepend Value"; 1794 _ 3 rsvd; 1795 rxlenerrr 1 "Rx Length Error Reporting"; 1796 rxpadstrp 1 "Rx Padding Strip Enable"; 1797 _ 3 rsvd; 1798 }; 1799 1800 // 8.2.3.22.9 1801 register hlreg1 ro addr(base, 0x04244) "MAC Core Status 1 Register" { 1802 _ 5 rsvd; 1803 rxerrsym 1 rc "Error symbol received"; 1804 rxillsym 1 rc "Illegal symbol received"; 1805 rxidleerr 1 rc "Idle error received"; 1806 rxlclflt 1 rc "Local fault is or was active"; 1807 rxrmtflt 1 rc "Remote fault is or was active"; 1808 _ 22 rsvd; 1809 }; 1810 1811 constants pace "Pace" { 1812 p_10gbe = 0b0000"10 GbE (LAN)"; 1813 p_1gbe = 0b0001"1 GbE"; 1814 p_2gbe = 0b0010 "2 GbE"; 1815 p_3gbe = 0b0011 "3 GbE"; 1816 p_4gbe = 0b0100 "4 GbE"; 1817 p_5gbe = 0b0101 "5 GbE"; 1818 p_6gbe = 0b0110 "6 GbE"; 1819 p_7gbe = 0b0111 "7 GbE"; 1820 p_8gbe = 0b1000 "8 GbE"; 1821 p_9gbe = 0b1001 "9 GbE"; 1822 p_9gbe_wan = 0b1111 "9.294196 GbE (WAN)"; 1823 }; 1824 1825 // 8.2.3.22.10 1826 register pap rw addr(base, 0x04248) "Pause and Pace Register" { 1827 _ 16 rsvd; 1828 pace 4 type(pace) "Pace"; 1829 _ 12 rsvd; 1830 }; 1831 1832 constants mdi_opcode "OP Code" { 1833 addr_cycle = 0b00 "Address cycle (new protocol only)"; 1834 write_op = 0b01 "Write operation"; 1835 read_incad = 0b10 "Read increment address(new) /Read operation (old)"; 1836 read_op = 0b11 "Read operation (new protocol only)"; 1837 }; 1838 1839 constants mdi_stcode "ST Code" { 1840 new_proto = 0b00 "New protocol"; 1841 old_proto = 0b01 "Old protocol"; 1842 }; 1843 1844 // 8.2.3.22.11 1845 register msca rw addr(base, 0x0425C) "MDI Single Command and Address" { 1846 mdiadd 16 "MDI Address"; 1847 devadd 5 "DeviceType/Register Address"; 1848 phyadd 5 "PHY Address"; 1849 opcode 2 type(mdi_opcode) "OP Code"; 1850 stcode 2 type(mdi_stcode) "ST Code"; 1851 mdicmd 1 "MDI Command"; 1852 _ 1 rsvd; 1853 }; 1854 1855 // 8.2.3.22.12 1856 register msrwd rw addr(base, 0x04260) "MDI Single Read and Write Data" { 1857 mdiwrdata 16 "MDI Write Data"; 1858 mdirddata 16 "MDI Read Data"; 1859 }; 1860 1861 // 8.2.3.22.13 1862 register maxfrs rw addr(base, 0x04268) "Max Frame Size" { 1863 _ 16 rsvd; 1864 mfs 16 "Maximum frame size in bytes units"; 1865 }; 1866 1867 // 8.2.3.22.14 1868 register pcss1 ro addr(base, 0x04288) "XGXS Status 1" { 1869 _ 2 rsvd; 1870 pcsrcvlnkup 1 "PCS receive link up"; 1871 _ 4 rsvd; 1872 local_fault 1 "LF detected on transmit or receive path"; 1873 _ 24 rsvd; 1874 }; 1875 1876 constants dev_present "Device present" { 1877 dev_present = 0b10 "Device responding at this address"; 1878 }; 1879 1880 // 8.2.3.22.15 1881 register pcss2 ro addr(base, 0x0428C) "XGXS Status 2" { 1882 c10gbase_r 1 "PCS is able to support 10GBASE-R port type"; 1883 c10gbase_x 1 "PCS is able to support 10GBASE-X port type"; 1884 c10gbase_w 1 "PCS is able to support 10GBASE-W port type"; 1885 _ 7 rsvd; 1886 rx_lfault 1 "Local fault condition on the receive path"; 1887 tx_lfault 1 "Local fault condition on the transmit path"; 1888 _ 2 rsvd; 1889 dev_present 2 type(dev_present) "Device present"; 1890 _ 16 rsvd; 1891 }; 1892 1893 // 8.2.3.22.16 1894 register xpcss ro addr(base, 0x04290) "10GBASE-X PCS Status" { 1895 lane0_sync 1 "Lane 0 is synchronized"; 1896 lane1_sync 1 "Lane 1 is synchronized"; 1897 lane2_sync 1 "Lane 2 is synchronized"; 1898 lane3_sync 1 "Lane 3 is synchronized"; 1899 _ 8 rsvd; 1900 align_stat 1 "10GBASE-X PCS receive lanes aligned"; 1901 _ 3 rsvd; 1902 deskew_err 1 "De-skew error was detected"; 1903 algcolcnt4 1 "Align column count has reached four"; 1904 lane0_invc 1 "Invalid code was detected for that lane"; 1905 lane1_invc 1 "Invalid code was detected for that lane"; 1906 lane2_invc 1 "Invalid code was detected for that lane"; 1907 lane3_invc 1 "Invalid code was detected for that lane"; 1908 lane0_ccnt4 1 "Comma count for that lane has reached four"; 1909 lane1_ccnt4 1 "Comma count for that lane has reached four"; 1910 lane2_ccnt4 1 "Comma count for that lane has reached four"; 1911 lane3_ccnt4 1 "Comma count for that lane has reached four"; 1912 lane0_sigd 1 "Signal is detected"; 1913 lane1_sigd 1 "Signal is detected"; 1914 lane2_sigd 1 "Signal is detected"; 1915 lane3_sigd 1 "Signal is detected"; 1916 _ 2 rsvd; 1917 }; 1918 1919 // 8.2.3.22.17 1920 register serdesc rw addr(base, 0x04298) "SerDes Interface Control Register" { 1921 txl0_pol 1 "Changes bits polarity of MAC Tx lane 0"; 1922 txl1_pol 1 "Changes bits polarity of MAC Tx lane 1"; 1923 txl2_pol 1 "Changes bits polarity of MAC Tx lane 2"; 1924 txl3_pol 1 "Changes bits polarity of MAC Tx lane 3"; 1925 rxl0_pol 1 "Changes bits polarity of MAC Rx lane 0"; 1926 rxl1_pol 1 "Changes bits polarity of MAC Rx lane 1"; 1927 rxl2_pol 1 "Changes bits polarity of MAC Rx lane 2"; 1928 rxl3_pol 1 "Changes bits polarity of MAC Rx lane 3"; 1929 txl0_swiz 1 "Swizzles bits of MAC Tx lane 0"; 1930 txl1_swiz 1 "Swizzles bits of MAC Tx lane 1"; 1931 txl2_swiz 1 "Swizzles bits of MAC Tx lane 2"; 1932 txl3_swiz 1 "Swizzles bits of MAC Tx lane 3"; 1933 rxl0_swiz 1 "Swizzles bits of MAC Rx lane 0"; 1934 rxl1_swiz 1 "Swizzles bits of MAC Rx lane 1"; 1935 rxl2_swiz 1 "Swizzles bits of MAC Rx lane 2"; 1936 rxl3_swiz 1 "Swizzles bits of MAC Rx lane 3"; 1937 txl3_swap 2 "Determines Core destination Tx lane for MAC Tx lane 3"; 1938 txl2_swap 2 "Determines Core destination Tx lane for MAC Tx lane 2"; 1939 txl1_swap 2 "Determines Core destination Tx lane for MAC Tx lane 1"; 1940 txl0_swap 2 "Determines Core destination Tx lane for MAC Tx lane 0"; 1941 rxl3_swap 2 "Determines which Core lane is mapped to MAC Rx lane 3"; 1942 rxl2_swap 2 "Determines which Core lane is mapped to MAC Rx lane 2"; 1943 rxl1_swap 2 "Determines which Core lane is mapped to MAC Rx lane 1"; 1944 rxl0_swap 2 "Determines which Core lane is mapped to MAC Rx lane 0"; 1945 }; 1946 1947 // 8.2.3.22.18 1948 register macs rw addr(base, 0x0429C) "FIFO Status/CNTL Report Register" { 1949 xgssf_dis 1 "Use shift-fsm control, disable fix"; 1950 xgtxe_dis 1 "Disable tx_end on link-down"; 1951 xgsdsf_dis 1 "Disable align on invalid fix"; 1952 noncem_dis 1 "Disable nonce match"; 1953 _ 12 rsvd; 1954 cfgflt_len 8 "Config fault length"; 1955 cfgfifothr 4 "Config FIFO threshold"; 1956 txfifo_ur 1 "FIFO under run in xgmii_mux_tx_fifo"; 1957 txfifo_or 1 "FIFO overrun in xgmii_mux_tx_fifo"; 1958 rxfifo_ur 1 "FIFO under run in xgmii_mux_rx_fifo"; 1959 rxfifo_or 1 "FIFO overrun in xgmii_mux_rx_fifo"; 1960 }; 1961 1962 1963 constants pmad_10gbe "10 GbE PMA/PMD" { 1964 pmad_xaui = 0b00 "XAUI PMA/PMD"; 1965 pmad_kx4 = 0b01 "KX4 PMA/PMD"; 1966 pmad_cx4 = 0b10 "CX4 PMA/PMD"; 1967 }; 1968 1969 constants pmad_1gbe "PMA/PMD used for 1 Gb" { 1970 pmad_sfi = 0b0 "SFI PMA/PMD"; 1971 pmad_kxbx = 0b1 "KX or BX PMA/PMD"; 1972 }; 1973 1974 constants link_mode "Link Mode Select" { 1975 l1g = 0b000 "1 GbE link (no bp aneg)"; 1976 l10g_kx4 = 0b001 "10 GbE parallel link (KX4 no bp aneg)"; 1977 l1g_bx = 0b010 "1 GbE link with clause 37 aneg enable"; 1978 l10g_sfi = 0b011 "10 GbE serial link (SFI no bp aneg)"; 1979 l1g_kxr = 0b100 "KX/KX4/KR bp aneg; 1 GbE (Clause 37) aneg disabled"; 1980 l100m_sgmii = 0b101 "SGMII 100M/1 GbE link"; 1981 l1g_kxr_an = 0b110 "KX/KX4/KR bp aneg; 1 GbE (Clause 37) aneg enabled"; 1982 l1g_sgmii = 0b111 "KX/KX4/KR aneg enable. SGMII 100 Mb/s and 1GbE enable"; 1983 }; 1984 1985 constants aneg_pdt "Auto-Negotiation Parallel Detect Timer" { 1986 t1ms = 0b00 "1 ms"; 1987 t2ms = 0b01 "2 ms"; 1988 t5ms = 0b10 "5 ms"; 1989 t8ms = 0b11 "8 ms"; 1990 }; 1991 1992 // 8.2.3.22.19 1993 register autoc rw addr(base, 0x042A0) "Auto Negotiation Control Register" { 1994 flu 1 "Force Link Up"; 1995 anack2 1 "Auto-Negotiation Ack2 field"; 1996 ansf 5 "Auto-Negotiation Selector Field"; 1997 pmad_10gbe 2 type(pmad_10gbe) "10 GbE PMA/PMD over four differential pairs"; 1998 pmad_1gbe 1 type(pmad_1gbe) "PMA/PMD used for 1 GbE"; 1999 d10gmp 1 "Disables 10 GbE (KX4) on Dx (Dr/D3) without main-power"; 2000 ratd 1 "Restarts auto-negotiation on transition to Dx"; 2001 restart_an 1 "Applies new link settings and restarts relative auto-negotiation"; 2002 lms 3 type(link_mode) "Link Mode Select"; 2003 kr_sup 1 "KR supported"; 2004 fecr 1 "FEC requested from link partner"; 2005 feca 1 "FEC supported"; 2006 anrxat 4 "Backplane Auto-Negotiation Rx Align Threshold"; 2007 anrxdm 1 "Auto-Negotiation Rx Drift Mode"; 2008 anrxlm 1 "Auto-Negotiation Rx Loose Mode"; 2009 anpdt 2 type(aneg_pdt) "Auto-Negotiation Parallel Detect Timer"; 2010 rf 1 "Loaded to the RF of the auto-negotiation word"; 2011 pb 2 "Loaded to bits D11-D10 of the Link code word"; 2012 kx_sup 1 "KX supported"; 2013 kx4sup 1 "KX4 supported"; 2014 }; 2015 2016 2017 constants mac_lnkmode "MAC link mode status" { 2018 lms_1g = 0b00 "1 GbE"; 2019 lms_10g_par = 0b01 "10 GbE parallel"; 2020 lms_10g_ser = 0b10 "10 GbE serial"; 2021 lms_aneg = 0b11 "auto-negotiation"; 2022 }; 2023 2024 constants link_speed "MAC link speed status" { 2025 ls_100m = 0b01 "100 Mb/s"; 2026 ls_1g = 0b10 "1 GbE"; 2027 ls_10g = 0b11 "10 GbE"; 2028 }; 2029 2030 // 8.2.3.22.20 2031 register links ro addr(base, 0x042A4) "Link Status Register" { 2032 kxsig_det 1 "A signal is present"; 2033 fecsig_det 1 "FEC reports signal detected"; 2034 fecblk_lck 1 "FEC reached block lock"; 2035 krhberr 1 "10GbE serial KR_PCS high error rate"; 2036 krpcsbl 1 "10 GbE serial PCS block lock"; 2037 kxr_annprcv 1 "KX/KX4/KR AN Next Page Received"; 2038 kxr_anprcv 1 "KX/KX4/KR Backplane Auto Negotiation Page Received"; 2039 lnk_stat 1 "Link Up and there was no link down from last time read"; 2040 kx4sig_det 4 "Signal Detect of 10 GbE Parallel (KX4, CX4 or XAUI) (1bit per lane)"; 2041 krsig_det 1 "Signal Detect of 10 GbE serial (KR or SFI)"; 2042 l10g_syncst 4 "10G Parallel lane sync status (1bit per lane)"; 2043 l10g_algst 1 "10 GbE align_status"; 2044 l1g_syncst 1 "1G sync_status"; 2045 kxr_anrxid 1 "KX/KX4/KR Backplane Auto Negotiation Rx Idle"; 2046 l1g_anen 1 "PCS_1 GbE auto-negotiation is enabled"; 2047 l1g_lnken 1 "1 GbE PCS enabled for 1 GbE and SGMII operation"; 2048 l10g_lnken 1 "XGXS Enabled for 10 GbE operation"; 2049 fec_en 1 "Status of forwarderrorcorrection in 10 GbE serial link"; 2050 l10g_seren 1 "Status of 10 GbE serial PCS (KR PCS) for KR or SFI operation"; 2051 sgmii_en 1 "Status of SGMII operation"; 2052 mlink_mode 2 type (mac_lnkmode) "MAC link mode status"; 2053 lnk_speed 2 type (link_speed) "MAC link speed status"; 2054 lnk_up 1 "Link is up"; 2055 kxr_ancomp 1 "KX/KX4/KR backplane auto-negotiation has completed successfully"; 2056 }; 2057 2058 2059 constants mac_rxtxlm "MAC link mode in the Core Rx/Tx path" { 2060 rxlm_1g = 0b00 "1 GbE"; 2061 rxlm_10g_p = 0b01 "10 GbE parallel"; 2062 rxlm_10g_s = 0b10 "10GbE serial"; 2063 rxlm_aneg = 0b11 "auto-negotiation"; 2064 }; 2065 2066 // 8.2.3.22.21 2067 register links2 ro addr(base, 0x04324) "Link Status Register 2" { 2068 mac_rxlm 2 type(mac_rxtxlm) "MAC link mode in the Core Rx path"; 2069 _ 1 rsvd; 2070 mac_txlm 2 type(mac_rxtxlm) "MAC link mode in the Core Tx path"; 2071 _ 1 rsvd; 2072 lnkp_an 1 "Link partner is KX/KX4/KR backplane auto-negotiation capable"; 2073 _ 25 rsvd; 2074 }; 2075 2076 constants pmapd_10gbes "PMAPMD used for 10 GbE serial link operation" { 2077 pmapd_kr = 0b00 "KR"; 2078 pmapd_sfi = 0b10 "SFI"; 2079 }; 2080 2081 // 8.2.3.22.22 2082 register autoc2 rw addr(base, 0x042A8) "Auto Negotiation Control 2 Register" { 2083 _ 16 rsvd; 2084 pmad_10ser 2 type(pmapd_10gbes) "PMAPMD used for 10 GbE serial link operation"; 2085 ddpt 1 "Disable DME Pages Transmit"; 2086 _ 11 rsvd; 2087 pdd 1 "Disable the parallel detect part in the KX/KX4/KR bp aneg"; 2088 _ 1 rsvd; 2089 }; 2090 2091 // 8.2.3.22.23 2092 register anlp1 ro addr(base, 0x042B0) "Auto Negotiation Link Partner Link Control Word 1 Register" { 2093 lpan_sel 5 "LP AN adv Selector field"; 2094 lpan_echn 5 "LP AN adv Echoed Nonce field"; 2095 lpan_pause 2 "LP AN adv Pause"; 2096 _ 1 rsvd; 2097 lpan_rf 1 "LP AN adv RF"; 2098 lpan_ack 1 "LP AN adv Acknowledge"; 2099 lpan_np 1 "LP AN adv NP"; 2100 anas 4 "KX/KX4/KR Backplane Auto-Negotiation Arbitration State"; 2101 _ 12 rsvd; 2102 }; 2103 2104 // 8.2.3.22.24 2105 register anlp2 ro addr(base, 0x042B4) "Auto Negotiation Link Partner Link Control Word 2 Register" { 2106 lpan_nf 5 "LP AN adv page fields T[4:0]"; 2107 lpan_afl 11 "LP AN adv page fields A[10:0]"; 2108 lpan_afh 16 "LP AN adv page fields A[26:11]"; 2109 }; 2110 2111 // 8.2.3.22.25 2112 register mmngc ro addr(base, 0x042D0) "MAC Manageability Control Register" { 2113 mng_veto 1 "MNG_VETO"; 2114 _ 31 rsvd; 2115 }; 2116 2117 // 8.2.3.22.26 2118 register anlpnp1 ro addr(base, 0x042D4) "Auto Negotiation Link Partner Next Page 1 Register" { 2119 msg 11 "LP AN adv np Message/Unformatted Code"; 2120 toggle 1 "LP AN adv np Toggle"; 2121 ack2 1 "LP AN adv np Acknowledge2"; 2122 mp 1 "LP AN adv np MP"; 2123 ack 1 "LP AN adv np Acknowledge"; 2124 np 1 "LP AN adv np NP"; 2125 ufmtc 16 "LP AN adv np Unformatted Code"; 2126 }; 2127 2128 // 8.2.3.22.27 2129 register anlpnp2 ro addr(base, 0x042D8) "Auto Negotiation Link Partner Next Page 2 Register" { 2130 lpan_nph 16 "LP AN Next Page Fields D[47:32]. [15:0] = Unformatted Code"; 2131 _ 16 rsvd; 2132 }; 2133 2134 2135 constants fec_ncnt "Good Parity Block Count" { 2136 gbl_4 = 0b00 "4 good blocks"; 2137 gbl_2 = 0b01 "2 good blocks"; 2138 gbl_5 = 0b10 "5 good blocks"; 2139 gbl_7 = 0b11 "7 good blocks"; 2140 }; 2141 2142 constants fec_mcnt "Bad Parity Block Count" { 2143 err_8 = 0b00 "8 errors"; 2144 err_4 = 0b01 "4 errors"; 2145 err_12 = 0b10 "12 errors"; 2146 err_15 = 0b11 "15 errors"; 2147 }; 2148 2149 // 8.2.3.22.28 2150 register krpcsfc rw addr(base, 0x042E0) "KR PCS and FEC Control Register" { 2151 _ 11 mbz; 2152 _ 5 rsvd; 2153 fec_enerr 1 "FEC Enable Error Indication to KR-PCS"; 2154 _ 1 rsvd; 2155 fec_ncnt 2 type(fec_ncnt) "Good Parity Block Count"; 2156 fec_mcnt 2 type(fec_mcnt) "Bad Parity Block Count"; 2157 fec_lmode 1 "Enables FEC Loose Mode"; 2158 fec_rxswp 1 "FEC Rx Bit Order Swap"; 2159 fec_txswp 1 "FEC Tx Bit Order Swap"; 2160 _ 1 rsvd; 2161 slipass 1 "Loss of Sync (frame_align) Idle Pass-Through Select"; 2162 ssync 1 "Rx Block Lock Override"; 2163 _ 4 rsvd; 2164 }; 2165 2166 // 8.2.3.22.29 2167 register krpcss ro addr(base, 0x042E4) "KR PCS Status Register" { 2168 _ 3 rsvd; 2169 errcnt_blk 8 rc "Rx Decoder Error Counter"; 2170 berbad_cnt 6 rc "BER Bad Counter"; 2171 rxfifo_elh 1 rc "Elastic Buffer Error"; 2172 rxlf_det 1 rc "RX_LF Detect"; 2173 rxfrm_alerr 1 rc "Frame Align Error"; 2174 blklck 1 "Rx Block Lock Status bit"; 2175 hber_sts 1 rc "Rx High Bit Error Rate Status bit"; 2176 rxfl_det2 1 rc "RX_LF Detect"; 2177 lnk_sts 1 "Rx Link Status"; 2178 rx_ufl 1 rc "Rx Underflow Status"; 2179 rx_ofl 1 rc "Rx Overflow Status"; 2180 rx_fifoerr 1 "Rx Elastic Buffer Error"; 2181 rx_dataval 1 "Data Valid Status"; 2182 tx_ufl 1 rc "Tx Underflow Status"; 2183 tx_ofl 1 rc "Tx Overflow Status"; 2184 tx_fifoerr 1 "Unlatched FIFO Error Status"; 2185 tx_dataval 1 "Data Valid Status"; 2186 }; 2187 2188 // 8.2.3.22.30 2189 register fecs1 rc addr(base, 0x042E8) "FEC Status 1 Register" { 2190 fec_cr 32 "FEC Correctable Error Counter"; 2191 }; 2192 2193 // 8.2.3.22.31 2194 register fecs2 rc addr(base, 0x042EC) "FEC Status 2 Register" { 2195 fec_uncr 32 "FEC Uncorrectable Error Counter"; 2196 }; 2197 2198 // 8.2.3.22.32 2199 register corectl rw addr(base, 0x14F00) "Core Analog Configuration Register" { 2200 data 8 "Data to Core Analog Registers"; 2201 address 8 "Address to Core Analog Registers"; 2202 latch_addr 1 "Latch address"; 2203 _ 15 rsvd; 2204 }; 2205 2206 // 8.2.3.22.33 2207 register smadarctl rw addr(base, 0x14F10) "Core Common Configuration Register" { 2208 data 8 "Data to Core Analog Registers"; 2209 address 8 "Address to Core Analog Registers"; 2210 latch_addr 1 "Latch address"; 2211 _ 15 rsvd; 2212 }; 2213 2214 // 8.2.3.22.34 2215 register mflcn rw addr(base, 0x04294) "MAC Flow Control Register" { 2216 pmcf 1 "Pass MAC Control Frames"; 2217 dpf 1 "Discard Pause Frame"; 2218 rpfce 1 "Receive Priority Flow Control Enable"; 2219 rfce 1 "Receive Flow Control Enable"; 2220 _ 28 rsvd; 2221 }; 2222 2223 // 8.2.3.22.35 2224 register sgmiic rw addr(base, 0x04314) "SGMII Control Register" { 2225 srxrassmp 4 "Shift Rx Rate-Adapt Single Data Sampling"; 2226 srxrarsmp 4 "Shift Rx Rate-Adapt Replicated Data Sampling"; 2227 stxrasmp 4 "Shift Tx Rate-Adapt Sampling"; 2228 ansflu100 1 "AN SGMII Force Link Up 100 Mb/s"; 2229 ansbyp 1 "AN SGMII Bypass"; 2230 anstrig 1 "AN SGMII Trigger"; 2231 anslnktmr 1 "AN SGMII Link-Timer"; 2232 _ 1 rsvd; 2233 anignrrxrf 1 "Auto-Negotiation Ignore Received RF Field"; 2234 _ 14 rsvd; 2235 }; 2236 2237 2238 /************************************ 2239 * 8.2.3.23 Statistics 2240 ***********************************/ 2241 2242 // 8.2.3.23.1 2243 register crcerrs rc addr(base, 0x04000) "CRC Error Count" 2244 type(uint32); 2245 2246 // 8.2.3.23.2 2247 register illerrc rc addr(base, 0x04004) "Illegal Byte Error Count" 2248 type(uint32); 2249 2250 // 8.2.3.23.3 2251 register errbc rc addr(base, 0x04008) "Error Byte Count" 2252 type(uint32); 2253 2254 // 8.2.3.23.4 2255 regarray rxmpc rc addr(base, 0x03FA0) [8] "Rx Missed Packets Count" 2256 type(uint32); 2257 2258 // 8.2.3.23.5 2259 register mlfc rc addr(base, 0x04034) "MAC Local fault count" 2260 type(uint32); 2261 2262 // 8.2.3.23.6 2263 register mrfc rc addr(base, 0x04038) "MAC Remote fault count" 2264 type(uint32); 2265 2266 // 8.2.3.23.7 2267 register rlec rc addr(base, 0x04040) "Receive Length Error Count" 2268 type(uint32); 2269 2270 2271 // 8.2.3.23.23 2272 register prc1522 rc addr(base, 0x04070) "Packets Received [1024 to Max Bytes] Count" 2273 type(uint32); 2274 2275 // 8.2.23.26 2276 2277 // 8.2.3.23.8 2278 register ssvpc rc addr(base, 0x08780) "Switch Security Violation Packet Count" 2279 type(uint32); 2280 2281 // 8.2.3.23.26 2282 2283 register gprc ro addr(base, 0x04074) "Good packets recieved count" 2284 type(uint32); 2285 2286 // 8.2.3.23.27 2287 register gorcl rc addr(base, 0x04088) "Good Octets Received Count Low" 2288 type(uint32); 2289 2290 // 8.2.3.23.28 2291 register gorch rc addr(base, 0x0408c) "Good Octets Received Count High" 2292 type(uint32); 2293 2294 // 8.2.3.23.29 2295 register rxnfgpc rc addr(base, 0x041B0) "Good Rx Non-Filtered Packet Counter" 2296 type(uint32); 2297 2298 // 8.2.3.23.32 2299 register rxdgpc rc addr(base, 0x02F50) "DMA Good Rx Packet Counter" 2300 type(uint32); 2301 2302 // 8.2.3.23.44 2303 register gptc rc addr(base, 0x04080) "Good packets trasmitted count" 2304 type(uint32); 2305 2306 // 8.2.3.23.45 2307 register gotcl rc addr(base, 0x04090) "Good octets transmitted count low" 2308 type(uint32); 2309 2310 // 8.2.3.23.46 2311 register gotch rc addr(base, 0x04094) "Good octets transmitted count high" 2312 type(uint32); 2313 2314 // 8.2.3.23.47 2315 register txdgpc rc addr(base, 0x087A0) "DMA Good Tx Packet Counter" 2316 type(uint32); 2317 2318 // 8.2.3.23.50 2319 register ruc rc addr(base, 0x040A4) "Receive Undersize Count" 2320 type(uint32); 2321 2322 // 8.2.3.23.51 2323 register rfc rc addr(base, 0x040A8) "Receive Fragment Count" 2324 type(uint32); 2325 2326 // 8.2.3.23.52 2327 register roc rc addr(base, 0x040AC) "Receive Oversize Count" 2328 type(uint32); 2329 2330 // 8.2.3.23.53 2331 register rjc rc addr(base, 0x040B0) "Receive Jabber Count" 2332 type(uint32); 2333 2334 // 8.2.3.23.54 2335 register mngprc rc addr(base, 0x040B4) "Management Packets Received Count" 2336 type(uint32); 2337 2338 // 8.2.3.23.55 2339 register mngpdc rc addr(base, 0x040B8) "Management Packets Dropped Count" 2340 type(uint32); 2341 2342 // 8.2.3.23.57 2343 register torl rc addr(base, 0x040c0) "Total octets received low" 2344 type(uint32); 2345 2346 // 8.2.3.23.58 2347 register torh rc addr(base, 0x040c4) "Total octets received high" 2348 type(uint32); 2349 2350 // 8.2.3.23.59 2351 register tpr rc addr(base, 0x040D0) "Total Packets Recieved" 2352 type(uint32); 2353 2354 // 8.2.3.23.60 2355 register tpt rc addr(base, 0x040D4) "Total Packets Transmitted" 2356 type(uint32); 2357 2358 // 8.2.3.23.69 2359 register mspdc rc addr(base, 0x04010) "MAC Short Packet Discard Count" 2360 type(uint32); 2361 2362 // 8.2.3.23.71 2363 regarray rqsmr rw addr(base, 0x02300) [32; 0x4] "Receive Queue Statistics Mapping" { 2364 q_map0 4 "Map to queue 4*n+0"; 2365 _ 4; 2366 q_map1 4 "Map to queue 4*n+1"; 2367 _ 4; 2368 q_map2 4 "Map to queue 4*n+2"; 2369 _ 4; 2370 q_map3 4 "Map to queue 4*n+3"; 2371 _ 4; 2372 }; 2373 2374 // 8.2.3.23.73 2375 regarray tqsm rw addr(base, 0x08600) [32; 0x4] "Transmit Queue Statistics Mapping" { 2376 q_map0 4 "Map to queue 4*n+0"; 2377 _ 4; 2378 q_map1 4 "Map to queue 4*n+1"; 2379 _ 4; 2380 q_map2 4 "Map to queue 4*n+2"; 2381 _ 4; 2382 q_map3 4 "Map to queue 4*n+3"; 2383 _ 4; 2384 }; 2385 2386 // 8.2.3.23.74 2387 regarray qprc rc addr(base, 0x01030) [16; 0x40] "Queue Packets Received Count" 2388 type(uint32); 2389 2390 // 8.2.3.23.75 2391 regarray qprdc rc addr(base, 0x01430) [16; 0x40] "Queue Packets Received Drop Count" 2392 type(uint32); 2393 2394 2395 /************************************ 2396 * 8.2.3.24 Wake up control 2397 ***********************************/ 2398 2399 // 8.2.3.24.9 2400 regarray fhft_1 rw addr(base, 0x09000) [128] "Flexible Host Filter Table Registers 0-3" 2401 type(uint32); 2402 2403 regarray fhft_2 rw addr(base, 0x09800) [64] "Flexible Host Filter Table Registers 4-5" 2404 type(uint32); 2405 2406 2407 /************************************ 2408 * 8.2.3.25 Management filters 2409 ***********************************/ 2410 2411 // 8.2.3.25.1 2412 regarray mavtv rw addr(base, 0x05010) [8] "Management VLAN TAG Value" { 2413 vid 12 "VLAN ID that should be compared with incoming packet"; 2414 _ 20 rsvd; 2415 }; 2416 2417 // 8.2.3.25.2 2418 regarray mfutp rw addr(base, 0x05030) [8] "Management Flex UDP/TP Ports" { 2419 mfutp_1 16 "VLAN ID that should be compared with incoming packet"; 2420 mfutp_2 16 "VLAN ID that should be compared with incoming packet"; 2421 }; 2422 2423 // 8.2.3.25.3 2424 regarray metf rw addr(base, 0x05190) [4] "Management Ethernet Type Filter" { 2425 etype 16 "EtherType value to be compared with incoming packet"; 2426 _ 14 rsvd; 2427 polarity 1 "Negative filter"; 2428 _ 1 rsvd; 2429 }; 2430 2431 // 8.2.3.25.4 2432 register manc rw addr(base, 0x05820) "Management Control Register" { 2433 _ 17 rsvd; 2434 rcv_tco_en 1 "Receive TCO Packets Enabled"; 2435 _ 1 rsvd; 2436 rcv_all 1 "Receive All Enable"; 2437 mcst_pl2 1 "Receive All Multicast"; 2438 en_m2h 1 "Enable manageability packets to host memory"; 2439 bp_vlan 1 "VLAN filtering is bypassed for MNG packets"; 2440 en_xsum_flt 1 "When set, this bit enables Xsum filtering to manageability"; 2441 en_ipv4_flt 1 "Enable IPv4 address Filters"; 2442 fixed_net_t 1 "Fixed next type"; 2443 net_type 1 "Pass only VLAN tagged packets"; 2444 _ 5 rsvd; 2445 }; 2446 2447 // 8.2.3.25.5 2448 register mfval rw addr(base, 0x05824) "Manageability Filters Valid" { 2449 mac 4 "Indicates if the MAC unicast filters contain valid MAC addresses"; 2450 _ 4 rsvd; 2451 vlan 8 "VLAN filter registers contain valid VLAN tags"; 2452 ipv4 4 "IPv4 address filters contain valid addresses"; 2453 _ 4 rsvd; 2454 ipv6 4 "IPv6 address filters contain valid addresses"; 2455 _ 4 rsvd; 2456 }; 2457 2458 // 8.2.3.25.6 2459 register manc2h rw addr(base, 0x05860) "Management Control To Host Register" { 2460 host_en 8 "Host Enable"; 2461 _ 24 rsvd; 2462 }; 2463 2464 // 8.2.3.25.7 (TODO: Correct type) 2465 regarray mdef rw addr(base, 0x05890) [8] "Manageability Decision Filters" 2466 type(uint32); 2467 2468 // 8.2.3.25.7 (TODO: Correct type) 2469 regarray mdef_ext rw addr(base, 0x05160) [8] "Manageability Decision Filters" 2470 type(uint32); 2471 2472 /************************************ 2473 * 8.2.3.27 Virtualization 2474 ***********************************/ 2475 2476 // 8.2.3.27.1 2477 register pfvtctl rw addr(base, 0x051B0) "VT Control Register" { 2478 vt_en 1 "Virtualization Enabled Mode"; 2479 _ 6 rsvd; 2480 def_pl 6 "Default pool"; 2481 _ 16 rsvd; 2482 dis_def_pl 1 "Disable default pool"; 2483 rpl_en 1 "Replication enable"; 2484 _ 1 rsvd; 2485 }; 2486 2487 // 8.2.3.27.5 2488 regarray pfvflre ro addr(base, 0x00600) [2] "PF VFLR Events Indication" type(uint32); 2489 2490 // 8.2.3.27.6 2491 regarray pfvflrec rw1c addr(base, 0x00700) [2] "PF VFLR Events Clear" type(uint32); 2492 2493 // 8.2.3.27.7 2494 regarray pfvfre rw addr(base, 0x051e0) [2] "PF VF Receive Enable" type(uint32); 2495 2496 // 8.2.3.27.8 2497 regarray pfvfte rw addr(base, 0x08110) [2] "PF VF Transmit Enable" type(uint32); 2498 2499 // 8.2.3.27.9 2500 register pfqde rw addr(base, 0x02F04) "PF PF Queue Drop Enable Register" { 2501 qde 1 "Enable drop of packets from Rx Queue queue_idx"; 2502 _ 7 rsvd; 2503 queue_idx 7 "Queue index referenced"; 2504 _ 1 rsvd; 2505 we 1 "Write Enable"; 2506 re 1 "Read Enable"; 2507 _ 14 rsvd; 2508 }; 2509 2510 // 8.2.3.27.11 2511 regarray pfvfspoof rw addr(base, 0x08200) [8] "PF VF Anti Spoof Control" { 2512 macas 8 "MAC Address Anti-spoofing filter"; 2513 vlanas 8 "VLAN tag anti-spoofing filter"; 2514 _ 16; 2515 }; 2516 2517 // 8.2.3.27.12 2518 register pfdtxgswc rw addr(base, 0x08220) "PFDMA Tx General Switch Control" { 2519 lbe 1 "Enables VMDQ loopback"; 2520 _ 31; 2521 }; 2522 2523 // 8.2.3.27.14 2524 regarray pfvml2flt rw addr(base, 0x0f000) [64] "PF VM L2 Control" { 2525 _ 24; 2526 aupe 1 "Accept Untagged Packets Enable"; 2527 rompe 1 "Receive Overflow Multicast Packets"; 2528 rope 1 "Receive MAC Filters Overflow"; 2529 bam 1 "Broadcast accept"; 2530 mpe 1 "Multicast Promiscuous"; 2531 _ 3; 2532 }; 2533 2534 // 8.2.3.27.15 2535 regarray pfvlvf rw addr(base, 0x0F100) [64] "PF VM VLAN Pool Filter" { 2536 vlan_id 12 "VLAN tag for pool VLAN filter n"; 2537 _ 19 rsvd; 2538 vi_en 1 "VLAN Id Enable"; 2539 }; 2540 2541 // 8.2.3.27.16 2542 regarray pfvlvfb rw addr(base, 0x0F200) [128] "PF VM VLAN Pool Filter Bitmap" { 2543 pool_ena 32 "Pool Enable Bit Array"; 2544 }; 2545 2546 // 8.2.3.27.17 2547 regarray pfuta rw addr(base, 0x0F400) [128] "PF Unicast Table Array" { 2548 bitvec 32 "Bit Vector"; 2549 }; 2550 2551 2552/* 2553 register addr(base, 0x00000) "" { 2554 }; 2555 2556*/ 2557}; 2558