1/* 2 * Copyright (c) 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * e1000.dev 11 * 12 * DESCRIPTION: Intel e1000 family Gigabit Ethernet NICs 13 * 14 * Numbers in comments refer to the Intel PCIe GbE Controllers Open 15 * Source Software Development Manual, 631xESB / 632xESB, 82563EB / 16 * 82564EB, 82571EB / 82572EI & 82573E / 82573V / 82573L. 17 * 316080-003, Revison 1.2, September 2007 18 */ 19 20device e1000 lsbfirst ( addr base ) "Intel e1000 Gigabit Ethernet" { 21 22 /************************************ 23 * General registers 24 ***********************************/ 25 26 // 13.3.1 27 constants linkspeed "Link speed" { 28 mb10 = 0b00 "10Mb/s"; 29 mb100 = 0b01 "100Mb/s"; 30 mb1000 = 0b10 "1Gb/s"; 31 mb_notused = 0b11 "1Gb/s"; 32 }; 33 34 register ctrl rw addr(base, 0x0000) "Device control" { 35 fd 1 "full-duplex"; 36 _ 1 mbz; 37 gio_md 1 "GIO master disable"; 38 lrst 1 "Link reset"; 39 _ 1 mbz; 40 asde 1 "Auto-Speed Detection Enable"; 41 slu 1 "Set link up"; 42 ilos 1 "Invert Loss-of-Signal (LOS)"; 43 speed 2 type(linkspeed) "Speed selection"; 44 _ 1 mbz; 45 frcspd 1 "Force speed"; 46 frcdplx 1 "Force duplex"; 47 _ 5 mbz; 48 sdp0_data 1 "SDP0 data value, or dock/undock status"; 49 sdp1_data 1 "SDP1 data value"; 50 advd3wuc 1 "D3cold wakeup capability"; 51 en_phy_pwr_mgmt 1 "PHY Power-Management Enable"; 52 sdp0_iodir 1 "SDP0 pin I/O directionality"; 53 sdp1_iodir 1 "SDP1 pin I/O directionality"; 54 _ 2 mbz; 55 rst 1 "Device reset"; 56 rfce 1 "Receive flow control enable"; 57 tfce 1 "Transmit flow control enable"; 58 _ 1 mbz; 59 vme 1 "VLAN mode enable"; 60 phy_rst 1 "PHY reset"; 61 }; 62 63 // 82546 rev 3 64 register ctrldup rw addr(base, 0x0004) "Device Control Duplicate (Shadow)" { 65 fd 1 "full-duplex"; 66 _ 1 mbz; 67 gio_md 1 "GIO master disable"; 68 lrst 1 "Link reset"; 69 _ 1 mbz; 70 asde 1 "Auto-Speed Detection Enable"; 71 slu 1 "Set link up"; 72 ilos 1 "Invert Loss-of-Signal (LOS)"; 73 speed 2 type(linkspeed) "Speed selection"; 74 _ 1 mbz; 75 frcspd 1 "Force speed"; 76 frcdplx 1 "Force duplex"; 77 _ 5 mbz; 78 sdp0_data 1 "SDP0 data value, or dock/undock status"; 79 sdp1_data 1 "SDP1 data value"; 80 advd3wuc 1 "D3cold wakeup capability"; 81 en_phy_pwr_mgmt 1 "PHY Power-Management Enable"; 82 sdp0_iodir 1 "SDP0 pin I/O directionality"; 83 sdp1_iodir 1 "SDP1 pin I/O directionality"; 84 _ 2 mbz; 85 rst 1 "Device reset"; 86 rfce 1 "Receive flow control enable"; 87 tfce 1 "Transmit flow control enable"; 88 _ 1 mbz; 89 vme 1 "VLAN mode enable"; 90 phy_rst 1 "PHY reset"; 91 }; 92 93 constants lanid "LAN ID" { 94 lan_a = 0b00 "LAN A"; 95 lan_b = 0b01 "LAN B"; 96 lan_not_u1 = 0b10 "LAN ID not used"; 97 lan_not_u2 = 0b11 "LAN ID not used"; 98 }; 99 constants mac_mask "LAN MAC MASK" { 100 lan_b_mask = 0x0100 "LAN B mask"; 101 }; 102 103 // 13.3.2 104 register status ro addr(base, 0x0008) "Device status" { 105 fd 1 "Link full duplex configuration"; 106 lu 1 "Link up"; 107 func_id 2 "Function ID"; 108 txoff 1 "Transmission paused"; 109 tbimode 1 "TBI mode"; 110 speed 2 type(linkspeed) "Link speed setting"; 111 asdv 2 type(linkspeed) "Auto speed detection value"; 112 phyra 1 "PHY reset asserted"; 113 pci66 1 "PCI Bus speed indication"; 114 bus64 1 "PCI Bus Width indication"; 115 pcix_mode 1 "PCI-X Mode indication"; 116 pcixspd 2 "PCI-X Bus Speed Indication"; 117 _ 3 mbz; 118 gio_mes 1 "GIO master enable status"; 119 dev_rst_set 1 "Device reset set"; 120 pf_rst_done 1 "Software Rest or device reset completed"; 121 _ 10 mbz; 122 }; 123 124 register status_I350 rw also addr(base, 0x0008) "Device status" { 125 fd 1 "Link full duplex configuration"; 126 lu 1 "Link up"; 127 lan_id 2 "Function ID"; 128 txoff 1 "Transmission paused"; 129 _ 1 mbz; 130 speed 2 type(linkspeed) "Link speed setting"; 131 asdv 2 type(linkspeed) "Auto speed detection value"; 132 phyra 1 "PHY reset asserted"; 133 _ 3 mbz; 134 nvf 4 "Num VFs in the IOV capability s"; 135 vfe 1 "VF enable (VFE) bit in the IOV capability"; 136 gio_mes 1 "GIO master enable status"; 137 dev_rst_set 1 "Device reset set"; 138 pf_rst_done 1 "Software Rest or device reset completed"; 139 _ 9 mbz; 140 mac_gate 1 "MAC clock gating Enable"; 141 }; 142 143 // 13.3.3 144 constants flashenable "Flash write enable control" { 145 flash_erase = 0b00 "Flash erase"; 146 flash_wr_disable = 0b01 "Flash writes discarded"; 147 flash_wr_enable = 0b10 "Flash writed enabled"; 148 }; 149 150 constants eeaddrsize "EEPROM address size" { 151 bits8or9 = 0 "8- and 9-bit"; 152 bits16 = 1 "16-bit"; 153 }; 154 155 constants nvmtype "Non-volatile memory type" { 156 eeprom = 0b00 "EEPROM"; 157 saflash = 0b01 "Stand-alone Flash"; 158 spiflash = 0b10 "Shared SPI Flash"; 159 sio = 0b11 "SIO"; 160 }; 161 162 register eecd rw addr(base, 0x0010) "EEPROM/Flash control" { 163 ee_sk 1 "Clock input to EEPROM"; 164 ee_cs 1 "Chip select to EEPROM"; 165 ee_di 1 "Data input to EEPROM"; 166 ee_do 1 "Data output bit from EEPROM"; 167 fwe 2 type(flashenable) "Flash write enable control"; 168 ee_req 1 "Request EEPROM access"; 169 ee_gnt 1 "Grant EEPROM access"; 170 ee_pres 1 "EEPROM present"; 171 ee_size_n 1 "EEPROM size for NM93C46 compatible EEPROM" ; 172 ee_size_m 1 "EEPROM size for Microwire EEPROMs"; 173 _ 2 mbz; 174 ee_type 1 "EEPROM Type. (82541xx and 82547GI/EI)"; 175 _ 18 mbz; 176 }; 177 178 register eec rw also addr(base, 0x0010) "EEPROM/Flash control for I350" { 179 ee_sk 1 "Clock input to EEPROM"; 180 ee_cs 1 "Chip select to EEPROM"; 181 ee_di 1 "Data input to EEPROM"; 182 ee_do 1 "Data output bit from EEPROM"; 183 fwe 2 type(flashenable) "Flash write enable control"; 184 ee_req 1 "Request EEPROM access"; 185 ee_gnt 1 "Grant EEPROM access"; 186 ee_pres 1 "EEPROM present"; 187 auto_rd 1 "EEPROM Auto Read Done"; 188 ee_addr_size 1 "EEPROM Address Size"; 189 ee_size 4 "EEPROM Size"; 190 ee_blocked 1 "EEPROM access Aborted"; 191 ee_abort 1 "EEPROM access Aborted"; 192 ee_rd_timeout 1 "EERD access timeout"; 193 ee_clr_err 1 "Clear EEPROM Access Error"; 194 ee_det 1 "EEPROM Detected"; 195 _ 12 mbz; 196 }; 197 198 register eec_82574 rw also addr(base, 0x0010) "EEPROM/Flash control for 82574" { 199 ee_sk 1 "Clock input to EEPROM"; 200 ee_cs 1 "Chip select to EEPROM"; 201 ee_di 1 "Data input to EEPROM"; 202 ee_do 1 "Data output bit from EEPROM"; 203 fwe 2 type(flashenable) "Flash write enable control"; 204 ee_req 1 "Request EEPROM access"; 205 ee_gnt 1 "Grant EEPROM access"; 206 ee_pres 1 "EEPROM present"; 207 auto_rd 1 "EEPROM Auto Read Done"; 208 _ 1 mbz; 209 nv_size 4 "NVM Size"; 210 nv_adds 2 "NVM Address size"; 211 _ 3 mbz; 212 audpen 1 "Autonomous flash update"; 213 _ 1 mbz; 214 sec1val 1 "Sec 1 valid"; 215 nvmtype 1 "NVM Type"; 216 _ 8 mbz; 217 }; 218 219 // 13.3.4 220 // NM93C46 compatible EEPROMs 221 register eerd_nm rw addr(base, 0x0014) "EEPROM read" { 222 start 1 "Start read"; 223 _ 3 mbz; 224 done 1 ro "Read done"; 225 _ 3 mbz; 226 addr 8 "Read address"; 227 data 16 "Read data"; 228 }; 229 230 register eerd_ms rw also addr(base, 0x0014) "EEPROM read 82541xx and 82547GI/EI" { 231 start 1 "Start read"; 232 done 1 ro "Read done"; 233 addr 14 "Read address"; 234 data 16 "Read data"; 235 }; 236 237 238 // 13.3.5 239 constants linkmode "Link mode" { 240 glci = 0b00 "Direct coper or GLCI"; 241 l82573 = 0b10 "Must be set for 82573E/V/L"; 242 serdes = 0b11 "Internal SerDes (TBI) or SerDes mode"; 243 }; 244 register ctrlext rw addr(base, 0x0018) "Extended device control" { 245 _ 2 mbz; 246 sdp2_gpien 1 "General-purpose interrupt detection for SDP2"; 247 sdp3_gpien 1 "General-purpose interrupt detection for SDP3"; 248 _ 2; 249 sdp2_data 1 "SDP2 data value"; 250 sdp3_data 1 "SDP3 data value"; 251 _ 2 mbz; 252 sdp2_iodir 1 "SDP2 pin directionality"; 253 sdp3_iodir 1 "SDP3 pin directionality"; 254 asdchk 1 "Auto-speed-detection check"; 255 ee_rst 1 "EEPROM reset"; 256 _ 1 mbz; 257 spd_byps 1 "Speed select bypass"; 258 _ 1; 259 rodis 1 "Relaxed ordering disabled"; 260 serdeslpe 1 "SERDES low power enable"; 261 dmadge 1 "DMA dynamic gating enable"; 262 phypde 1 "PHY power down enable"; 263 _ 1; 264 link_mode 2 type(linkmode) "Link mode"; 265 pb_paren 1 "Packet buffer parity error detection enable"; 266 df_paren 1 "Descriptor FIFO parity error detection enable"; 267 _ 1 mbz; 268 iame 1 "Interrupt acknowledge auto-mask enable"; 269 drv_load 1 "Driver loaded"; 270 int_tca 1 "Timers clear enable"; 271 host_paren 1 "Host data FIFO parity enable"; 272 _ 1; 273 }; 274 275 // 13.3.6 276 register fla rw addr(base, 0x001c) "Flash access" { 277 fl_sk 1 "Clock input to Flash"; 278 fl_ce 1 "Chip select to Flash"; 279 fl_si 1 "Data input to Flash"; 280 fl_so 1 "Data output bit from Flash"; 281 fl_req 1 "Request Flash access"; 282 fl_gnt 1 "Grant Flash access"; 283 fl_addr_sz 1 "Flash address size"; 284 _ 2; 285 sw_wr_done 1 "Last write done"; 286 rd_status 1 "Flash status"; 287 _ 5; 288 ide_bo 14 "Base address of IDE Boot expansion ROM"; 289 fl_busy 1 "Flash busy"; 290 fl_er 1 "Flash erase command"; 291 }; 292 293 // 13.3.7 294 constants phyop "PHY register opcode" { 295 mdi_write_ = 0b01 "MDI Write"; 296 mdi_read_ = 0b10 "MDI Read"; 297 }; 298 register mdic rw addr(base, 0x0020) "MDI control" { 299 data 16 "Data"; 300 regadd 5 "PHY register address"; 301 phyadd 5 "PHY address"; 302 op 2 type(phyop) "Opcode"; 303 r 1 "Ready bit"; 304 i 1 "Interrupt enable"; 305 e 1 "Error"; 306 _ 1 mbz; 307 }; 308 309 // 13.3.8 310 // There are a lot of PHY registers, all accessed through the MDIC. 311 // We don't yet list them here. 312 313 // 13.3.10 314 register serdesctl rw addr(base, 0x0024) "SERDES ANA" { 315 data 8 "Data to SerDes"; 316 addr 8 "Address to SerDes"; 317 _ 15; 318 done 1 "Done"; 319 }; 320 321 // 13.3.11-12 322 constants fca "Flow control address" { 323 fca_lo = 0x0c28001; 324 fca_hi = 0x0000100; 325 }; 326 register fcal rw addr(base, 0x0028) "Flow control address low" type(uint32); 327 register fcah rw addr(base, 0x002C) "Flow control address low" type(uint32); 328 329 // 13.3.13 330 constants fctval "Flow control type" { 331 fct_val = 0x0008808; 332 }; 333 register fct rw addr(base, 0x0030) "Flow control type" type(uint32); 334 335 // 13.3.14 336 register kumctrlsta rw addr(base, 0x0034) "GLCI control and status" { 337 data 16 "Data"; 338 offset 5 "Offset of internal register"; 339 ren 1 "Read enable (1=read)"; 340 _ 10; 341 }; 342 343 // 13.3.15 344 constants vet_val "VLAN ether type value" { 345 vlan_type = 0x0008100; 346 }; 347 register vet rw addr(base, 0x0038) "VLAN Ether type" type(uint32); 348 349 // 13.3.16 350 register mdphya rw addr(base, 0x003c) "MDC/MDIO PHY address" { 351 phya 5 "PHY address"; 352 _ 27; 353 }; 354 355 // 13.3.17 356 register ufuse3 ro also addr(base, 0x00f0) "ULT Fuse register 3" { 357 drred 15 "Data RAM redundancy fuses"; 358 crred 13 "Code RAM redundancy fuses"; 359 enad 1 "Enable Data RAM redundancy fuses"; 360 enac 1 "Enable Code RAM redundancy fuses"; 361 _ 2; 362 }; 363 364 // 13.3.18 365 register fcttv rw addr(base, 0x0170) "Flow control transmit timer value" { 366 ttv 16 "Transmit timer value"; 367 _ 16 mbz; 368 }; 369 370 // 13.3.19 371 register txcw rw addr(base, 0x0178) "Transmit config word" { 372 _ 5 mbz; 373 txcw_fd 1 "TXCW full-duplex"; 374 txcw_hd 1 "TXCW half-duplex"; 375 txcw_pause 2 "TXCW pause"; 376 _ 3 mbz; 377 txcw_rfi 2 "TXCW remote fault indication"; 378 _ 1 mbz; 379 txcw_npr 1 "TXCW next page request"; 380 _ 14 mbz; 381 txconfig 1 "Transmit config control bit"; 382 ane 1 "Auto-negotiation enable"; 383 }; 384 385 // 13.3.20 386 register rxcw ro addr(base, 0x0180) "Receive config word" { 387 _ 5 mbz; 388 rxcw_fd 1 "RXCW full-duplex"; 389 rxcw_hd 1 "RXCW half-duplex"; 390 rxcw_pause 2 "RXCW pause"; 391 _ 3 mbz; 392 rxcw_rfi 2 "RXCW remote fault indication"; 393 _ 1 mbz; 394 rxcw_npr 1 "RXCW next page request"; 395 _ 10 mbz; 396 nc 1 "Carrier sense indicator"; 397 inv 1 "Invalid symbol during config process"; 398 chg 1 "Change to RXCW indication"; 399 rxconfig 1 "Reception indication"; 400 sync 1 "Lost bit sync indication"; 401 anc 1 "Auto-negotiation complete"; 402 }; 403 404 // 13.3.21 405 constants ledmode "LED output mode" { 406 link_10_100 = 0b0000 "Either 10 or 100 Mbs link established"; 407 link_100_1000 = 0b0001 "Either 100 or 1000 Mbs link established"; 408 link_up = 0b0010 "Any speed link established"; 409 filter_activity = 0b0011 "Packets passing MAC filtering"; 410 link_activity = 0b0100 "No transmit or receive activity"; 411 link_10 = 0b0101 "10 Mbs link established"; 412 link_100 = 0b0110 "100 Mbs link established"; 413 link_1000 = 0b0111 "1000 Mbs link established"; 414 full_duplex = 0b1001 "Link configured for full-duplex"; 415 collision = 0b1010 "Collision is observed"; 416 activity = 0b1011 "Link established and packets sent or revd"; 417 bus_size = 0b1100 "Controller detects 1 PCIe lane conn."; 418 paused = 0b1101 "Transmitter is flow controlled"; 419 led_on = 0b1110 "Always on"; 420 led_off = 0b1111 "Always off"; 421 }; 422 constants blmode "LED blink mode" { 423 ms200 = 0 "200ms on, 200ms off"; 424 ms83 = 1 "83ms on, 83 ms off"; 425 }; 426 register ledctl rw addr(base, 0x0e00) "LED control" { 427 led0_mode 4 type(ledmode) "LED0/LINK# mode"; 428 _ 1 mbz; 429 global_blink_mode 1 type(blmode) "Global blink mode"; 430 led0_ivrt 1 "LED0 invert"; 431 led0_blink 1 "LED0 blink"; 432 433 led1_mode 4 type(ledmode) "LED1/LINK# mode"; 434 _ 1 mbz; 435 led1_blink_mode 1 type(blmode) "Global blink mode"; 436 led1_ivrt 1 "LED1 invert"; 437 led1_blink 1 "LED1 blink"; 438 439 led2_mode 4 type(ledmode) "LED2/LINK# mode"; 440 _ 1 mbz; 441 led2_blink_mode 1 type(blmode) "Global blink mode"; 442 led2_ivrt 1 "LED2 invert"; 443 led2_blink 1 "LED2 blink"; 444 445 led3_mode 4 type(ledmode) "LED3/LINK# mode"; 446 _ 1 mbz; 447 led3_blink_mode 1 type(blmode) "Global blink mode"; 448 led3_ivrt 1 "LED3 invert"; 449 led3_blink 1 "LED3 blink"; 450 }; 451 452 // 13.3.22 453 register extcnf_ctrl rw addr(base, 0x0f00) "Extended config control" { 454 _ 1 mbz; 455 phy_we 1 "PHY write enable"; 456 dud_en 1 "Extended dock/undock configuration enable"; 457 _ 1; 458 dock_own 1 "Dock config owner"; 459 mdio_swown 1 "MDIO software ownership"; 460 mdio_hwown 1 "MDIO hoftware ownership"; 461 _ 9; 462 ecp 12 "Extended configuration pointer"; 463 _ 4; 464 }; 465 466 // 13.3.23 467 register extcnf_size rw addr(base, 0x0f08) "Extended config size" { 468 phy_len 8 "Extended PHY configuration area length"; 469 dock_len 8 "Extended dock configuration area length"; 470 _ 8 mbz; 471 _ 8; 472 }; 473 474 // 13.3.24 475 register pba rw addr(base, 0x1000) "Packet buffer allocation" { 476 rxa 16 "Rx packet buffer allocation in KB"; 477 txa 16 "Tx packet buffer allocation in KB"; 478 }; 479 480 // 13.3.25 481 register eemngctl rw addr(base, 0x1010) "MNG EEPROM control" { 482 _ 18; 483 crg_done 1 "MNG configuration cycle done"; 484 _ 13; 485 }; 486 487 // 13.3.26 488 register sw_fw_sync rw addr(base, 0x5b5c) "Software/firmware sync" { 489 sw_eep_sm 1 "EEPROM access owned by software"; 490 sw_phy_sm0 1 "PHY 0 access owned by software"; 491 sw_phy_sm1 1 "PHY 1 access owned by software"; 492 sw_mac_csr_sm 1 "Shared CSR access owned by software"; 493 _ 12; 494 fw_eep_sm 1 "EEPROM access owned by firmware"; 495 fw_phy_sm0 1 "PHY 0 access owned by firmware"; 496 fw_phy_sm1 1 "PHY 1 access owned by firmware"; 497 fw_mac_csr_sm 1 "Shared CSR access owned by firmware"; 498 _ 12; 499 }; 500 501 /************************************ 502 * Interrupt registers 503 ***********************************/ 504 505 // 13.3.27 506 regtype intreg "Interrupt register format" { 507 txdw 1 "Transmit descriptor written back"; 508 txqe 1 "Transmit queue empty"; 509 lsc 1 "Link status change"; 510 rxseq 1 "Receive sequence error"; 511 rxdmt0 1 "Receive descriptor minimum threshold reached"; 512 _ 1; 513 rxo 1 "Receiver overrun"; 514 rxt0 1 "Receiver timer interrupt"; 515 _ 1; 516 mdac 1 "MDI/O access complete"; 517 rxcfg 1 "Received configuration symbols"; 518 _ 2; 519 gpi_sdp2 1 "General-purpose interrupt on SPD2"; 520 gpi_sdp3 1 "General-purpose interrupt on SPD3"; 521 txd_low 1 "Transmit descriptor low threshold"; 522 srpd 1 "Small receive packet detected"; 523 ack 1 "Receive ack frame detected"; 524 _ 2; 525 rx_desc_fifo_par0 1 "Rx descriptor FIFO parity error 0"; 526 tx_desc_fifo_par0 1 "Tx descriptor FIFO parity error 0"; 527 pcie_master_par 1 "PCIe master data FIFO parity error"; 528 pbpar 1 "Packet buffer parity error"; 529 rx_desc_fifo_par1 1 "Rx descriptor FIFO parity error 1"; 530 tx_desc_fifo_par1 1 "Tx descriptor FIFO parity error 1"; 531 _ 5; 532 int_asserted 1 "Interrupt asserted"; 533 }; 534 535 regtype eintreg "Extended Interrupt register format" { 536 rxtxq0 1 "Receive/Transmit Queue 0 Interrupt"; 537 rxtxq1 1 "Receive/Transmit Queue 1 Interrupt"; 538 rxtxq2 1 "Receive/Transmit Queue 2 Interrupt"; 539 rxtxq3 1 "Receive/Transmit Queue 3 Interrupt"; 540 rxtxq4 1 "Receive/Transmit Queue 4 Interrupt"; 541 rxtxq5 1 "Receive/Transmit Queue 5 Interrupt"; 542 rxtxq6 1 "Receive/Transmit Queue 6 Interrupt"; 543 rxtxq7 1 "Receive/Transmit Queue 7 Interrupt"; 544 _ 22 mbz; 545 tcp_timer 1 "TCP Timer expired"; 546 other_cause 1 "Other cause"; 547 }; 548 549 regtype msixintreg "MSI-X Interrupt register format "{ 550 msix 25 "MSI-X vectors"; 551 _ 7 mbz; 552 }; 553 554 // 13.3.27 555 register icr ro addr(base, 0x00c0) "Interrupt cause read" type(intreg); 556 557 // 13.3.28 558 register itr rw addr(base, 0x00c4) "Interrupt throttling rate" { 559 interval 16 "Minimum inter-interrupt interval (x256ns)"; 560 _ 16 mbz; 561 }; 562 563 // 13.3.29 564 register ics wo addr(base, 0x00c8) "Interrupt cause write" type(intreg); 565 566 // 13.3.30 567 register ims rw addr(base, 0x00d0) "Interrupt mask set/read" type(intreg); 568 569 // 13.3.31 570 register imc wo addr(base, 0x00d8) "Interrupt mask clear" type(intreg); 571 572 // 13.3.32 573 register iam rw addr(base, 0x00e0) "Interrupt ack auto mask" type(intreg); 574 575 576 // 82574: 10.2.4.9 577 register ivar_82574 rw addr(base, 0x00e4) "Interrupt Vector Allocation" { 578 int_alloc0 3 "MSI-X vector RxQ0"; 579 int_alloc_val0 1 "Enable RxQ0"; 580 int_alloc1 3 "MSI-X vector RxQ1"; 581 int_alloc_val1 1 "Enable RxQ1"; 582 int_alloc2 3 "MSI-X vector TxQ0"; 583 int_alloc_val2 1 "Enable TxQ0"; 584 int_alloc3 3 "MSI-X vector TxQ1"; 585 int_alloc_val3 1 "Enable TxQ1"; 586 int_alloc4 3 "MSI-X vector Other"; 587 int_alloc_val4 1 "Enable Other"; 588 _ 11 mbz; 589 int_on_all_wb 1 "Int on every writeback"; 590 591 }; 592 // 82574: 10.2.4.3 593 regarray eitr_82574 addr(base, 0x00e8)[4;0x4] "Extended Interrupt Throttle" { 594 interval 16 "Minimum inter-interrupt interval (x256ns)"; 595 _ 16 mbz; 596 }; 597 598 regarray eitr addr(base, 0x1680)[9;0x4] "Extended Interrupt Throttle" { 599 _ 2 mbz; 600 interval 13 "Interval"; 601 _ 1 mbz; 602 counter 16 "Down counter"; 603 }; 604 605 register gpie rw addr(base, 0x1514) "General Purpose Interrupt Enable" { 606 nsicr 1 "Non Selective Interrupt clear on read"; 607 _ 3 mbz; 608 multiple_msix 1 "Multiple MSIX"; 609 _ 2 mbz; 610 ll_interval 5 "Low Latency Credits Increment Rate"; 611 _ 18 mbz; 612 EIAME 1 "EIAME"; 613 pba_support 1 "PBA support"; 614 }; 615 616 register eics wo addr(base, 0x1520) "Extended Interrupt Cause Set" type(eintreg); 617 register eims rw addr(base, 0x1524) "Extended Interrupt Mask Set/Read" type(eintreg); 618 register eimc wo addr(base, 0x1528) "Extended Interrupt Mask Clear" type(eintreg); 619 register eiac rw addr(base, 0x152c) "Extended Interrupt Auto Clear" type(eintreg); 620 register eiam rw addr(base, 0x1530) "Extended Interrupt Auto Mask Enable" type(eintreg); 621 register eicr rw addr(base, 0x1580) "Extended Interrupt Cause" type(eintreg); 622 623 register eimc_msix wo also addr(base, 0x1528) "Extended Interrupt Mask Clear" type(msixintreg); 624 625 regarray eitr_I350 also addr(base, 0x1680)[24;0x4] "Extended Interrupt Throttle" { 626 _ 2 mbz; 627 interval 13 "Interval"; 628 lli_en 1 "LLI moderation enable."; 629 ll_counter 5 "Reflects the current credits for that EITR for LL interrupts"; 630 mod_count 10 "Down counter, exposes only the 10 most significant"; 631 cnt_ingr 1 "When set the hardware does not override the counters fields"; 632 }; 633 634 regarray ivar rw addr(base, 0x1700)[4;0x4] "Interrupt Vector Allocation" { 635 int_alloc0 5 "MSI-X vector"; 636 _ 2 mbz; 637 int_alloc_val0 1 "Valid bit"; 638 int_alloc1 5 "MSI-X vector"; 639 _ 2 mbz; 640 int_alloc_val1 1 "Valid bit"; 641 int_alloc2 5 "MSI-X vector"; 642 _ 2 mbz; 643 int_alloc_val2 1 "Valid bit"; 644 int_alloc3 5 "MSI-X vector"; 645 _ 2 mbz; 646 int_alloc_val3 1 "Valid bit"; 647 }; 648 649 register ivar_misc rw addr(base, 0x1740) "Interrupt Vector Allocation - MISC" { 650 int_alloc16 5 "TCP Timer"; 651 _ 2 mbz; 652 int_alloc_val16 1 "Valid bit"; 653 int_alloc17 5 "Other cause"; 654 _ 2 mbz; 655 int_alloc_val17 1 "Valid bit"; 656 _ 16 mbz; 657 }; 658 659 660 /************************************ 661 * Receive registers 662 ***********************************/ 663 664 // 13.3.33 665 constants lbmode "Loopback mode" { 666 lb_normal = 0b00 "Normal operation"; 667 lb_mac = 0b01 "MAC loopback"; 668 }; 669 constants rxthresh "Received desc. threshold size" { 670 rdlen_2 = 0b00 "1/2 RDLEN"; 671 rdlen_4 = 0b01 "1/4 RDLEN"; 672 rdlen_8 = 0b10 "1/8 RDLEN"; 673 }; 674 constants dtype "Descriptor type" { 675 dt_legacy = 0b00 "Legacy descriptor type"; 676 dt_split = 0b01 "Packet split descriptor type"; 677 }; 678 constants rxbsize "Receive buffer size" { 679 rxb2048 = 0b00 "2048 bytes"; 680 rxb1024 = 0b01 "1024 or 16384 bytes"; 681 rxb512 = 0b10 "512 or 8192 bytes"; 682 rxb256 = 0b11 "256 or 4096 bytes"; 683 }; 684 register rctl rw addr(base, 0x0100) "Receive control" { 685 _ 1 mbz; 686 en 1 "Receiver enable"; 687 sbp 1 "Store bad packets"; 688 upe 1 "Unicast promiscuous enabled"; 689 mpe 1 "Multicast promiscuous enabled"; 690 lpe 1 "Long packet reception enable"; 691 lbm 2 type(lbmode) "Loopback mode"; 692 rdmts 2 type(rxthresh) "Receive descriptor minimum threshold size"; 693 dtyp 2 type(dtype) "Descriptor type"; 694 mo 2 "Multicast offset (12 bits starting at 36-val)"; 695 _ 1 mbz; 696 bam 1 "Broadcast accept mode"; 697 bsize 2 type(rxbsize) "Receive buffer size (see BSEX)"; 698 vfe 1 "VLAN filter enable"; 699 cfien 1 "Canonical form indicator enable"; 700 cfi 1 "Canonical form indicator value"; 701 _ 1 mbz; 702 dpf 1 "Discard pause frames"; 703 pmcf 1 "Pass MAC control frames"; 704 _ 1 mbz; 705 bsex 1 "Buffer size extension"; 706 secrc 1 "Strip Ethernet CRC from packet"; 707 flxbuf 4 "Flexible buffer size (in KB)"; 708 _ 1 mbz; 709 }; 710 711 // 13.3.34 712 register ert rw addr(base, 0x2008) "Early receive threshold" { 713 rxthresh 13 "Receive threshold value (x 8 bytes)"; 714 _ 1; 715 _ 18 mbz; 716 }; 717 718 // 13.3.35 719 register fcrtl rw addr(base, 0x2160) "Flow control rx threshold low" { 720 _ 3 mbz; 721 rtl 13 "Recieve threshold low"; 722 _ 15 mbz; 723 xone 1 "XON enable"; 724 }; 725 726 // 13.3.36 727 register fcrth rw addr(base, 0x2168) "Flow control rx threshold high" { 728 _ 3 mbz; 729 rth 13 "Recieve threshold high"; 730 _ 15 mbz; 731 flowcntdis 1 "Flow control disable"; 732 }; 733 734 // 13.3.37 735 register psrctl rw addr(base, 0x2170) "Packet split rx control" { 736 bsize0 7 "Receive buffer 0 size (x 128 bytes)"; 737 _ 1 mbz; 738 bsize1 7 "Receive buffer 1 size (x 1 kbytes)"; 739 _ 1 mbz; 740 bsize2 7 "Receive buffer 2 size (x 1 kbytes)"; 741 _ 1 mbz; 742 bsize3 7 "Receive buffer 3 size (x 1 kbytes)"; 743 _ 1 mbz; 744 }; 745 746 // 13.3.38/46/39/47 747 regarray rdbal rw addr(base, 0x2800)[2;0x100] 748 "Rx descr. base addr low" type(uint32); 749 regarray rdbah rw addr(base, 0x2804)[2;0x100] 750 "Rx descr. base addr high" type(uint32); 751 752 regarray rdbal_I350 rw addr(base, 0xC000)[8;0x40] 753 "Rx descr. base addr low" type(uint32); 754 regarray rdbah_I350 rw addr(base, 0xC004)[8;0x40] 755 "Rx descr. base addr high" type(uint32); 756 757 // 13.3.40/48 and 13.3.62/71 758 // Note that the description of the transmit length (13.3.62/71) refers to 759 // the size of the descriptor buffer in bytes. This is misleading; the whole 760 // register (raw value) refers to that, but the bottom 7 bits must be zero. 761 regtype dqlen "Descriptor length value" { 762 _ 7 mbz; 763 len 13 "Num. descriptors (x8)"; 764 _ 12 mbz; 765 }; 766 regarray rdlen rw addr(base, 0x2808)[2;0x100] 767 "Rx descriptor length" type(dqlen); 768 769 regarray rdlen_I350 rw addr(base, 0xC008)[8;0x40] 770 "Rx descriptor length" type(dqlen); 771 772 // 13.3.41/49/42/50 773 regtype dqval "Descriptor head/tail value" { 774 val 16 "value"; 775 _ 16 mbz; 776 }; 777 regarray rdh rw addr(base, 0x2810)[2;0x100] "Rx descr. head" type(dqval); 778 regarray rdt rw addr(base, 0x2818)[2;0x100] "Rx descr. tail" type(dqval); 779 780 regarray rdh_I350 rw addr(base, 0xC010)[8;0x40] "Rx descr. head" type(dqval); 781 regarray rdt_I350 rw addr(base, 0xC018)[8;0x40] "Rx descr. tail" type(dqval); 782 783 // 13.3.43 784 register rdtr rw addr(base, 0x2820) "Rx. interrupt delay timer" { 785 delay 16 "delay timer (x 1.024us)"; 786 _ 15 mbz; 787 fpd 1 "Flush partial descriptor block"; 788 }; 789 790 // 13.3.44/51 791 constants threshgran "Threshold granularity" { 792 gran_cache = 0 "Cache line granularity"; 793 gran_desc = 1 "Descriptor granularity"; 794 }; 795 796 regarray rxdctl rw addr(base, 0x2828)[2;0x100] "Rx descriptor control" { 797 pthresh 6 "Prefetch threshold"; 798 _ 2 mbz; 799 hthresh 6 "Host threshold"; 800 _ 2 mbz; 801 wthresh 6 "Write back threshold"; 802 _ 2 mbz; 803 gran 1 type(threshgran) "Granularity"; 804 _ 7 mbz; 805 }; 806 807 regarray rxdctl_82575 rw also addr(base, 0x2828)[2;0x100] "Rx descriptor control" { 808 pthresh 6 "Prefetch threshold"; 809 _ 2 mbz; 810 hthresh 6 "Host threshold"; 811 _ 2 mbz; 812 wthresh 6 "Write back threshold"; 813 _ 3 mbz; 814 enable 1 "Granularity"; 815 swflush 1 "Receive Software Flush"; 816 _ 5 mbz; 817 }; 818 819 regarray rxdctl_I350 rw also addr(base, 0xC028)[8;0x40] "Rx descriptor control" { 820 pthresh 5 "Prefetch threshold"; 821 _ 3 mbz; 822 hthresh 5 "Host threshold"; 823 _ 3 mbz; 824 wthresh 5 "Write back threshold"; 825 _ 4 mbz; 826 enable 1 "Receive Queue Enable"; 827 swflush 1 "Receive Software Flush"; 828 _ 5 mbz; 829 }; 830 831 // 13.3.45 832 register radv rw addr(base, 0x282c) "Rx absolute intr. delay" { 833 idv 16 "Interrupt delay value"; 834 _ 16 mbz; 835 }; 836 837 // 13.3.52 838 register rsrpd rw addr(base, 0x2c00) "Rx small packet detect interrupt" { 839 size 12 "Max size of small packet"; 840 _ 20 mbz; 841 }; 842 843 // 13.3.53 844 register raid rw addr(base, 0x2c08) "Rx ACK interrupt delay" { 845 idv 16 "Interrupt delay value (x 1.024us)"; 846 _ 16 mbz; 847 }; 848 849 // 13.3.54 850 register cpuvec rw addr(base, 0x2c10) "CPU vector" type(uint32); 851 852 // 13.3.55 853 register rxcsum rw addr(base, 0x5000) "Receive checksum control" { 854 pcss 8 "Packet checksum start"; 855 ipofld 1 "IP checksum offload enable"; 856 tuofld 1 "TCP/UDP checksum offload enable"; 857 _ 22 mbz; 858 }; 859 860 // 13.3.56 861 register rfctl rw addr(base, 0x5008) "Receive filter control" { 862 iscsi_dis 1 "iSCSI filtering disable"; 863 iscsi_dwc 5 "iSCSI dword count"; 864 nfsw_dis 1 "NFS write filtering disable"; 865 nfsr_dis 1 "NFS read filtering disable"; 866 nfs_ver 2 "NFS version (+2)"; 867 ipv6_dis 1 "IPv6 filtering disable"; 868 ipv6xsum_dis 1 "IPv6 xsum disable"; 869 ackdis 1 "ACK accelerator disable"; 870 ackd_dis 1 "ACK data disable"; 871 ipfrsp_dis 1 "IP fragment split disable"; 872 exsten 1 "Extended status enable"; 873 _ 16 mbz; 874 }; 875 876 regarray srrctl rw addr(base, 0xC00C)[8; 0x40] "Split and Replication Receive Control" { 877 bsizepacket 7 "Receive Buffer Size for Packet Buffer, The value is in 1 KB resolution."; 878 dmacq_dis 1 "DMA Coalescing disable"; 879 bsizeheader 6 "Receive Buffer Size for Header Buffer"; 880 _ 6 mbz; 881 rdmts 5 "Receive Descriptor Minimum Threshold Size"; 882 desctype 3 "Defines the descriptor in Rx"; 883 _ 2 mbz; 884 timestamp 1 "Timestamp Received packet"; 885 drop_en 1 "Drop Enabled"; 886 }; 887 888 /************************************ 889 * Transmit registers 890 ***********************************/ 891 892 // 13.3.57 893 constants coldist "Recommended collision distances" { 894 cd_half = 0x200 "512 byte-times"; 895 cd_full = 0x3f "64 byte-times"; 896 cd_esb = 0x40 "64 byte-times (for 631xESB/632xESB)"; 897 cd_internal = 0x42 "i350 internal phy mode"; 898 }; 899 register tctl rw addr(base, 0x400) "Transmit control" { 900 _ 1 mbz; 901 en 1 "Transmit enable"; 902 _ 1 mbz; 903 psp 1 "Pad short packets"; 904 ct 8 "Collision threshold"; 905 bst 10 "Back-Off Slot time"; 906 swxoff 1 "Software XOFF transmission"; 907 _ 1 mbz; 908 rtlc 1 "Retransmit on late collision"; 909 unortx 1 "Underrun no re-transmit"; 910 txcscmt 2 "Tx descriptor minimum threshold"; 911 mulr 1 "Multiple request support"; 912 _ 3; 913 }; 914 915 // 13.3.58 916 register tctl_ext rw addr(base, 0x0404) "Transmit control extended" { 917 _ 10 mbz; 918 cold 10 type(coldist) "Collision distance"; 919 _ 12; 920 }; 921 922 // 13.3.59 923 register tipg rw addr(base, 0x0410) "Transmit IPQ" { 924 ipgt 10 "IPG back to back (x MAC clock, +4)"; 925 ipgr1 10 "IPG Part 1"; 926 ipgr2 10 "IPG after deferral"; 927 _ 2 mbz; 928 }; 929 930 // 931 // The e1000 has two transmit queues, hence two sets of the 932 // remaining registers 933 // 934 935 // 13.3.60/61/69/70 936 regarray tdbal rw addr(base, 0x3800)[2;0x100] "Tx descr. base addr. low" 937 type(uint32); 938 regarray tdbah rw addr(base, 0x3804)[2;0x100] "Tx descr. base addr. hi" 939 type(uint32); 940 941 regarray tdbal_I350 rw addr(base, 0xE000)[8;0x40] "Tx descr. base addr. low" 942 type(uint32); 943 regarray tdbah_I350 rw addr(base, 0xE004)[8;0x40] "Tx descr. base addr. hi" 944 type(uint32); 945 946 // 13.3.62/71 947 regarray tdlen rw addr(base, 0x3808)[2;0x100] "Tx descr. length" type(dqlen); 948 regarray tdlen_I350 rw addr(base, 0xE008)[8;0x40] "Tx descr. length" type(dqlen); 949 950 // 13.3.63/64/73 951 regarray tdh rw addr(base, 0x3810)[2;0x100] "Tx descr. head" type(dqval); 952 regarray tdt rw addr(base, 0x3818)[2;0x100] "Tx descr. tail" type(dqval); 953 regarray tdh_I350 rw addr(base, 0xE010)[8;0x40] "Tx descr. head" type(dqval); 954 regarray tdt_I350 rw addr(base, 0xE018)[8;0x40] "Tx descr. tail" type(dqval); 955 // 13.3.65 956 register tidv rw addr(base, 0x3820) "Transmit interrupt delay value" { 957 idv 16 "Interupt delay value"; 958 _ 15 mbz; 959 fdp 1 wo "Flush partial description block"; 960 }; 961 962 regarray tdwbal rw addr(base, 0xE038)[8; 0x40] "Tx Descriptor Completion Write" { 963 head_wb_en 1 "Head Write-Back Enable"; 964 wb_on_eitr 1 "write back is done upon EITR expiration."; 965 HeadWB_Low 30 "Bits 31:2 of the head write-back memory location"; 966 }; 967 968 regarray tdwbah rw addr(base, 0xE03C)[8; 0x40] "Tx Descriptor Completion Write" 969 type(uint32); 970 971 // 13.3.66/74 972 regarray txdctl rw addr(base, 0x3828)[2;0x100] "Transmit descr. control queue" { 973 pthresh 6 "Prefetch threshold"; 974 _ 2 mbz; 975 hthresh 8 "Host threshold"; 976 wthresh 6 "Write back threshold"; 977 _ 1 mb1; 978 _ 1; 979 gran 1 type(threshgran) "Granularity"; 980 lwthresh 7 "Transmit descriptor low threshold"; 981 }; 982 983 regarray txdctl_I350 rw addr(base, 0xE028)[8;0x40] "Transmit descr. control queue" { 984 pthresh 5 "Prefetch threshold"; 985 _ 3 mbz; 986 hthresh 5 "Host threshold"; 987 _ 3 mbz; 988 wthresh 5 "Write back threshold"; 989 _ 3 mbz; 990 _ 1 mbz; 991 enable 1 "Queue Enable"; 992 swflsh 1 "Software Flush"; 993 priority 1 "Priority"; 994 hwbthresh 4 "Transmit Head writeback threshold"; 995 }; 996 997 regarray txdctl_82575 rw also addr(base, 0x3828)[4;0x100] "Transmit descr. control queue for 82575 cards" { 998 pthresh 6 "Prefetch threshold"; 999 _ 2 mbz; 1000 hthresh 6 "Host threshold"; 1001 _ 2; 1002 wthresh 6 "Write back threshold"; 1003 _ 3 mb1; 1004 enable 1 "Enable the queue"; 1005 swflsh 1 "Transmit Software Flush"; 1006 priority 1 "Priority"; 1007 _ 4; 1008 }; 1009 1010 // 13.3.67 1011 register tadv rw addr(base, 0x382c) "Tx absolute intr. delay" { 1012 idv 16 "Interrupt delay value"; 1013 _ 16 mbz; 1014 }; 1015 1016 // 13.3.68/75 1017 regarray tarc rw addr(base, 0x3840)[2;0x100] "Tx arbitration counter" { 1018 count 7 "Transmit arbitration count"; 1019 _ 1; 1020 ratio 2 "Compensation ratio (1 / 2^val)"; 1021 enable 1 mb1; 1022 _ 10 mbz; 1023 _ 1 mb1; 1024 _ 1 mbz; 1025 _ 4 mb1; 1026 _ 5 mbz; 1027 }; 1028 1029 /************************************ 1030 * Filter registers 1031 ***********************************/ 1032 1033 // 13.4.1 1034 regarray mta rw addr(base, 0x5200)[128] "Multicast table array" type(uint32); 1035 1036 // 13.4.2 1037 regarray ral rw addr(base, 0x5400)[16;8] "Receive address low" type(uint32); 1038 1039 // 13.4.3 1040 constants addrsel "Address select" { 1041 as_dest = 0b00 "Destination"; 1042 as_src = 0b01 "Source"; 1043 }; 1044 regarray rah rw addr(base, 0x5404)[16;8] "Receive address high" { 1045 rah 16 "Receive address high"; 1046 asel 2 type(addrsel) "Address select"; 1047 _ 13 mbz; 1048 av 1 "Address valid"; 1049 }; 1050 1051 // 13.4.4 1052 regarray vfta rw addr(base, 0x5600)[128] 1053 "VLAN filter table array" type(uint32); 1054 1055 // 13.4.5 1056 constants mrqen "Multiple rx queue enable" { 1057 mrq_dis = 0b00 "Multiple queues disabled"; 1058 mrq_rss = 0b01 "Multiple queues enabled by MSFT RSS"; 1059 }; 1060 register mrq rw addr(base, 0x5818) "Multiple queues receive command" { 1061 mrqe 2 type(mrqen) "Multiple rx queues enable"; 1062 rssie 1 "RSS interrupt enable"; 1063 _ 13 mbz; 1064 tcp4 1 "Enable TCP IPv4 hash"; 1065 ipv4 1 "Enable IPv4 hash"; 1066 tcp6ex 1 "Enable TCP IPv6 Ex hash"; 1067 ipv6ex 1 "Enable IPv6 Ex hash"; 1068 ipv6 1 "Enable IPv6 hash"; 1069 _ 11; 1070 }; 1071 1072 // 13.4.6 1073 register rssim rw addr(base, 0x5864) "RSS interrupt mask" type(uint32); 1074 1075 // 13.4.7 1076 register rssir rw addr(base, 0x5868) "RSS interrupt request" type(uint32); 1077 1078 // 13.4.8 1079 regarray reta rw addr(base, 0x5c00)[128] "Redirection table" type(uint8); 1080 1081 // 13.4.9 1082 regarray rssrk rw addr(base, 0x5c80)[40] "RSS Random key" type(uint8); 1083 1084 /************************************ 1085 * Wakeup registers 1086 ***********************************/ 1087 1088 // 13.5.1 1089 register wuc rw addr(base, 0x5800) "Wakeup control" { 1090 apme 1 "Advanced power mgmt enable"; 1091 pme_en 1 "PME enable"; 1092 pme_stat 1 "PME status"; 1093 apmpme 1 "Assert PME on APM wakeup"; 1094 _ 28; 1095 }; 1096 1097 // 13.5.2 1098 regtype wakeup "Wakeup register" { 1099 lnkc 1 "Link status change"; 1100 mag 1 "Magic packet"; 1101 ex 1 "Directed exact"; 1102 mc 1 "Directed multicast"; 1103 bc 1 "Broadcast"; 1104 arp 1 "ARP request packet"; 1105 ipv4 1 "Directed IPv4"; 1106 ipv6 1 "Directed IPv6"; 1107 _ 7 mbz; 1108 notco 1 "Ignore TCO/management packets"; 1109 flx0 1 "Flexible filter 0 enable"; 1110 flx1 1 "Flexible filter 1 enable"; 1111 flx2 1 "Flexible filter 2 enable"; 1112 flx3 1 "Flexible filter 3 enable"; 1113 _ 12 mbz; 1114 }; 1115 register wufc rw addr(base, 0x5808) "Wakeup filter control" type(wakeup); 1116 1117 // 13.5.3 1118 register wus ro addr(base, 0x5810) "Wakeup status" type(wakeup); 1119 1120 // 13.5.4 1121 register ipav rw addr(base, 0x5838) "IP address valid" { 1122 v40 1 "IPv4 address 0 valid"; 1123 v41 1 "IPv4 address 1 valid"; 1124 v42 1 "IPv4 address 2 valid"; 1125 v43 1 "IPv4 address 3 valid"; 1126 _ 12 mbz; 1127 v60 1 "IPv6 address 0 valid"; 1128 _ 15 mbz; 1129 }; 1130 1131 // 13.5.5 1132 regarray ip4at rw addr(base, 0x5840)[4;8] 1133 "IPv4 address table" type(uint32); 1134 1135 // 13.5.6 1136 regarray ip6at rw addr(base, 0x5880)[4] "IPv6 address table" type(uint32); 1137 1138 // 13.5.7 1139 register wupl rw addr(base, 0x5900) "Wakeup packet length" { 1140 len 12 "Length"; 1141 _ 20 mbz; 1142 }; 1143 1144 // 13.5.8 1145 regarray wupm rw addr(base, 0x5a00)[32] "Wakeup packet memory" type(uint32); 1146 1147 // 13.5.9 1148 regarray fflt rw addr(base, 0x5f00)[4;8] "Flexible filter length table" { 1149 len 11 "Length"; 1150 _ 21 mbz; 1151 }; 1152 regarray ffltco rw addr(base, 0x5f20)[2;8] "Flexible filter length table" { 1153 tcolen 11 "Length"; 1154 _ 21 mbz; 1155 }; 1156 1157 // 13.5.10 1158 regarray ffmt rw addr(base, 0x9000)[128;8] "Flexible filter mask table" { 1159 mask 4 "mask"; 1160 _ 28 mbz; 1161 }; 1162 1163 // 13.5.11 1164 regarray ffvt rw addr(base, 0x9800)[128;8] "Flexible filter value table" { 1165 val0 8 "Value 0"; 1166 val1 8 "Value 1"; 1167 val2 8 "Value 2"; 1168 val3 8 "Value 3"; 1169 }; 1170 1171 /************************************ 1172 * Management control registers 1173 ***********************************/ 1174 1175 // 13.6.1 1176 register manc rw addr(base, 0x5820) "Management control" { 1177 _ 3 mbz; 1178 en_flexport0 1 "Enable flex UDP/TCP port 0 filtering"; 1179 en_flexport1 1 "Enable flex UDP/TCP port 1 filtering"; 1180 en_flexport2 1 "Enable flex UDP/TCP port 2 filtering"; 1181 flex_tco1_filter 1 "Enable TCO filter 1"; 1182 flex_tco0_filter 1 "Enable TCO filter 0"; 1183 rmcp_en 1 "Enable RMCP 0x026f filtering"; 1184 o298_en 1 "Enable RMCP 0x0298 filtering"; 1185 _ 3 mbz; 1186 arp_req_en 1 "Enable ARP request filtering"; 1187 neighbor_en 1 "Enable neighbor discovery filtering"; 1188 arp_res_en 1 "Enable ARP response filtering"; 1189 tco_reset 1 "TCO reset occurred"; 1190 rcv_tco_en 1 "Receive TCO packets enable"; 1191 blk_phyrst_on_ide 1 "Block PHY reset and power on state changes"; 1192 rcv_all 1 "Receive all enable"; 1193 en_mac16_filter 1 "Enable MAC address 16 filtering"; 1194 en_mng2host 1 "Enable firmware packets to host memory"; 1195 en_ip_addrfilter 1 "Enable IP address filtering"; 1196 en_xsum_filter 1 "Enable Xsum filtering to firmware"; 1197 br_en 1 "Enable broadcast filtering"; 1198 _ 7 mbz; 1199 }; 1200 1201 /************************************ 1202 * PCIe registers 1203 ***********************************/ 1204 1205 // NOTE: Intel in their infinite wisdom have chosen to list these 1206 // registers MSBfirst in the documentation, as opposed to all the 1207 // others which are LSBfirst... 1208 1209 // 13.7.1 1210 register gcr rw addr(base, 0x5b00) "PCIe control" { 1211 rxd_nosnoop 1 "Receive data write"; 1212 rxdscw_nosnoop 1 "Receive descriptor write"; 1213 rxdscr_nosnoop 1 "Receive descriptor read"; 1214 txd_nosnoop 1 "Transmit data write"; 1215 txdscw_nosnoop 1 "Transmit descriptor write"; 1216 txdscr_nosnoop 1 "Transmit descriptor read"; 1217 elec_idle_in0 1 ro "SerDes0 internal electrical idle indicator"; 1218 elec_idle_in1 1 ro "SerDes1 internal electrical idle indicator"; 1219 self_test_enable 1 "Perform self test"; 1220 _ 12 mbz; 1221 logheader 1 "Log header into PCI config space"; 1222 _ 1 mbz; 1223 l1el_msb 1 ro "L1 Entry latency msb"; 1224 l0s_el 1 "L0s entry latency"; 1225 l1el_lsb 2 ro "L1 Entry latency lsbs"; 1226 l1_aw_l0s 1 "L1 act without L0s_rx correlation"; 1227 gio_dis_rderr 1 "Disable running disparity err"; 1228 gio_good_10s 1 "Force good PCIe l0s training"; 1229 self_test_result 1 "Result of self test"; 1230 dis_tmout 1 "Disable PCIe timeout mechanism"; 1231 }; 1232 1233 // 13.7.2 1234 register gscl1 rw addr(base, 0x5b10) "PCIe statistics control 1" { 1235 count_en0 1 "Enable PCIe stats counter 0"; 1236 count_en1 1 "Enable PCIe stats counter 1"; 1237 count_en2 1 "Enable PCIe stats counter 2"; 1238 count_en3 1 "Enable PCIe stats counter 3"; 1239 _ 23; 1240 count_test 1 "Test bit"; 1241 en_64bit 1 "Enable two 64-bit counters instead of 4 32-bit"; 1242 count_reset 1 "Reset indication of PCIe stats"; 1243 count_stop 1 "Stop indication"; 1244 count_start 1 "Start indication"; 1245 }; 1246 1247 // 13.7.3 1248 register gscl2 rw addr(base, 0x5b14) "PCIe statistics control 2" { 1249 event0 8 "Event number that counter 0 counts"; 1250 event1 8 "Event number that counter 1 counts"; 1251 event2 8 "Event number that counter 2 counts"; 1252 event3 8 "Event number that counter 3 counts"; 1253 }; 1254 1255 // 13.7.4 1256 register gscl3 rw addr(base, 0x5b18) "PCIe statistics control 3" { 1257 fc_th0 12 "Threshold of flow control credits 0"; 1258 _ 4; 1259 fc_th1 12 "Threshold of flow control credits 1"; 1260 _ 4; 1261 }; 1262 1263 // 13.7.5 1264 register gscl4 rw addr(base, 0x5b1c) "PCIe statistics control 4" { 1265 coml_th 10 "Completions latency threshold"; 1266 rb_th 6 "Retry buffer threshold"; 1267 _ 16; 1268 }; 1269 1270 // 13.7.6-9 1271 regarray gscn rw addr(base, 0x5b20)[4] "PCIe counter" type(uint32); 1272 1273 // 13.7.10 1274 constants fps "Function power state" { 1275 fps_dr = 0b00 "DR"; 1276 fps_d0u = 0b01 "D0u"; 1277 fps_d0a = 0b10 "Doa"; 1278 fps_d3 = 0b11 "D3"; 1279 }; 1280 register factps ro addr(base, 0x5b30) "Fn. active & power state to MNG" { 1281 f0ps 2 type(fps) "Power state of fn. 0"; 1282 lan0v 1 "LAN 0 valid enable"; 1283 f0aux 1 "Fn. 0 aux power enable shadow"; 1284 lan0en 1 "LAN 0 enabled"; 1285 _ 1; 1286 f1ps 2 type(fps) "Power state of fn. 1"; 1287 lan1v 1 "LAN 1 valid enable"; 1288 f1aux 1 "Fn. 1 aux power enable shadow"; 1289 lan1en 1 "LAN 1 enabled"; 1290 _ 1; 1291 f2ps 2 type(fps) "Power state of fn. 2"; 1292 ide_en 1 "IDE (function 2) enable"; 1293 f2aux 1 "Fn. 2 aux power enable shadow"; 1294 _ 2; 1295 f3ps 2 type(fps) "Power state of fn. 3"; 1296 sp_en 1 "SP (function 3) enable"; 1297 f3aux 1 "Fn. 3 aux power enable shadow"; 1298 _ 2; 1299 f4ps 2 type(fps) "Power state of fn. 4"; 1300 ipmi_en 1 "IPMI (function 4) enable"; 1301 f4aux 1 "Fn. 4 aux power enable shadow"; 1302 _ 1; 1303 mngcg 1 "MNG clock gated"; 1304 lanfs 1 "LAN function select"; 1305 pmchg 1 "PM state changed"; 1306 }; 1307 1308 // 13.7.11-12 1309 regtype anal_ctl "Analog circuit configuration" { 1310 data 8 "Data to SerDes"; 1311 address 8 "Address to SerDes"; 1312 _ 15; 1313 done 1 "Done indicator"; 1314 }; 1315 regarray gioanactl rw addr(base,0x5b34)[4] "Analog control" type(anal_ctl); 1316 1317 // 13.7.13 1318 register gioanactlall rw addr(base,0x5b44) "Analog control" type(anal_ctl); 1319 1320 // 13.7.14 1321 register ccmctl rw addr(base,0x5b48) "CCM analog control" type(anal_ctl); 1322 1323 // 13.7.15 1324 register anactl rw also addr(base,0x5b48) "Analog control" { 1325 data 8 "Data to/from analog register"; 1326 address 8 "Address of analog register"; 1327 _ 14; 1328 write 1 "Read/write command"; 1329 done 1 "Done indication"; 1330 }; 1331 1332 // 13.7.16 1333 register scctl rw addr(base, 0x5b4c) "SCC analog control" type(anal_ctl); 1334 1335 // 13.7.17 1336 register swsm rw addr(base, 0x5b50) "Software semaphore" { 1337 smbi 1 "Semaphore bit"; 1338 swesmbi 1 "Software EEPROM semaphore bit"; 1339 wmng 1 "Wake MNG clock"; 1340 _ 29; 1341 }; 1342 1343 // 13.7.18 1344 constants fwmode "Firmware mode" { 1345 nomng = 0b000 "No MNG"; 1346 ptmode = 0b010 "PT mode"; 1347 hieo = 0b100 "Host interface firmware"; 1348 }; 1349 constants pcierr "PCIe external error indication" { 1350 pe_none = 0x00 "No error"; 1351 pe_mschk = 0x01 "Bad checksum in manageability sections"; 1352 pe_prot = 0x02 "EEPROM protection disabled"; 1353 pe_clkoff = 0x03 "Clock off command executed"; 1354 pe_flchk = 0x04 "Bad checksum in flash header"; 1355 pe_pschk = 0x05 "Bad checksum in patch section"; 1356 pe_lschk = 0x06 "Bad checksum in loader section"; 1357 pe_dschk = 0x07 "Bad checksum in diagnostic section"; 1358 pe_inval = 0x08 "Invalid firmware mode"; 1359 pe_tlbe = 0x09 "TLB table exceeded"; 1360 pe_eerd = 0x0a "EEPROM read failed"; 1361 pe_hwver = 0x0b "Bad hardware version in patch load"; 1362 pe_sfrd = 0x0c "SFlash read failed"; 1363 pe_unspec = 0x0d "Unspecified error"; 1364 pe_auth = 0x0e "Flash authentication failed"; 1365 pe_pfrd = 0x0f "PFlash read failed"; 1366 pe_ifep = 0x10 "Invalid Flash entry point"; 1367 }; 1368 register fwsm rw addr(base, 0x5b54) "Firmware semaphore" { 1369 eep_fw 1 "EEPROM firmware semaphore"; 1370 fw_mode 3 type(fwmode) "Firmware mode"; 1371 ide_on 1 "IDE redirection on"; 1372 sol_on 1 "SOL on"; 1373 eep_rl 1 "EEPROM reloaded indication"; 1374 _ 8; 1375 fwval 1 "Firmware valid bit"; 1376 rstcnt 3 "Reset counter"; 1377 error 6 type(pcierr) "External error indication"; 1378 _ 7; 1379 }; 1380 1381 /************************************ 1382 * Statistics registers 1383 ***********************************/ 1384 1385 // 13.8 ff 1386 register crcerrs rc addr(base, 0x4000) 1387 "CRC error count" type(uint32); 1388 register algnerrc rc addr(base, 0x4004) 1389 "Alignment error count" type(uint32); 1390 register symerrs rc addr(base, 0x4008) 1391 "Symbol error count" type(uint32); 1392 register rxerrc rc addr(base, 0x400c) 1393 "Receive error count" type(uint32); 1394 register mpc rc addr(base, 0x4010) 1395 "Missed packets count" type(uint32); 1396 register scc rc addr(base, 0x4014) 1397 "Single collision count" type(uint32); 1398 register ecol rc addr(base, 0x4018) 1399 "Excessive collisions count" type(uint32); 1400 register mcc rc addr(base, 0x401c) 1401 "Multiple collision count" type(uint32); 1402 register latecol rc addr(base, 0x4020) 1403 "Late collisions count" type(uint32); 1404 register colc rc addr(base, 0x4028) 1405 "Collision count" type(uint32); 1406 register dc rc addr(base, 0x4030) 1407 "Defer count" type(uint32); 1408 register tncrs rc addr(base, 0x4034) 1409 "Transmit with no CRS" type(uint32); 1410 register sec rc addr(base, 0x4038) 1411 "Sequence error count" type(uint32); 1412 register cexterr rc addr(base, 0x403c) 1413 "Carrier extension error count" type(uint32); 1414 register rlec rc addr(base, 0x4040) 1415 "Receive length error count" type(uint32); 1416 register xonrxc rc addr(base, 0x4048) 1417 "XON received count" type(uint32); 1418 register xontxc rc addr(base, 0x404c) 1419 "XON transmitted count" type(uint32); 1420 register xoffrxc rc addr(base, 0x4050) 1421 "XOFF received count" type(uint32); 1422 register xofftxc rc addr(base, 0x4054) 1423 "XOFF transmitted count" type(uint32); 1424 register fcurc rc addr(base, 0x4058) 1425 "FC received unsupported count" type(uint32); 1426 register prc64 rc addr(base, 0x405c) 1427 "Packets received (64 bytes) count" type(uint32); 1428 register prc127 rc addr(base, 0x4060) 1429 "Packets received (65-127 bytes) count" type(uint32); 1430 register prc255 rc addr(base, 0x4064) 1431 "Packets received (128-255 bytes) count" type(uint32); 1432 register prc511 rc addr(base, 0x4068) 1433 "Packets received (256-511 bytes) count" type(uint32); 1434 register prc1023 rc addr(base, 0x406c) 1435 "Packets received (512-1023 bytes) count" type(uint32); 1436 register prc1522 rc addr(base, 0x4070) 1437 "Packets received (1024-max bytes) count" type(uint32); 1438 register gprc rc addr(base, 0x4074) 1439 "Good packets received count" type(uint32); 1440 register bprc rc addr(base, 0x4078) 1441 "Broadcast packets received count" type(uint32); 1442 register mcprc rc addr(base, 0x407c) 1443 "Multicast packets received count" type(uint32); 1444 register gptc rc addr(base, 0x4080) 1445 "Good packets transmitted count" type(uint32); 1446 register gorcl rc addr(base, 0x4088) 1447 "Good octets received count low" type(uint32); 1448 register gorch rc addr(base, 0x408c) 1449 "Good octets received count high" type(uint32); 1450 register gotcl rc addr(base, 0x4090) 1451 "Good octets transmitted count low" type(uint32); 1452 register gotch rc addr(base, 0x4094) 1453 "Good octets transmitted count high" type(uint32); 1454 register rnbc rc addr(base, 0x40a0) 1455 "Receive no buffers count" type(uint32); 1456 register ruc rc addr(base, 0x40a4) 1457 "Receive undersize count" type(uint32); 1458 register rfc rc addr(base, 0x40a8) 1459 "Receive fragment count" type(uint32); 1460 register roc rc addr(base, 0x40ac) 1461 "Receive oversize count" type(uint32); 1462 register rjc rc addr(base, 0x40b0) 1463 "Receive jabber count" type(uint32); 1464 register mprc rc addr(base, 0x40b4) 1465 "Management packets receive count" type(uint32); 1466 register mpdc rc addr(base, 0x40b8) 1467 "Management packets dropped count" type(uint32); 1468 register mptc rc addr(base, 0x40bc) 1469 "Management packets transmitted count" type(uint32); 1470 register torl rc addr(base, 0x40c0) 1471 "Total octets received low" type(uint32); 1472 register torh rc addr(base, 0x40c4) 1473 "Total octets received high" type(uint32); 1474 register totl rc addr(base, 0x40c8) 1475 "Total octets transmitted low" type(uint32); 1476 register toth rc addr(base, 0x40cc) 1477 "Total octets transmitted high" type(uint32); 1478 register tpr rc addr(base, 0x40d0) 1479 "Total packets received" type(uint32); 1480 register tpt rc addr(base, 0x40d4) 1481 "Total packets transmitted" type(uint32); 1482 register ptc64 rc addr(base, 0x40d8) 1483 "Packets transmitted (64 bytes) count" type(uint32); 1484 register ptc127 rc addr(base, 0x40dc) 1485 "Packets transmitted (65-127 bytes) count" type(uint32); 1486 register ptc255 rc addr(base, 0x40e0) 1487 "Packets transmitted (128-255 bytes) count" type(uint32); 1488 register ptc511 rc addr(base, 0x40e4) 1489 "Packets transmitted (256-511 bytes) count" type(uint32); 1490 register ptc1023 rc addr(base, 0x40e8) 1491 "Packets transmitted (512-1023 bytes) count" type(uint32); 1492 register ptc1522 rc addr(base, 0x40ec) 1493 "Packets transmitted (1024-max bytes) count" type(uint32); 1494 register mcptc rc addr(base, 0x40f0) 1495 "Multicast packets transmitted count" type(uint32); 1496 register bptc rc addr(base, 0x40f4) 1497 "Broadcast packets transmitted count" type(uint32); 1498 register tsctc rc addr(base, 0x40f8) 1499 "TCP segmentation context transmitted count" type(uint32); 1500 register tsctfc rc addr(base, 0x40fc) 1501 "TCP segmentation context tx fail count" type(uint32); 1502 register iac rc addr(base, 0x4100) 1503 "Interrupt assertion count" type(uint32); 1504 register icrxptc rc addr(base, 0x4104) 1505 "Interrupt cause rx packet timer expire count" type(uint32); 1506 register icrxatc rc addr(base, 0x4108) 1507 "Interrupt cause rx absolute timer expire count" type(uint32); 1508 register ictxptc rc addr(base, 0x410c) 1509 "Interrupt cause tx packet timer expire count" type(uint32); 1510 register ictxatc rc addr(base, 0x4110) 1511 "Interrupt cause tx absolute timer expire count" type(uint32); 1512 register ictxqec rc addr(base, 0x4118) 1513 "Interrupt cause transmit queue empty count" type(uint32); 1514 register ictxdltc rc addr(base, 0x411c) 1515 "Interrupt cause transmit descriptor low threshold count" type(uint32); 1516 register icrxdmtc rc addr(base, 0x4120) 1517 "Interrupt cause receive descriptor minimum threshold count" type(uint32); 1518 register icrxoc rc addr(base, 0x4124) 1519 "Interrupt cause receive overrun count" type(uint32); 1520 1521 regarray statsregs rc also addr(base, 0x4000)[74] 1522 "All stats registers" type(uint32); 1523 1524 1525 /************************************ 1526 * Descriptors 1527 ***********************************/ 1528 1529 // 3.2.4 1530 datatype legacy_rdesc lsbfirst(64) "Legacy rx descriptor" { 1531 addr 64 "Buffer address"; 1532 length 16 "Packet length"; 1533 checksum 16 "Packet checksum"; 1534 // Status 1535 dd 1 "Descriptor done"; 1536 eop 1 "End of packet"; 1537 ixsm 1 "Ignore checksum indication"; 1538 vp 1 "Packet is 802.1q (matched VET)"; 1539 udpcs 1 "UDP checksum calculated on packet"; 1540 tcpcs 1 "TCP checksum calculated on packet"; 1541 ipcs 1 "IPv4 checksum calculated on packet"; 1542 pif 1 "Passed in-exact filter"; 1543 // Errors 1544 ce 1 "CRC or alignment error"; 1545 se 1 "Symbol error"; 1546 seq 1 "Sequence error"; 1547 _ 2; 1548 tcpe 1 "TCP/UDP checksum error"; 1549 ipe 1 "IPv4 checksum error"; 1550 rxe 1 "RX data error"; 1551 // VLAN tag field 1552 vlan 12 "VLAN id"; 1553 cr 1 "Canonical form indicator"; 1554 pri 3 "802.1p priority"; 1555 }; 1556 1557 // 3.2.5 1558 datatype rdesc_read lsbfirst(64) "Extended rx descriptor (read format)" { 1559 addr 64 "Buffer address"; 1560 dd 1 "Descriptor done"; 1561 _ 63; 1562 }; 1563 datatype rdesc_write lsbfirst(64) "Extended rx descriptor (write format)" { 1564 // MRQ 1565 rss 4 type(rsstype) "RSS type"; 1566 _ 4; 1567 queue 5 "Receive queue"; 1568 _ 19; 1569 // IP id; note that the RSS hash can overlay the next two fields 1570 ipid 16 "IP header identification field"; 1571 // Checksum 1572 checksum 16 "Packet checksum"; 1573 // Extended status 1574 dd 1 "Descriptor done"; 1575 eop 1 "End of packet"; 1576 ixsm 1 "Ignore checksum indication"; 1577 vp 1 "Packet is 802.1q (matched VET)"; 1578 udpcs 1 "UDP checksum calculated on packet"; 1579 tcpcs 1 "TCP checksum calculated on packet"; 1580 ipcs 1 "IPv4 checksum calculated on packet"; 1581 pif 1 "Passed in-exact filter"; 1582 _ 1; 1583 ipidv 1 "IP identification valid"; 1584 udpv 1 "Valid UDP checksum"; 1585 _ 4; 1586 ack 1 "ACK packet identification"; 1587 _ 4; 1588 // Extended errors 1589 _ 4; 1590 ce 1 "CRC or alignment error"; 1591 se 1 "Symbol error"; 1592 seq 1 "Sequence error"; 1593 _ 2; 1594 tcpe 1 "TCP/UDP checksum error"; 1595 ipe 1 "IPv4 checksum error"; 1596 rxe 1 "RX data error"; 1597 // Length 1598 length 16 "Packet length"; 1599 // VLAN tag field 1600 vlan 12 "VLAN id"; 1601 cr 1 "Canonical form indicator"; 1602 pri 3 "802.1p priority"; 1603 }; 1604 1605 // 3.2.5.4 1606 constants rsstype "RSS computation type" { 1607 no_rss = 0x0 "No RS computation"; 1608 tcp_v4 = 0x1 "IPv4 with TCP hash"; 1609 ipv4 = 0x2 "IPv4 hash"; 1610 tcp_v6 = 0x3 "IPv6 with TCP hash"; 1611 ipv6 = 0x5 "IPv6 hash"; 1612 }; 1613 1614 /************************************ 1615 * Virtualization Registers 1616 ***********************************/ 1617 register txswc rw addr(base, 0x5ACC) { 1618 macas 8 "Enable anti spoofing filter on MAC addresses"; 1619 vlanas 8 "Enable anti spoofing filter on VLAN tags"; 1620 lle 8 "Local loopback enable"; 1621 _ 7 mbz; 1622 loopback_en 1 "Enable VMDQ loopback."; 1623 }; 1624 1625}; 1626