1/* 2 * Copyright (c) 2015, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * cpuid_intel.dev 11 * 12 * DESCRIPTION: ia32 CPU ID instruction results 13 * 14 * See: 15 * Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., April 2015 16 * Table 3-17. Information Returned by CPUID Instruction 17 */ 18 19device cpuid_intel lsbfirst () "ia32 / Intel64 CPUID instruction results" { 20 21 /* 22 *============================================================================ 23 * Basic Information. 24 *============================================================================ 25 */ 26 27 /* 28 * CPUID(0, _) 29 * --------------------------------------------------------------------------- 30 */ 31 datatype basic0 lsbfirst (32) "" { 32 max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information"; 33 vendor0 32 rw "Vendor string part 1"; 34 vendor2 32 rw "Vendor string part 3"; 35 vendor1 32 rw "Vendor string part 2"; 36 }; 37 38 /* 39 * CPUID(1, _) 40 * --------------------------------------------------------------------------- 41 */ 42 constants proc_type width(2) "" { 43 original = 0x00 "Original OEM Processor"; 44 overdrive= 0x01 "Intel OverDrive(r) Processor"; 45 dual = 0x02 "Dual processor (not applicable to Intel486 processors)"; 46 reserved = 0x03 "Intel reserved"; 47 }; 48 49 datatype family lsbfirst(32) "" { 50 /* Version Information: Type, Family, Model, and Stepping ID (see Figure 3-5) */ 51 52 stepping 4 rw "Processor Stepping ID"; 53 model 4 rw "Processor Model"; 54 family 4 rw "Processor Family"; 55 proctype 2 rw "Processor Type"; 56 _ 2 mbz "Reserved"; 57 extmodel 4 rw "Extended Model ID"; 58 extfamily 8 rw "Extended Family ID"; 59 _ 4 mbz "Reserved"; 60 }; 61 62 /* EAX=1 */ 63 64 datatype miscinfo lsbfirst(32) "" { 65 66 brand_idx 8 rw "Brand index"; 67 cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)"; 68 max_log_proc 8 rw "Maximum number of addressable IDs for logical processors"; 69 /*in this physical package. 70 The nearest power-of-2 integer that is not smaller than 71 EBX[23:16] is the number of unique initial APIC IDs 72 reserved for addressing different logical processors in a 73 physical package. */ 74 init_apicid 8 rw "Initial APIC ID"; 75 }; 76 77 datatype features lsbfirst(32) "" { 78 /* Feature Information (see Figure 3-6 and Table 3-19) */ 79 sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). "; 80 pclmulqdq 1 rw "PCLMULQDQ."; 81 dtes64 1 rw "64-bit DS Area"; 82 monitor 1 rw "MONITOR/MWAIT"; 83 ds_cpl 1 rw "CPL Qualified Debug Store. "; 84 vmx 1 rw "Virtual Machine Extensions"; 85 smx 1 rw "Safer Mode Extensions. "; 86 eist 1 rw "Enhanced Intel SpeedStep(r) technology. "; 87 tm2 1 rw "Thermal Monitor 2"; 88 ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)"; 89 cntx_id 1 rw "L1 Context ID. A"; 90 sdbg 1 rw "IA32_DEBUG_INTERFACE MSR "; 91 fma 1 rw "FMA extensions using YMM state."; 92 cmpxchg16b 1 rw "CMPXCHG16B Available"; 93 xtpr 1 rw "xTPR Update Control"; 94 pdcm 1 rw "Perfmon and Debug Capability"; 95 _ 1 mbz ""; 96 pcid 1 rw "Process-context identifiers"; 97 dca 1 rw "ability to prefetch data from a memory mapped device."; 98 sse4_1 1 rw "supports SSE4.1. "; 99 sse4_2 1 rw "supports SSE4.2. "; 100 x2apic 1 rw "supports x2APIC feature"; 101 movbe 1 rw "supports MOVBE instruction"; 102 popcnt 1 rw "supports the POPCNT instruction."; 103 tsc_one 1 rw "local APIC timer supports one-shot operation "; 104 aesni 1 rw " AESNI instruction extensions"; 105 xsave 1 rw " XSAVE/XRSTOR processor "; 106 osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction"; 107 avx 1 rw "AVX instruction extensions"; 108 f16c 1 rw "16-bit floating-point conversion instructions."; 109 rdrand 1 rw "supports RDRAND instruction."; 110 _ 1 mbz ""; 111 112 /* Feature Information (see Figure 3-7 and Table 3-20) */ 113 fpu 1 rw "Floating Point Unit On-Chip"; 114 vme 1 rw "Virtual 8086 Mode Enhancements"; 115 de 1 rw "Debugging Extensions. "; 116 pse 1 rw "Page Size Extension"; 117 tsc 1 rw "Time Stamp Counter."; 118 msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions"; 119 pae 1 rw "Physical Address Extension"; 120 mce 1 rw "Machine Check Exception. "; 121 cx8 1 rw "CMPXCHG8B Instruction."; 122 apic 1 rw "APIC On-Chip. "; 123 _ 1 mbz ""; 124 sep 1 rw "SYSENTER and SYSEXIT Instructions."; 125 mtrr 1 rw "Memory Type Range Registers"; 126 pge 1 rw "Page Global Bit"; 127 mca 1 rw "Machine Check Architecture."; 128 cmov 1 rw "Conditional Move Instructions"; 129 pat 1 rw "Page Attribute Table"; 130 pse36 1 rw "36-Bit Page Size Extension"; 131 psn 1 rw "Processor Serial Number. "; 132 clfsh 1 rw "CLFLUSH Instruction"; 133 _ 1 rw ""; 134 ds 1 rw "Debug Store"; 135 acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities"; 136 mmx 1 rw "Intel MMX Technology"; 137 fxsr 1 rw "FXSAVE and FXRSTOR Instructions"; 138 sse 1 rw "SSE1"; 139 sse2 1 rw "SSE2"; 140 ss 1 rw "Self Snoop"; 141 htt 1 rw "Max APIC IDs reserved field is Valid"; 142 tm 1 rw "Thermal Monitor"; 143 _ 1 mbz ""; 144 pbe 1 rw "Pending Break Enable. "; 145 }; 146 147 148 /* EAX=2 */ 149 datatype cache_info lsbfirst (32) "" { 150 d0 8 "ignored, always 0x01"; 151 d1 8 "Descriptor 01"; 152 d2 8 "Descriptor 02"; 153 d3 7 "Descriptor 03"; 154 v0 1 "Contains valid descriptors"; 155 }; 156 157 /* EAX=3 */ 158 /* not used post P3 */ 159 160 /* 161 *--------------------------------------------------------------------- 162 * Deterministic Cache Parameters EAX=4, ECX=idx 163 *--------------------------------------------------------------------- 164 */ 165 166 constants cache_type "Intel Cache Type values" { 167 cache_type_null = 0x0 "No more caches"; 168 cache_type_data = 0x1 "data cache"; 169 cache_type_instr = 0x2 "Instruction Cache"; 170 cache_type_unified = 0x3 "Unified Cache"; 171 }; 172 173 /* EAX */ 174 datatype cache_info_basic lsbfirst (32) "" { 175 ctype 5 "Cache Type Field"; 176 level 3 "Cache Level (starts at 1)"; 177 selfinit 1 "Self Initializing cache level (does not need SW initialization)"; 178 fullyassoc 1 "Fully Associative cache"; 179 _ 4 "Reserved"; 180 maxlog 12 "Maximum number of addressable IDs for logical processors sharing this cache - 1"; 181 maxphys 6 "Maximum number of addressable IDs for processor cores in the physical package - 1"; 182 }; 183 184 datatype cache_info_ebx lsbfirst (32) "" { 185 coherency 12 "System Coherency Line Size - 1"; 186 partitions 10 "Physical Line partitions - 1"; 187 assoc 10 "Ways of associativity - 1"; 188 }; 189 190 datatype cache_info_ecx lsbfirst (32) "" { 191 num_sets 32 "The number of Sets - 1"; 192 }; 193 194 datatype cache_info_edx lsbfirst (32) "" { 195 wb_inv 1 "Write-Back Invalidate/Invalidate"; 196 inclusive 1 "Cache Inclusiveness"; 197 cpx_idx 1 "Complex Cache Indexing"; 198 _ 29 ""; 199 }; 200 201 /* 202 * CPUID(0x16, _) Processor Frequency Information Leaf 203 * --------------------------------------------------------------------------- 204 */ 205 datatype frequency lsbfirst (32) "" { 206 mhz 16 "Processor frequency in mhz"; 207 _ 16 "Reserved"; 208 }; 209 210 /* 211 *--------------------------------------------------------------------- 212 * Extended Information 213 *--------------------------------------------------------------------- 214 */ 215 216 /* extended topology enumaration leaf, eax = 0xb */ 217 datatype topology_eax lsbfirst (32) "" { 218 x2apic_shift 5 ""; 219 _ 27 ""; 220 }; 221 datatype topology_ebx lsbfirst (32) "" { 222 logical_proc 16 ""; 223 _ 16 ""; 224 }; 225 datatype topology_ecx lsbfirst (32) "" { 226 level_number 8 ""; 227 level_type 8 ""; 228 _ 16 ""; 229 }; 230 datatype topology_edx lsbfirst (32) "" { 231 x2apic 32 ""; 232 }; 233 234 constants topology_level "Intel Cache Type values" { 235 topology_level_invalid = 0x0 "Invalid"; 236 topology_level_smt = 0x1 "SMT"; 237 topology_level_core = 0x2 "Core"; 238 topology_level_package = 0x3 "Package"; 239 }; 240 241 242 /* 243 * CPUID(0x80000001, _) Extended Function CPUID Informatio 244 * --------------------------------------------------------------------------- 245 */ 246 datatype features_ext_edx "" { 247 _ 11 ""; 248 syscall 1 "SYSCALL/SYSRET available in 64-bit mode"; 249 _ 8 ""; 250 nx 1 "Execute Disable Bit available"; 251 _ 5 ""; 252 page1G 1 "1-GByte pages are available if 1"; 253 rdtscp 1 "RDTSCP and IA32_TSC_AUX are available if 1"; 254 _ 1 ""; 255 lm 1 "Intel 64 Architecture available if 1"; 256 _ 2 ""; 257 }; 258 259 260 261 /* 262 * CPUID(0x80000008, _) 263 * --------------------------------------------------------------------------- 264 */ 265 datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" { 266 physical 8 rw "Maximum physical byte address size in bits"; 267 linear 8 rw "Maximum linear byte address size in bits. "; 268 _ 16 mbz "reserved"; 269 }; 270}; 271 272 273 274 275 276 277 278