1/* 2 * Copyright (c) 2016, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* ARM CPUID register formats */ 10 11device cpuid_arm msbfirst () "ARMv7+ CPUID fields" { 12 constants ftr_supp "Feature support" { 13 ftr_ni = 0b0000 "Not implemented"; 14 ftr_i = 0b0001 "Implemented"; 15 }; 16 17 constants jaz_supp "Jazelle extension support" { 18 jaz_ni = 0b0000 "Not implemented"; 19 jaz_it = 0b0001 "Implemented, trivial"; 20 jaz_i = 0b0010 "Implemented, full"; 21 }; 22 23 constants thm_supp "ThumbEE instruction set support" { 24 thm_ni = 0b0000 "Not implemented"; 25 thm_i1 = 0b0001 "Thumb 1"; 26 thm_i2 = 0b0011 "Thumb 2"; 27 }; 28 29 datatype id_pfr0 msbfirst(32) "Processor Feature Register 0" { 30 _ 16 rsvd "Reserved"; 31 state3 4 rw type(ftr_supp) "ThumbEE instruction set support"; 32 state2 4 rw type(jaz_supp) "Jazelle extension support"; 33 state1 4 rw type(thm_supp) "Thumb instruction set support"; 34 state0 4 rw type(ftr_supp) "ARM instruction set support"; 35 }; 36 37 constants mpr_supp "M profile" { 38 mpr_ni = 0b0000 "Not supported"; 39 mpr_i = 0b0010 "Supported"; 40 }; 41 42 constants sec_supp "M profile" { 43 sec_ni = 0b0000 "Not implemented"; 44 sec_i = 0b0001 "Implemented"; 45 sec_ir = 0b0010 "Implemented, with NSACR.RFR"; 46 }; 47 48 datatype id_pfr1 msbfirst(32) "Processor Feature Register 1" { 49 _ 12 rsvd "Reserved"; 50 generic_timer 4 rw type(ftr_supp) "Generic timer extension"; 51 virtualisation 4 rw type(ftr_supp) "Virtualisation extensions"; 52 m_profile 4 rw type(mpr_supp) "M profile"; 53 security 4 rw type(sec_supp) "Security extensions"; 54 prog_model 4 rw type(ftr_supp) "Programmers' model"; 55 }; 56 57 constants midr_impl "Implementer code" { 58 impl_arm = 0x41 "ARM"; 59 impl_dec = 0x44 "DEC"; 60 impl_motorola = 0x4d "Motorola/Freescale"; 61 impl_qualcomm = 0x51 "Qualcomm"; 62 impl_marvell = 0x56 "Marvell"; 63 impl_intel = 0x69 "Intel"; 64 }; 65 66 constants arm_part "ARM part number" { 67 part_a5 = 0xc05 "Cortex-A5"; 68 part_a7 = 0xc07 "Cortex-A7"; 69 part_a8 = 0xc08 "Cortex-A8"; 70 part_a9 = 0xc09 "Cortex-A9"; 71 part_a15 = 0xc0f "Cortex-A15"; 72 part_a17 = 0xc0e "Cortex-A17"; 73 part_a53 = 0xd03 "Cortex-A53"; 74 part_a57 = 0xd07 "Cortex-A57"; 75 part_a72 = 0xd08 "Cortex-A72"; 76 part_a73 = 0xd09 "Cortex-A73"; 77 }; 78 79 datatype midr msbfirst(32) "Main ID Register" { 80 implementer 8 rw type(midr_impl) "Implementer"; 81 variant 4 rw "Variant"; 82 architecture 4 rw "Architecture"; 83 part 12 rw "Primary part number"; 84 revision 4 rw "Revision"; 85 }; 86}; 87