1/* 2 * Copyright (c) 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * cpuid.dev 11 * 12 * DESCRIPTION: ia32 CPU ID instruction results 13 * 14 * See: 15 * Intel Architecture Manual, Volume 2A, pp. 3-163 - ff., August 2007 16 * AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008 17 */ 18 19device cpuid lsbfirst () "ia32 / Intel64 CPUID instruction results" { 20 21 // We define a different address space for each register 22 space eax(i) valuewise "Results in EAX"; 23 space ebx(i) valuewise "Results in EBX"; 24 space ecx(i) valuewise "Results in ECX"; 25 space edx(i) valuewise "Results in EDX"; 26 27 // 28 // Basic CPUID information 29 // 30 31 // 32 // EAX=0x00 33 // 34 35 register max_biv ro eax(0x00) "Maximum input val for basic CPUID info" 36 type(uint32); 37 register vendor0 ro ebx(0x00) "Vendor string part 1" type(uint32); 38 register vendor1 ro edx(0x00) "Vendor string part 2" type(uint32); 39 register vendor2 ro ecx(0x00) "Vendor string part 3" type(uint32); 40 41 // 42 // EAX=0x01 43 // 44 45 register ver_info ro eax(0x01) "Version information" { 46 stepping 4 "Stepping ID"; 47 model 4 "Model ID"; 48 family 4 "Family ID"; 49 proc_type 2 "Processor type (Intel only)"; 50 _ 2 mbz; 51 extmodel 4 "Extended model ID"; 52 extfamily 8 "Extended family ID"; 53 _ 4 mbz; 54 }; 55 56 register brand_ndx ro ebx(0x01) "Brand Index, APIC info" { 57 brand 8 "Brand index"; 58 cflush_sz 8 "CFLUSH line size"; 59 max_log_proc 8 "Max. # logical processors in this package"; 60 init_apic_id 8 "Initial local APIC physical ID"; 61 }; 62 63 register feat_info ro edx(0x01) "Feature information" { 64 fpu_x87 1 "FPU on chip"; 65 vme 1 "Virtual-8086 mode enhancement"; 66 de 1 "Debugging extensions"; 67 pse 1 "Page size extensions"; 68 tsc 1 "Time stamp counter"; 69 msr 1 "RDMSR and WRMSR support"; 70 pae 1 "Physical address extensions"; 71 mce 1 "Machine check exception"; 72 cx8 1 "CMPXCHG8B instruction"; 73 apic 1 "APIC on chip"; 74 _ 1; 75 sep 1 "SYSENTER and SYSEXIT"; 76 mtrr 1 "Memory type range registers"; 77 pge 1 "PTE global bit"; 78 mca 1 "Machine check architecture"; 79 cmov 1 "Conditional move/compare instruction"; 80 pat 1 "Page attribute table"; 81 pse36 1 "Page size extension"; 82 psn 1 "Processor serial number"; 83 clfsh 1 "CFLUSH instruction"; 84 _ 1; 85 ds 1 "Debug store"; 86 acpi 1 "Thermal monitor and clock control"; 87 mmx 1 "MMX technology"; 88 fxsr 1 "FXSAVE / FXRSTOR"; 89 sse 1 "SSE instructions"; 90 sse2 1 "SSE2 instructions"; 91 ss 1 "Self-snoop"; 92 htt 1 "Multi-threading"; 93 tm 1 "Thermal monitor"; 94 _ 1; 95 pbe 1 "Pending break enable"; 96 }; 97 98 register ext_feat_info ro ecx(0x01) "Extended feature information" { 99 sse3 1 "SSE3 extensions"; 100 _ 2; 101 monitor 1 "MONITOR/MWAIT"; 102 ds_cpl 1 "CPL qualified debug store"; 103 vmx 1 "Virtual machine extensions"; 104 smx 1 "Safer mode extensions"; 105 est 1 "Enhanced Intel SpeedStep(tm) technology"; 106 tm2 1 "Thermal monitor 2"; 107 ssse3 1 "Supplemental SSE3 extensions"; 108 cnxt_id 1 "L1 context ID"; 109 _ 2; 110 cmpxchg16b 1 "CMPXCHG16B available"; 111 xtpr_up 1 "xTPR update control"; 112 pdcm 1 "Perfmon and debug capability"; 113 _ 3; 114 sse4_1 1 "SSE4.1"; 115 sse4_2 1 "SSE4.2"; 116 _ 2; 117 popcnt 1 "POPCNT instruction"; 118 _ 8; 119 }; 120 121 // 122 // EAX=0x02 : Cache descriptors (Intel only) 123 // 124 125 // Intel, Table 3.17 126 constants intel_cache_desc "Intel Cache & TLB descriptors" { 127 null_cd = 0x00 "Null descriptor"; 128 itlb_4k_4w_32 = 0x01 "ITLB, 4k pages, 4-way, 32 entries"; 129 itlb_4m_4w_2 = 0x02 "ITLB, 4M pages, 4-way, 2 entries"; 130 dtlb_4k_4w_64 = 0x03 "DTLB, 4k pages, 4-way, 64 entries"; 131 dtlb_4m_4w_8 = 0x04 "DTLB, 4M pages, 4-way, 8 entries"; 132 dtlb1_4m_4w_32 = 0x05 "DTLB1, 4M pages, 4-way, 32 entries"; 133 l1i_8k_4w_32 = 0x06 "L1 Icache, 8k, 4-way, 32b lines"; 134 135 l1i_16k_4w_32 = 0x08 "L1 Icache, 16k, 4-way, 32b lines"; 136 137 l1d_8k_2w_32 = 0x0a "L1 Dcache, 8k, 2-way, 32b lines"; 138 itlb_4m_4w_4 = 0x0b "ITLB, 4M pages, 4-way, 4 entries"; 139 l1d_16k_4w_32 = 0x0c "L1 Dcache, 16k, 4-way, 32b lines"; 140 141 l3_512k_4w_64_2 = 0x22 "L3 cache, 512k, 4-way, 64b lines, 2/sector"; 142 l3_1m_8w_64_2 = 0x23 "L3 cache, 1M, 8-way, 64b lines, 2/sector"; 143 l3_2m_8w_64_2 = 0x25 "L3 cache, 2M, 8-way, 64b lines, 2/sector"; 144 l3_4m_8w_64_2 = 0x29 "L3 cache, 4M, 8-way, 64b lines, 2/sector"; 145 146 l1d_32k_8w_64 = 0x2c "L1 Dcache, 32k, 8-way, 64b lines"; 147 l1i_32k_8w_64 = 0x30 "L1 Icache, 32k, 8-way, 64b lines"; 148 149 no_l2_l3 = 0x40 "No L2 or L3 cache"; 150 151 l2_128k_4w_32 = 0x41 "L2 cache, 128k, 4-way, 32b lines"; 152 l2_256k_4w_32 = 0x42 "L2 cache, 256k, 4-way, 32b lines"; 153 l2_512k_4w_32 = 0x43 "L2 cache, 512k, 4-way, 32b lines"; 154 l2_1m_4w_32 = 0x44 "L2 cache, 1M, 4-way, 32b lines"; 155 l2_2m_4w_32 = 0x45 "L2 cache, 2M, 4-way, 32b lines"; 156 157 l3_4m_4w_64 = 0x46 "L3 cache, 4M, 4-way, 64b lines"; 158 l3_8m_8w_64 = 0x47 "L3 cache, 8M, 8-way, 64b lines"; 159 160 l2_4m_16w_64 = 0x49 "L2 cache, 4M, 16-way, 64b lines"; 161 162 itlb_4k2m4n_64 = 0x50 "ITLB, 4k & 2M or 4M pages, 64 entries"; 163 itlb_4k2m4n_128 = 0x51 "ITLB, 4k & 2M or 4M pages, 128 entries"; 164 itlb_4k2m4n_256 = 0x52 "ITLB, 4k & 2M or 4M pages, 256 entries"; 165 166 dtlb0_4m_4w_16 = 0x56 "DTLB0, 4M pages, 4-way, 16 entries"; 167 dtlb0_4k_4w_16 = 0x57 "DTLB0, 4k pages, 4-way, 16 entries"; 168 169 dtlb_4k4m_64 = 0x5b "DTLB, 4k & 4M pages, 64 entries"; 170 dtlb_4k4m_128 = 0x5c "DTLB, 4k & 4M pages, 128 entries"; 171 dtlb_4k4m_256 = 0x5d "DTLB, 4k & 4M pages, 256 entries"; 172 173 l1d_16k_8w_64 = 0x60 "L1 Dcache, 16k, 8-way, 64b lines"; 174 l1d_8k_4w_64 = 0x66 "L1 Dcache, 8k, 4-way, 64b lines"; 175 l1d_16k_4w_64 = 0x67 "L1 Dcache, 16k, 4-way, 64b lines"; 176 l1d_32k_4w_64 = 0x68 "L1 Dcache, 32k, 4-way, 64b lines"; 177 178 tc_12k_8w = 0x70 "Trace cache, 12k-uop, 8-way"; 179 tc_16k_8w = 0x71 "Trace cache, 16k-uop, 8-way"; 180 tc_32k_8w = 0x72 "Trace cache, 32k-uop, 8-way"; 181 182 l2_1M_4w_64 = 0x78 "L2 cache, 1M, 4-way, 64b lines"; 183 l2_128k_8w_64_2 = 0x79 "L2 cache, 128k, 8-way, 64b lines, 2/sector"; 184 l2_256k_8w_64_2 = 0x7a "L2 cache, 256k, 8-way, 64b lines, 2/sector"; 185 l2_512k_8w_64_2 = 0x7b "L2 cache, 512k, 8-way, 64b lines, 2/sector"; 186 l2_1M_8w_64_2 = 0x7c "L2 cache, 1M, 8-way, 64b lines, 2/sector"; 187 l2_2M_8w_64 = 0x7d "L2 cache, 2M, 8-way, 64b lines"; 188 189 l2_512k_2w_64 = 0x7f "L2 cache, 512k, 2-way, 64b lines"; 190 191 l2_256k_8w_32 = 0x82 "L2 cache, 256k, 8-way, 32b lines"; 192 l2_512k_8w_32 = 0x83 "L2 cache, 512k, 8-way, 32b lines"; 193 l2_1M_8w_32 = 0x84 "L2 cache, 1M, 8-way, 32b lines"; 194 l2_2M_8w_32 = 0x85 "L2 cache, 2M, 8-way, 32b lines"; 195 l2_512k_4w_64 = 0x86 "L2 cache, 512k, 4-way, 64b lines"; 196 l2_1M_8w_64 = 0x87 "L2 cache, 1M, 8-way, 64b lines"; 197 198 itlb_4k_4w_128 = 0xb0 "ITLB, 4k pages, 4-way, 128 entries"; 199 200 dtlb_4k_4w_128 = 0xb3 "DTLB, 4k pages, 4-way, 128 entries"; 201 dtlb1_4k_4w_256 = 0xb4 "DTLB1, 4k pages, 4-way, 256 entries"; 202 203 pref_64 = 0xf0 "64-byte prefetching"; 204 pref_128 = 0xf1 "128-byte prefetching"; 205 }; 206 207/* 208 * Exclude this insane mess for now until we really, really need it. 209 * 210 regtype cache_info "Intel cache/TLB info" { 211 d0 8 type(intel_cache_desc) "Descriptor 0"; 212 d1 8 type(intel_cache_desc) "Descriptor 1"; 213 d2 8 type(intel_cache_desc) "Descriptor 2"; 214 d3 7 type(intel_cache_desc) "Descriptor 3"; 215 valid 1 "Contains valid descriptors"; 216 }; 217 register cache_i_a ro eax(0x02) "Intel cache/TLB info eax" type(cache_info); 218 register cache_i_b ro ebx(0x02) "Intel cache/TLB info ebx" type(cache_info); 219 register cache_i_c ro ecx(0x02) "Intel cache/TLB info ecx" type(cache_info); 220 register cache_i_d ro edx(0x02) "Intel cache/TLB info edx" type(cache_info); 221*/ 222 223 // 224 // EAX=0x03 : Processor serial number (Intel only) 225 // 226 227 register pns0 ro ecx(0x03) "Processor serial no. bits 0-31" type(uint32); 228 register pns1 ro edx(0x03) "Processor serial no. bits 32-63" type(uint32); 229 230 // 231 // EAX=0x04 : Deterministic cache parameters leaf (Intel only) 232 // 233 234 constants intel_cachetype "Intel cache type field" { 235 ct_null = 0 "Null, no more caches"; 236 ct_data = 1 "Data cache"; 237 ct_instruction = 2 "Instruction cache"; 238 ct_unified = 3 "Unified cache"; 239 }; 240 241 space dcpa(i) valuewise "Deterministic cache parameters leaf A"; 242 regarray cache_type ro dcpa(0x00)[4] "Cache type information" { 243 ctf 5 type(intel_cachetype) "Cache type"; 244 level 3 "Cache level (starts at 1)"; 245 self_init 1 "Self initializing"; 246 fully_assoc 1 "Fully associative"; 247 wb_inval 1 "Write-back invalidate/invalidate"; 248 inclusiveness 1 "Cache inclusiveness"; 249 _ 2; 250 max_threads 12 "Max. # threads sharing this cache in package"; 251 max_procs 6 "Max. # processor cores in this package"; 252 }; 253 254 space dcpb(i) valuewise "Deterministic cache parameters leaf B"; 255 regarray cache_pars ro dcpb(0x00)[4] "Cache parameters" { 256 l 12 "System coherency line size (-1)"; 257 p 10 "Physical line partitions (-1)"; 258 w 10 "Ways of associativity (-1)"; 259 }; 260 261 space dcpc(i) valuewise "Deterministic cache parameters leaf C"; 262 regarray num_sets ro dcpc(0x00)[4] "Number of sets" type(uint32); 263 264 // 265 // EAX=0x05 : MONITOR / MWAIT leaf 266 // 267 268 register min_monitor ro eax(0x05) "Smallest monitor-line size)" { 269 sz 16 "Smallest monitor-line size (bytes)"; 270 _ 16 mbz; 271 }; 272 register max_monitor ro ebx(0x05) "Largest monitor-line size)" { 273 sz 16 "Largest monitor-line size (bytes)"; 274 _ 16; 275 }; 276 register mwait_feat ro ecx(0x05) "MONITOR/MWAIT features" { 277 emx 1 "Supports enum. of Monitor/Mwait extensions"; 278 ibe 1 "Supports interrupts as break event"; 279 _ 30; 280 }; 281 register mwait_cstates ro edx(0x05) "sub-C states supported by MWAIT" { 282 c0 4 "# C0 sub-C-states supported"; 283 c1 4 "# C1 sub-C-states supported"; 284 c2 4 "# C2 sub-C-states supported"; 285 c3 4 "# C3 sub-C-states supported"; 286 c4 4 "# C4 sub-C-states supported"; 287 _ 12 mbz; 288 }; 289 290 // 291 // EAX=0x06 : Thermal and Power Management Leaf (Intel only) 292 // 293 294 register tpm_feat ro eax(0x06) "Thermal features" { 295 dts 1 "Digital temperature sensor supported"; 296 ida 1 "Intel dynamic acceleration enabled"; 297 _ 30 mbz; 298 }; 299 register tpm_thresh ro ebx(0x06) "# interrupt thresholds in sensor" { 300 val 4 "# interrupt thresholds in sensor"; 301 _ 28; 302 }; 303 register tpm_hcfc ro ecx(0x06) "Hardware coordination feedback" { 304 en 1 "HCFC present (MCNT/ACNT MSRs)"; 305 _ 31; 306 }; 307 308 // 309 // EAX=0x0a : Architectural Performance Monitoring Leaf (Intel 310 // only) 311 312 register apm_gen ro eax(0x0a) "Gen-purpose perf. counter info" { 313 version 8 "Version ID"; 314 num_counters 8 "# GP perf. counters per logical processor"; 315 width 8 "Bit width of GP perf. counters"; 316 vec_length 8 "EBX bit vector length to enumerate events"; 317 }; 318 register apm_feat ro ebx(0x0a) "Performance monitoring event availability" { 319 cc 1 "Core cycle event"; 320 ir 1 "Instruction retired"; 321 rc 1 "Reference cycles"; 322 llcr 1 "Last-level cache reference"; 323 llcm 1 "Last-level cache miss"; 324 bir 1 "Branch instruction retired"; 325 bmr 1 "Branch mispredict retired"; 326 _ 25 mbz; 327 }; 328 register apm_fixed ro edx(0x0a) "Fixed-function perf. counter infos" { 329 num 5 "# Fixed-function perf. counters"; 330 width 8 "Width of fixed-function perf. counters"; 331 _ 19; 332 }; 333 334 // 335 // Extended CPU information 336 // 337 338 register ext_biv ro eax(0x80000000) "Max input val for ext. CPUID info" 339 type(uint32); 340 register evendor0 ro ebx(0x80000000) "Ext. Vendor string pt 1" type(uint32); 341 register evendor1 ro edx(0x80000000) "Ext. Vendor string pt 2" type(uint32); 342 register evendor2 ro ecx(0x80000000) "Ext. Vendor string pt 3" type(uint32); 343 344 // Mostly AMD only 345 register brandid ro ebx(0x80000001) "Brand ID identifier" { 346 id 16 "Extended brand ID"; 347 _ 12; 348 pkgtype 4 "Package type"; 349 }; 350 register ext_featc ro ecx(0x80000001) "Extend misc. features 1" { 351 lahfsahf 1 "LAHF & SAHF support in 64-bit mode"; 352 cmplegacy 1 "Core multiprocessing legacy mode"; 353 svm 1 "Secure virtual machine"; 354 extapicspace 1 "Extended APIC space"; 355 altmovcr8 1 "LOCK MOV CR0 means MOV CR8"; 356 abm 1 "Advanced bit manipulation"; 357 sse4a 1 "EXTRQ/INSERTQ/MOVNTSS/MOVNTSD support"; 358 misalignsse 1 "Misaligned SSE mode"; 359 pref3dnow 1 "PREFETCH/PREFETCHW support"; 360 osvw 1 "OS visible workaround"; 361 ibs 1 "Instruction-based sampling"; 362 sse5 1 "SSE 5 instruction support"; 363 skinit 1 "SKINIT/STGI supported"; 364 wdt 1 "Watchdog timer support"; 365 _ 18; 366 }; 367 register ext_featd ro edx(0x80000001) "Extend misc. features 2" { 368 _ 11; 369 syscallsysret 1 "SYSCALL/SYSRET available in 64-bit mode"; 370 _ 8; 371 nx 1 "No-execute page protection"; 372 _ 1; 373 mmxext 1 "AMD extensions to MMX instructions"; 374 _ 2; 375 ffxsr 1 "FFXSR instruction optimizations"; 376 page1fb 1 "1-GB large page support"; 377 rdtscp 1 "RDTSCP instruction"; 378 _ 1; 379 longmode 1 "Long mode / Intel64 available"; 380 i3dnowext 1 "AMD extensions to 3DNow! instructions"; 381 i3dnow 1 "3DNow! instructions"; 382 }; 383 384 register brand0 ro eax(0x80000002) "Brand string contd." type(uint32); 385 register brand1 ro ebx(0x80000002) "Brand string contd." type(uint32); 386 register brand2 ro ecx(0x80000002) "Brand string contd." type(uint32); 387 register brand3 ro edx(0x80000002) "Brand string contd." type(uint32); 388 389 register brand4 ro eax(0x80000003) "Brand string contd." type(uint32); 390 register brand5 ro ebx(0x80000003) "Brand string contd." type(uint32); 391 register brand6 ro ecx(0x80000003) "Brand string contd." type(uint32); 392 register brand7 ro edx(0x80000003) "Brand string contd." type(uint32); 393 394 register brand8 ro eax(0x80000004) "Brand string contd." type(uint32); 395 register brand9 ro ebx(0x80000004) "Brand string contd." type(uint32); 396 register branda ro ecx(0x80000004) "Brand string contd." type(uint32); 397 register brandb ro edx(0x80000004) "Brand string contd." type(uint32); 398 399 // 400 // EAX=0x80000005 : L1 cache and TLB identifiers (AMD only) 401 // 402 regtype amd_tlbinfo1 "AMD TLB information" { 403 itlb_sz 8 "Number of instruction TLB entries"; 404 itlb_asc 8 "Instruction TLB associativity"; 405 dtlb_sz 8 "Number of data DTLB entries"; 406 dtlb_asc 8 "Data TLB associativity"; 407 }; 408 regtype amd_cacheinfo1 "AMD cache information" { 409 linesize 8 "line size"; 410 lpt 8 "lines per tag"; 411 assoc 8 "associativity"; 412 size 8 "size in Kb"; 413 }; 414 register l1_24m ro eax(0x80000005) "AMD L1 TLB info for 2MB/4MB pages" 415 type(amd_tlbinfo1); 416 register l1_4k ro ebx(0x80000005) "AMD L1 TLB info for 4k pages" 417 type(amd_tlbinfo1); 418 register l1_dci ro ecx(0x80000005) "AMD L1 DCache info" 419 type(amd_cacheinfo1); 420 register l1_ici ro edx(0x80000005) "AMD L1 ICache info" 421 type(amd_cacheinfo1); 422 423 // 424 // EAX=0x80000006 : L2 cache and TLB identifiers (mostly AMD only) 425 // 426 regtype amd_tlbinfo23 "AMD TLB information" { 427 itlb_sz 12 "Number of instruction TLB entries"; 428 itlb_asc 4 "Instruction TLB associativity"; 429 dtlb_sz 12 "Number of data DTLB entries"; 430 dtlb_asc 4 "Data TLB associativity"; 431 }; 432 regtype amd_cacheinfo23 "AMD cache information" { 433 linesize 8 "line size"; 434 lpt 4 "lines per tag"; 435 assoc 4 "associativity"; 436 size 16 "size in Kb"; 437 }; 438 register l2_24m ro eax(0x80000006) "AMD L2 TLB info for 2MB/4MB pages" 439 type(amd_tlbinfo23); 440 register l2_4k ro ebx(0x80000006) "AMD L2 TLB info for 4k pages" 441 type(amd_tlbinfo23); 442 register l2_ci ro ecx(0x80000006) "AMD L2 cache info" 443 type(amd_cacheinfo23); 444 register l3_ci ro edx(0x80000006) "AMD L3 cache info" 445 type(amd_cacheinfo23); 446 447 // 448 // EAX=0x80000007 : Advanced Power Management (AMD only) 449 // 450 451 register amd_apm ro edx(0x80000007) "AMD Advanced Power Mgmt" { 452 ts 1 "Temperature sensor"; 453 fid 1 "Frequency ID control"; 454 vid 1 "Voltage ID control"; 455 ttp 1 "THERMTRIP"; 456 tm 1 "Hardware thermal control"; 457 stc 1 "Software thermal control"; 458 Mhz100steps 1 "100MHz multiplier control"; 459 hpwstate 1 "Hardware P-State control"; 460 tscinvariant 1 "TSC rate invariant"; 461 _ 23; 462 }; 463 464 // 465 // EAX=0x80000008 : Address size and physical core count 466 // 467 468 register addr_size ro eax(0x80000008) "Address size" { 469 phys 8 "Max physical byte address size in bits"; 470 linear 8 "Max linear byte address size in bits"; 471 guest 8 "Max guest physical byte address size in bits"; 472 _ 8; 473 }; 474 // AMD only 475 register core_count ro ecx(0x80000008) "Core count" { 476 nc 8 "Number of CPU cores -1 "; 477 _ 4; 478 apiccoreidsz 4 "APIC core ID size in bits"; 479 _ 16; 480 }; 481 482 // 483 // EAX=0x8000000A : SVM revision/feature identification (AMD only) 484 // 485 486 register svmrev ro eax(0x8000000A) "Secure Virtual Machine rev." { 487 rev 8 "SVM revision number"; 488 _ 24; 489 }; 490 register nasid ro ebx(0x8000000A) "# Addr. space identifiers" type(uint32); 491 register svmfeat ro edx(0x8000000A) "SVM features" { 492 np 1 "Nested paging"; 493 lbrvirt 1 "LBR virtualization"; 494 svml 1 "SVM lock"; 495 nrips 1 "NRIP save"; 496 _ 5; 497 ssse3sse5dis 1 "SSSE3 and SSE5 opcode set disable"; 498 _ 22; 499 }; 500 501 // 502 // EAX=0x80000019 : TLB 1GB page identifiers (AMD only) 503 // 504 505 register l1_1G ro eax(0x80000019) "AMD L1 TLB info for 1GB pages" 506 type(amd_tlbinfo23); 507 register l2_1G ro ebx(0x80000019) "AMD L2 TLB info for 1GB pages" 508 type(amd_tlbinfo23); 509 510 // 511 // EAX=0x8000001A : Performance optimization identifiers (AMD only) 512 // 513 514 register opt_id ro eax(0x8000001A) "Perf. optimization identifiers" { 515 fp128 1 "128-bit SSE has full-width execution"; 516 movu 1 "MOVU SSE instructions faster than MOVL"; 517 _ 30; 518 }; 519}; 520 521 522 523 524 525 526 527