1/* 2 * Copyright (c) 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * audio_nbm.dev 11 * 12 * DESCRIPTION: Intel Native Audio Bus Master registers 13 * 14 * Numbers in comments refer to the Intel 631xESB/632xESB I/O 15 * Controller Hub Datasheet 16 */ 17 18device audio_nbm msbfirst ( io base ) "Native Audio Bus Master" { 19 20 // 19.2.1 21 regtype bdbar "Buffer descriptor base address" { 22 a 29 "Address [31:3]"; 23 _ 3 mbz; 24 }; 25 26 // 19.2.4 27 regtype sr "Status" { 28 _ 11; 29 fifoe 1 rwc "FIFO error"; 30 bcis 1 rwc "Buffer completion interrupt status"; 31 lvbci 1 rwc "Last valid buffer completion interrupt"; 32 celv 1 ro "Current equals last valid"; 33 dch 1 ro "DMA controller halted"; 34 }; 35 36 // 19.2.7 37 regtype cr "Control" { 38 _ 3; 39 ioce 1 "Interrupt on completion enable"; 40 feie 1 "FIFO error interrupt enable"; 41 lvbie 1 "Last valid buffer interrupt enable"; 42 rr 1 "Reset registers"; 43 rpbm 1 "Run/pause bus master"; 44 }; 45 46 // 19.2.8 47 constants pcm_om "PCM output mode" { 48 b16 = 0b00 "16 bit audio"; 49 b20 = 0b01 "20 bit audio"; 50 }; 51 constants pcm_cm "PCM channel mode" { 52 c2 = 0b00 "2 channels"; 53 c4 = 0b01 "4 channels"; 54 c6 = 0b10 "6 channels"; 55 }; 56 57 register glob_cnt rw io(base, 0x2c) "Global control" { 58 ssm 2 "S/PDIF slot map"; 59 _ 6; 60 pom 2 type(pcm_om) "PCM out mode"; 61 pcm46 2 type(pcm_cm) "PCM channel mode"; 62 _ 13; 63 s2ie 1 "ACZ_SDIN2 interrupt enable"; 64 s1ie 1 "ACZ_SDIN1 interrupt enable"; 65 s0ie 1 "ACZ_SDIN0 interrupt enable"; 66 ldo 1 "AC-LINK shut off"; 67 awr 1 "AC97 warm reset"; 68 acr 1 "AC97 cold reset"; 69 gie 1 "GPI interrupt enable"; 70 }; 71 72 73 // 19.2.9 74 register glob_sta io(base, 0x30) "Global status" { 75 _ 2; 76 s2ri 1 rwc "ACZ_SDIN2 resume interrupt"; 77 s2cr 1 ro "ACZ_SDIN2 codec ready"; 78 bcs 1 ro "Bit clock stopped"; 79 spint 1 ro "S/PDIF interrupt"; 80 p2int 1 ro "PCM in 2 interrupt"; 81 m2int 1 ro "Microphone 2 in interrupt"; 82 scap 2 ro "Sample capabilities"; 83 mcap 2 ro "Multichannel capabilities"; 84 _ 2; 85 md3 1 rw "Power down semaphore for modem"; 86 ad3 1 rw "Power down semaphore for audio"; 87 rcs 1 rwc "Read completion status"; 88 slot12 3 ro "Display bits 1-3 of most recent slot 12"; 89 s1ri 1 rwc "ACZ_SDIN1 resume interrupt"; 90 s0ri 1 rwc "ACZ_SDIN0 resume interrupt"; 91 s1cr 1 ro "ACZ_SDIN1 codec ready"; 92 s0cr 1 ro "ACZ_SDIN0 codec ready"; 93 mint 1 ro "Microphone in interrupt"; 94 point 1 ro "PCM out interrupt"; 95 piint 1 ro "PCM in interrupt"; 96 _ 2; 97 moint 1 ro "Modem out interrupt"; 98 miint 1 ro "Modem in interrupt"; 99 gsci 1 rwc "GPI status change interrupt"; 100 }; 101 102 // 19.2.10 103 register cas rw io(base, 0x34) "Codec access semaphore" { 104 _ 7; 105 s 1 "read to set"; 106 }; 107 108 // 19.2.11 109 register sdm io(base, 0x80) "SDATA_IN map" { 110 di2l 2 rw "PCM in 2, Mic in 2 data in line"; 111 di1l 2 rw "PCM in 1, Mic in 1 data in line"; 112 se 1 rw "Steer enable"; 113 _ 1; 114 ldi 2 ro "Last codec read data input"; 115 }; 116 117 // 19.2 118 register pi_bdbar rw io(base, 0x00) "PCM in buffer desc. list base" type(bdbar); 119 register pi_civ ro io(base, 0x04) "PCM in cur. index value" type(uint8); 120 register pi_lvi rw io(base, 0x05) "PCM in last valud index" type(uint8); 121 register pi_sr io(base, 0x06) "PCM in status" type(sr); 122 register pi_picb ro io(base, 0x08) "PCM in pos. in cur. buffer" type(uint16); 123 register pi_piv ro io(base, 0x0a) "PCM in prefetched index val" type(uint8); 124 register pi_cr rw io(base, 0x0b) "PCM in control" type(cr); 125 126 register po_bdbar rw io(base, 0x10) "PCM out buffer desc. list base" type(bdbar); 127 register po_civ ro io(base, 0x14) "PCM out cur. index value" type(uint8); 128 register po_lvi rw io(base, 0x15) "PCM out last valud index" type(uint8); 129 register po_sr io(base, 0x16) "PCM out status" type(sr); 130 register po_picb ro io(base, 0x18) "PCM out pos. in cur. buffer" type(uint16); 131 register po_piv ro io(base, 0x1a) "PCM out prefetched index val" type(uint8); 132 register po_cr rw io(base, 0x1b) "PCM out control" type(cr); 133 134 register mc_bdbar rw io(base, 0x20) "Mic in buffer desc. list base" type(bdbar); 135 register mc_civ ro io(base, 0x24) "Mic in cur. index value" type(uint8); 136 register mc_lvi rw io(base, 0x25) "Mic in last valud index" type(uint8); 137 register mc_sr io(base, 0x26) "Mic in status" type(sr); 138 register mc_picb ro io(base, 0x28) "Mic in pos. in cur. buffer" type(uint16); 139 register mc_piv ro io(base, 0x2a) "Mic in prefetched index val" type(uint8); 140 register mc_cr rw io(base, 0x2b) "Mic in control" type(cr); 141 142 register mc2_bdbar rw io(base, 0x40) "Mic 2 buffer desc. list base" type(bdbar); 143 register mc2_civ ro io(base, 0x44) "Mic 2 cur. index value" type(uint8); 144 register mc2_lvi rw io(base, 0x45) "Mic 2 last valud index" type(uint8); 145 register mc2_sr io(base, 0x46) "Mic 2 status" type(sr); 146 register mc2_picb ro io(base, 0x48) "Mic 2 pos. in cur. buffer" type(uint16); 147 register mc2_piv ro io(base, 0x4a) "Mic 2 prefetched index val" type(uint8); 148 register mc2_cr rw io(base, 0x4b) "Mic 2 control" type(cr); 149 150 register pi2_bdbar rw io(base, 0x50) "PCM in 2 buf desc. list base" type(bdbar); 151 register pi2_civ ro io(base, 0x54) "PCM in 2 cur. index value" type(uint8); 152 register pi2_lvi rw io(base, 0x55) "PCM in 2 last valud index" type(uint8); 153 register pi2_sr io(base, 0x56) "PCM in 2 status" type(sr); 154 register pi2_picb ro io(base, 0x58) "PCM in 2 pos. in cur. buf" type(uint16); 155 register pi2_piv ro io(base, 0x5a) "PCM in 2 pref. index val" type(uint8); 156 register pi2_cr rw io(base, 0x5b) "PCM in 2 control" type(cr); 157 158 register sp_bdbar rw io(base, 0x60) "S/PDIF buf desc. list base" type(bdbar); 159 register sp_civ ro io(base, 0x64) "S/PDIF cur. index value" type(uint8); 160 register sp_lvi rw io(base, 0x65) "S/PDIF last valud index" type(uint8); 161 register sp_sr io(base, 0x66) "S/PDIF status" type(sr); 162 register sp_picb ro io(base, 0x68) "S/PDIF pos. in cur. buf" type(uint16); 163 register sp_piv ro io(base, 0x6a) "S/PDIF pref. index val" type(uint8); 164 register sp_cr rw io(base, 0x6b) "S/PDIF control" type(cr); 165 166}; 167 168 169