1/* 2 * Copyright (c) 2017 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * NOTE: This file has been automatically generated based on the XML files 12 * provided by ARM. 13 * 14 * Download from: 15 * https://developer.arm.com/products/architecture/a-profile/exploration-tools 16 * 17 * Based on version: SysReg_v82A_xml-00bet3.1.tar.gz 18 */ 19 20device armv8 msbfirst () "ARMv8 architecture definitions" { 21 22space armv8_sysreg(name) registerwise "System registers"; 23space cache_ctrl(name) registerwise "Cache control register"; 24 25constants MAIR_Mem width(2) "Shareability" { 26 MAIR_MEM_Write_Through_Transient = 0b00; 27 MAIR_MEM_NonCache = 0b01; 28 MAIR_MEM_Write_Through_Non_Transient = 0b10; 29 MAIR_MEM_Write_Back_Non_Transient = 0b11; 30}; 31 32constants MAIR_Dev width(2) "Shareability" { 33 MAIR_DEV_nGnRnE = 0b00; 34 MAIR_DEV_nGnRE = 0b01; 35 MAIR_DEV_nGRE = 0b10; 36 MAIR_DEV_GRE = 0b11; 37}; 38 39constants shareability width(2) "Shareability" { 40 non_shareable = 0b00 "Non-shareable"; 41 outer_shareable = 0b10 "Outer Shareable"; 42 inner_shareable = 0b11 "Inner Shareable"; 43}; 44 45constants cacheability width(2) "Cacheability" { 46 non_cacheable = 0b00 "Normal memory, Outer Non-cacheable"; 47 WbRaWa_cache = 0b01 "Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable"; 48 WtRanWa_cache = 0b10 "Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable"; 49 WbRanWa_cache = 0b11 "Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable"; 50}; 51 52constants ASID_size width(1) "ASID size" { 53 bit_8 = 0b0 "8 bit ASID size"; 54 bit_16 = 0b1 "16 bit ASID size"; 55}; 56 57constants granule width(2) "Granule size" { 58 KB_4 = 0b00; 59 KB_64 = 0b01; 60 KB_16 = 0b10; 61}; 62 63constants endianness width(1) "Endianness configuration" { 64 little = 0b0 "Little endian"; 65 big = 0b1 "Big endian"; 66}; 67 68constants fpen width(2) "Endianness configuration" { 69 fpen_trap_any = 0b00 "Trap any FP and SIMD instructions in EL0 or EL1"; 70 fpen_trap_el0 = 0b01 "Trap any FP and SIMD in EL0 to EL21"; 71 fpen_trap_el1 = 0b10 "Trap any FP and SIMD instructions in EL0 or EL1"; 72 fpen_trap_none = 0b11 "Does not cause any instruction to be trapped."; 73}; 74 75constants ID_FEATURE width(4) "Feature implemented" { 76 ID_FEATURE_IMPLEMENTED = 0b0000; 77 ID_FEATURE_NOT_IMPLEMENTED = 0b1111; 78}; 79 80constants EL_IMPLEMENTED width(4) "Feature implemented" { 81 ID_EL_NOT_IMPLEMENTED = 0b0000; 82 ID_EL_AARCH64_ONLY = 0b0001; 83 ID_EL_AARCH32_OR_64 = 0b0010; 84}; 85 86 87register MAIR_EL1 rw armv8_sysreg(MAIR_EL1) "Memory Attribute Indirection Register (EL1)" { 88 attr7_mem 2 type(MAIR_Mem) "Memory / Write Back"; 89 attr7_mem_rw 2 "Read/Write allocate policy"; 90 attr7_dev 2 type(MAIR_Dev) "Device memory type"; 91 _ 2 mbz; 92 attr6_mem 2 type(MAIR_Mem) "Memory / Write Back"; 93 attr6_mem_rw 2 "Read/Write allocate policy"; 94 attr6_dev 2 type(MAIR_Dev) "Device memory type"; 95 _ 2 mbz; 96 attr5_mem 2 type(MAIR_Mem) "Memory / Write Back"; 97 attr5_mem_rw 2 "Read/Write allocate policy"; 98 attr5_dev 2 type(MAIR_Dev) "Device memory type"; 99 _ 2 mbz; 100 attr4_mem 2 type(MAIR_Mem) "Memory / Write Back"; 101 attr4_mem_rw 2 "Read/Write allocate policy"; 102 attr4_dev 2 type(MAIR_Dev) "Device memory type"; 103 _ 2 mbz; 104 attr3_mem 2 type(MAIR_Mem) "Memory / Write Back"; 105 attr3_mem_rw 2 "Read/Write allocate policy"; 106 attr3_dev 2 type(MAIR_Dev) "Device memory type"; 107 _ 2 mbz; 108 attr2_mem 2 type(MAIR_Mem) "Memory / Write Back"; 109 attr2_mem_rw 2 "Read/Write allocate policy"; 110 attr2_dev 2 type(MAIR_Dev) "Device memory type"; 111 _ 2 mbz; 112 attr1_mem 2 type(MAIR_Mem) "Memory / Write Back"; 113 attr1_mem_rw 2 "Read/Write allocate policy"; 114 attr1_dev 2 type(MAIR_Dev) "Device memory type"; 115 _ 2 mbz; 116 attr0_mem 2 type(MAIR_Mem) "Memory / Write Back"; 117 attr0_mem_rw 2 "Read/Write allocate policy"; 118 attr0_dev 2 type(MAIR_Dev) "Device memory type"; 119 _ 2 mbz; 120}; 121 122register MAIR_EL2 rw armv8_sysreg(MAIR_EL2) "Memory Attribute Indirection Register (EL2)" { 123 attr7_mem 2 type(MAIR_Mem) "Memory / Write Back"; 124 attr7_mem_rw 2 "Read/Write allocate policy"; 125 attr7_dev 2 type(MAIR_Dev) "Device memory type"; 126 _ 2 mbz; 127 attr6_mem 2 type(MAIR_Mem) "Memory / Write Back"; 128 attr6_mem_rw 2 "Read/Write allocate policy"; 129 attr6_dev 2 type(MAIR_Dev) "Device memory type"; 130 _ 2 mbz; 131 attr5_mem 2 type(MAIR_Mem) "Memory / Write Back"; 132 attr5_mem_rw 2 "Read/Write allocate policy"; 133 attr5_dev 2 type(MAIR_Dev) "Device memory type"; 134 _ 2 mbz; 135 attr4_mem 2 type(MAIR_Mem) "Memory / Write Back"; 136 attr4_mem_rw 2 "Read/Write allocate policy"; 137 attr4_dev 2 type(MAIR_Dev) "Device memory type"; 138 _ 2 mbz; 139 attr3_mem 2 type(MAIR_Mem) "Memory / Write Back"; 140 attr3_mem_rw 2 "Read/Write allocate policy"; 141 attr3_dev 2 type(MAIR_Dev) "Device memory type"; 142 _ 2 mbz; 143 attr2_mem 2 type(MAIR_Mem) "Memory / Write Back"; 144 attr2_mem_rw 2 "Read/Write allocate policy"; 145 attr2_dev 2 type(MAIR_Dev) "Device memory type"; 146 _ 2 mbz; 147 attr1_mem 2 type(MAIR_Mem) "Memory / Write Back"; 148 attr1_mem_rw 2 "Read/Write allocate policy"; 149 attr1_dev 2 type(MAIR_Dev) "Device memory type"; 150 _ 2 mbz; 151 attr0_mem 2 type(MAIR_Mem) "Memory / Write Back"; 152 attr0_mem_rw 2 "Read/Write allocate policy"; 153 attr0_dev 2 type(MAIR_Dev) "Device memory type"; 154 _ 2 mbz; 155}; 156 157register MAIR_EL3 rw armv8_sysreg(MAIR_EL3) "Memory Attribute Indirection Register (EL3)" { 158 attr7_mem 2 type(MAIR_Mem) "Memory / Write Back"; 159 attr7_mem_rw 2 "Read/Write allocate policy"; 160 attr7_dev 2 type(MAIR_Dev) "Device memory type"; 161 _ 2 mbz; 162 attr6_mem 2 type(MAIR_Mem) "Memory / Write Back"; 163 attr6_mem_rw 2 "Read/Write allocate policy"; 164 attr6_dev 2 type(MAIR_Dev) "Device memory type"; 165 _ 2 mbz; 166 attr5_mem 2 type(MAIR_Mem) "Memory / Write Back"; 167 attr5_mem_rw 2 "Read/Write allocate policy"; 168 attr5_dev 2 type(MAIR_Dev) "Device memory type"; 169 _ 2 mbz; 170 attr4_mem 2 type(MAIR_Mem) "Memory / Write Back"; 171 attr4_mem_rw 2 "Read/Write allocate policy"; 172 attr4_dev 2 type(MAIR_Dev) "Device memory type"; 173 _ 2 mbz; 174 attr3_mem 2 type(MAIR_Mem) "Memory / Write Back"; 175 attr3_mem_rw 2 "Read/Write allocate policy"; 176 attr3_dev 2 type(MAIR_Dev) "Device memory type"; 177 _ 2 mbz; 178 attr2_mem 2 type(MAIR_Mem) "Memory / Write Back"; 179 attr2_mem_rw 2 "Read/Write allocate policy"; 180 attr2_dev 2 type(MAIR_Dev) "Device memory type"; 181 _ 2 mbz; 182 attr1_mem 2 type(MAIR_Mem) "Memory / Write Back"; 183 attr1_mem_rw 2 "Read/Write allocate policy"; 184 attr1_dev 2 type(MAIR_Dev) "Device memory type"; 185 _ 2 mbz; 186 attr0_mem 2 type(MAIR_Mem) "Memory / Write Back"; 187 attr0_mem_rw 2 "Read/Write allocate policy"; 188 attr0_dev 2 type(MAIR_Dev) "Device memory type"; 189 _ 2 mbz; 190}; 191 192/* Source: AArch64-osdlr_el1.xml */ 193register OSDLR_EL1 rw armv8_sysreg(OSDLR_EL1) "OS Double Lock Register" { 194 _ 31 mbz "Reserved, RES0."; 195 DLK 1 "OS Double Lock control bit. Possible values are:"; 196}; 197 198/* Source: AArch64-contextidr_el1.xml */ 199register CONTEXTIDR_EL1 rw armv8_sysreg(CONTEXTIDR_EL1) "Context ID Register (EL1)" { 200 PROCID 32 "Process Identifier. This field must be programmed with a unique value that identifies the current process."; 201}; 202 203/* Source: AArch64-tpidr_el0.xml */ 204register TPIDR_EL0 rw armv8_sysreg(TPIDR_EL0) "EL0 Read/Write Software Thread ID Register" type(uint64); 205 206/* Source: AArch64-cntvoff_el2.xml */ 207register CNTVOFF_EL2 rw armv8_sysreg(CNTVOFF_EL2) "Counter-timer Virtual Offset register" type(uint64); 208 209/* Source: AArch64-rmr_el1.xml */ 210register RMR_EL1 rw armv8_sysreg(RMR_EL1) "Reset Management Register (EL1)" { 211 _ 30 mbz "Reserved, RES0."; 212 RR 1 "Reset Request. Setting this bit to 1 requests a Warm reset."; 213 AA64 1 "When EL1 can use AArch32, determines which Execution state the PE boots into after a Warm reset:"; 214}; 215 216/* Source: AArch64-ifsr32_el2.xml */ 217register IFSR32_EL2 rw armv8_sysreg(IFSR32_EL2) "Instruction Fault Status Register (EL2)" { 218 _ 15 mbz "Reserved, RES0."; 219 FnV 1 "FAR not Valid, for a Synchronous external abort other than a Synchronous external abort on a translation table walk."; 220 _ 3 mbz "Reserved, RES0."; 221 ExT 1 "External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of external aborts."; 222 _ 1 mbz "Reserved, RES0."; 223 FS_hi 1 "See FS[3:0], bits [3:0] for description of the FS field."; 224 LPAE 1 "On taking a Data Abort exception, this bit is set as follows:"; 225 _ 5 mbz "Reserved, RES0."; 226 FS_lo 4 "Fault status bits. Interpreted with bit [10]. Possible values of FS[4:0] are:"; 227}; 228 229/* Source: AArch64-far_el2.xml */ 230register FAR_EL2 rw armv8_sysreg(FAR_EL2) "Fault Address Register (EL2)" type(uint64); 231 232/* Source: AArch64-cnthp_tval_el2.xml */ 233register CNTHP_TVAL_EL2 rw armv8_sysreg(CNTHP_TVAL_EL2) "Counter-timer Hypervisor Physical Timer TimerValue register" { 234 TimerValue 32 "The TimerValue view of the EL2 physical timer."; 235}; 236 237/* Source: AArch64-hstr_el2.xml */ 238register HSTR_EL2 rw armv8_sysreg(HSTR_EL2) "Hypervisor System Trap Register" { 239 _ 16 mbz "Reserved, RES0."; 240 T 16 "Fields T14 and T4 are RES0."; 241}; 242 243/* Source: AArch64-icc_ctlr_el1.xml */ 244register ICC_CTLR_EL1 rw armv8_sysreg(ICC_CTLR_EL1) "Interrupt Controller Control Register (EL1)" { 245 _ 16 mbz "Reserved, RES0."; 246 A3V 1 "Affinity 3 Valid. Read-only and writes are ignored. Possible values are:"; 247 SEIS 1 "SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports local generation of SEIs:"; 248 IDbits 3 "Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:"; 249 PRIbits 3 "Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one."; 250 _ 1 mbz "Reserved, RES0."; 251 PMHE 1 "Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution:"; 252 _ 4 mbz "Reserved, RES0."; 253 EOImode 1 "EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt:"; 254 CBPR 1 "Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts:"; 255}; 256 257/* Source: AArch64-ich_ap0rn_el2.xml */ 258regtype ICH_AP0R_EL2_type "Interrupt Controller Hyp Active Priorities Group 0 Registers" { 259 P 32 "Provides the access to the virtual active priorities for Group 0 interrupts. Possible values of each bit are:"; 260}; 261register ICH_AP0R0_EL2 rw armv8_sysreg(ICH_AP0R0_EL2) "Interrupt Controller Hyp Active Priorities Group 0 Registers" type(ICH_AP0R_EL2_type); 262register ICH_AP0R1_EL2 rw armv8_sysreg(ICH_AP0R1_EL2) "Interrupt Controller Hyp Active Priorities Group 0 Registers" type(ICH_AP0R_EL2_type); 263register ICH_AP0R2_EL2 rw armv8_sysreg(ICH_AP0R2_EL2) "Interrupt Controller Hyp Active Priorities Group 0 Registers" type(ICH_AP0R_EL2_type); 264 265/* Source: AArch64-cptr_el2.xml */ 266register CPTR_EL2 rw armv8_sysreg(CPTR_EL2) "Architectural Feature Trap Register (EL2)" { 267 TCPAC 1 "Traps Non-secure EL1 accesses to CPACR_EL1 or CPACR to EL2, from both Execution states."; 268 _ 10 mbz "Reserved, RES0."; 269 TTA 1 "Traps Non-secure System register accesses to all implemented trace registers to EL2, from both Execution states."; 270 _ 6 mbz "Reserved, RES0."; 271 _ 2 mb1 "Reserved, RES1."; 272 _ 1 mbz "Reserved, RES0."; 273 TFP 1 "Traps Non-secure accesses to SVE, Advanced SIMD and floating-point functionality to EL2, from both Execution states."; 274 _ 1 mb1 "Reserved, RES1."; 275 TZ 1 "Present only if is implemented."; 276 _ 8 mb1 "Reserved, RES1."; 277}; 278 279/* Source: AArch64-dbgdtr_el0.xml */ 280register DBGDTR_EL0 rw armv8_sysreg(DBGDTR_EL0) "Debug Data Transfer Register, half-duplex" { 281 HighWord 32 "Writes to this register set DTRRX to the value in this field and do not change RXfull."; 282 LowWord 32 "Writes to this register set DTRTX to the value in this field and set TXfull to 1."; 283}; 284 285/* Source: AArch64-mdrar_el1.xml */ 286register MDRAR_EL1 ro armv8_sysreg(MDRAR_EL1) "Monitor Debug ROM Address Register" { 287 _ 12 mbz "Reserved, RES0."; 288 ROMADDR_hi 4 "Extension to ROMADDR[47:12]. See ROMADDR[47:12] for more details."; 289 ROMADDR_lo 36 "Bits[47:12] of the ROM table physical address."; 290 _ 10 mbz "Reserved, RES0."; 291 Valid 2 "This field indicates whether the ROM Table address is valid. The permitted values of this field are:"; 292}; 293 294/* Source: AArch64-afsr0_el3.xml */ 295register AFSR0_EL3 rw armv8_sysreg(AFSR0_EL3) "Auxiliary Fault Status Register 0 (EL3)" { 296 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 297}; 298 299/* Source: AArch64-far_el1.xml */ 300register FAR_EL1 rw armv8_sysreg(FAR_EL1) "Fault Address Register (EL1)" type(uint64); 301 302/* Source: AArch64-id_isar4_el1.xml */ 303register ID_ISAR4_EL1 ro armv8_sysreg(ID_ISAR4_EL1) "AArch32 Instruction Set Attribute Register 4" { 304 SWP_frac 4 "Indicates support for the memory system locking the bus for SWP or SWPB instructions. Defined values are:"; 305 PSR_M 4 "Indicates the implemented M profile instructions to modify the PSRs. Defined values are:"; 306 SynchPrim_frac 4 "Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions. Possible values are:"; 307 Barrier 4 "Indicates the implemented Barrier instructions in the A32 and T32 instruction sets. Defined values are:"; 308 SMC 4 "Indicates the implemented SMC instructions. Defined values are:"; 309 Writeback 4 "Indicates the support for Writeback addressing modes. Defined values are:"; 310 WithShifts 4 "Indicates the support for instructions with shifts. Defined values are:"; 311 Unpriv 4 "Indicates the implemented unprivileged instructions. Defined values are:"; 312}; 313 314/* Source: AArch64-dacr32_el2.xml */ 315register DACR32_EL2 rw armv8_sysreg(DACR32_EL2) "Domain Access Control Register" { 316 D 32 "Domain n access permission, where n = 0 to 15. Permitted values are:"; 317}; 318 319/* Source: AArch64-rvbar_el2.xml */ 320register RVBAR_EL2 ro armv8_sysreg(RVBAR_EL2) "Reset Vector Base Address Register (if EL3 not implemented)" type(uint64); 321 322/* Source: AArch64-dbgclaimclr_el1.xml */ 323register DBGCLAIMCLR_EL1 rw armv8_sysreg(DBGCLAIMCLR_EL1) "Debug Claim Tag Clear register" { 324 _ 24 mbz "Reserved, RAZ/SBZ. Software can rely on these bits reading as zero, and must use a should-be-zero policy on writes. Implementations must ignore writes."; 325 CLAIM 8 "Read or clear CLAIM tag bits. Reading this field returns the current value of the CLAIM tag bits."; 326}; 327 328/* Source: AArch64-lorc_el1.xml */ 329register LORC_EL1 rw armv8_sysreg(LORC_EL1) "LORegion Control (EL1)" { 330 _ 54 mbz "Reserved, RES0."; 331 DS 8 "Descriptor Select. Selects the current LORegion descriptor accessed by LORSA_EL1, LOREA_EL1, and LORN_EL1."; 332 _ 1 mbz "Reserved, RES0."; 333 EN 1 "Enable. Indicates whether LORegions are enabled:"; 334}; 335 336/* Source: AArch64-sctlr_el1.xml */ 337register SCTLR_EL1 rw armv8_sysreg(SCTLR_EL1) "System Control Register (EL1)" { 338 _ 2 mbz "Reserved, RES0."; 339 LSMAOE 1 "Load Multiple and Store Multiple Atomicity and Ordering Enable. When the OPTIONAL feature is implemented, defined values are:"; 340 nTLSMD 1 "No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory. When the OPTIONAL feature is implemented, defined values are:"; 341 _ 1 mbz "Reserved, RES0."; 342 UCI 1 "Traps EL0 execution of cache maintenance instructions to EL1, from AArch64 state only."; 343 EE 1 type(endianness) "Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime."; 344 E0E 1 type(endianness) "Endianness of data accesses at EL0."; 345 SPAN 1 "Set Privileged Access Never, on taking an exception to EL1."; 346 _ 1 mb1 "Reserved, RES1."; 347 IESB 1 "Implicit Error Synchronizaition Barrier enable. Permitted values are:"; 348 _ 1 mb1 "Reserved, RES1."; 349 WXN 1 "Write permission implies XN (Execute-never). For the EL1&0 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:"; 350 nTWE 1 "Traps EL0 execution of WFE instructions to EL1, from both Execution states."; 351 _ 1 mbz "Reserved, RES0."; 352 nTWI 1 "Traps EL0 execution of WFI instructions to EL1, from both Execution states."; 353 UCT 1 "Traps EL0 accesses to the CTR_EL0 to EL1, from AArch64 state only."; 354 DZE 1 "Traps EL0 execution of DC ZVA instructions to EL1, from AArch64 state only."; 355 _ 1 mbz "Reserved, RES0."; 356 I 1 "Instruction access Cacheability control, for accesses at EL0 and EL1:"; 357 _ 1 mb1 "Reserved, RES1."; 358 _ 1 mbz "Reserved, RES0."; 359 UMA 1 "User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks to EL1, from AArch64 state only."; 360 SED 1 "SETEND instruction disable. Disables SETEND instructions at EL0 using AArch32."; 361 ITD 1 "IT Disable. Disables some uses of IT instructions at EL0 using AArch32."; 362 _ 1 mbz "Reserved, RES0."; 363 CP15BEN 1 "System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==1111) encoding space from EL0:"; 364 SA0 1 "SP Alignment check enable for EL0. When set to 1, if a load or store instruction executed at EL0 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see ."; 365 SA 1 "SP Alignment check enable. When set to 1, if a load or store instruction executed at EL1 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see ."; 366 C 1 "Cacheability control, for data accesses."; 367 A 1 "Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0:"; 368 M 1 "MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are:"; 369}; 370 371/* Source: AArch64-cntpct_el0.xml */ 372register CNTPCT_EL0 ro armv8_sysreg(CNTPCT_EL0) "Counter-timer Physical Count register" type(uint64); 373 374/* Source: AArch64-mdcr_el2.xml */ 375register MDCR_EL2 rw armv8_sysreg(MDCR_EL2) "Monitor Debug Configuration Register (EL2)" { 376 _ 14 mbz "Reserved, RES0."; 377 HPMD 1 "Guest Performance Monitors Disable. This control prohibits event counting at EL2. Permitted values are:"; 378 _ 2 mbz "Reserved, RES0."; 379 TPMS 1 "Trap Performance Monitor Sampling. When the Statistical Profiling Extension is implemented this field controls access to Statistical Profiling control registers from Non-secure EL1 and EL0. The possible values of this bit are:"; 380 E2PB 2 "EL2 Profiling Buffer. When the Statistical Profiling Extension is implemented this field controls the owning translation regime and access to Profiling Buffer control registers from Non-secure EL1. The possible values of this field are:"; 381 TDRA 1 "Trap Debug ROM Address register access. Traps Non-secure System register accesses to the Debug ROM registers to EL2. This trap is from:"; 382 TDOSA 1 "Trap debug OS-related register access. Traps Non-secure EL1 System register accesses to the powerdown debug registers to EL2, from both Execution states:"; 383 TDA 1 "Trap Debug Access. Traps Non-secure EL0 and EL1 System register accesses to those debug System registers that are not trapped by either of the following:"; 384 TDE 1 "Trap Debug exceptions. The possible values of this field are:"; 385 HPME 1 "Hypervisor Performance Monitors Counters Enable. The possible values of this bit are:"; 386 TPM 1 "Trap Performance Monitors accesses. Traps Non-secure EL0 and EL1 accesses to all Performance Monitors registers to EL2, from both Execution states:"; 387 TPMCR 1 "Trap PMCR_EL0 or PMCR accesses. Traps Non-secure EL0 and EL1 accesses to the PMCR_EL0 or PMCR to EL2."; 388 HPMN 5 "Defines the number of Performance Monitors counters that are accessible from Non-secure EL0 and EL1 modes."; 389}; 390 391/* Source: AArch64-oseccr_el1.xml */ 392register OSECCR_EL1 rw armv8_sysreg(OSECCR_EL1) "OS Lock Exception Catch Control Register" { 393 EDECCR 32 "Used for save/restore to EDECCR over powerdown."; 394}; 395 396/* Source: AArch64-spsr_und.xml */ 397register SPSR_und rw armv8_sysreg(SPSR_und) "Saved Program Status Register (Undefined mode)" { 398 N 1 "Set to the value of CPSR.N on taking an exception to Undefined mode, and copied to CPSR.N on executing an exception return operation in Undefined mode."; 399 Z 1 "Set to the value of CPSR.Z on taking an exception to Undefined mode, and copied to CPSR.Z on executing an exception return operation in Undefined mode."; 400 C 1 "Set to the value of CPSR.C on taking an exception to Undefined mode, and copied to CPSR.C on executing an exception return operation in Undefined mode."; 401 V 1 "Set to the value of CPSR.V on taking an exception to Undefined mode, and copied to CPSR.V on executing an exception return operation in Undefined mode."; 402 Q 1 "Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions."; 403 IT_lo 2 "IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field."; 404 J 1 "RES0."; 405 _ 1 mbz "Reserved, RES0."; 406 PAN 1 "When is implemented, set to the value of CPSR.PAN on taking an exception to Undefined mode, and copied to CPSR.PAN on executing an exception return operation in Undefined mode."; 407 _ 1 mbz "Reserved, RES0."; 408 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 409 GE 4 "Greater than or Equal flags, for parallel addition and subtraction."; 410 IT_hi 6 "IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts."; 411 E 1 "Endianness state bit. Controls the load and store endianness for data accesses:"; 412 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 413 I 1 "IRQ mask bit. The possible values of this bit are:"; 414 F 1 "FIQ mask bit. The possible values of this bit are:"; 415 T 1 "T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:"; 416 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 417 M_lo 4 "AArch32 mode that an exception was taken from. The possible values are:"; 418}; 419 420/* Source: AArch64-id_isar3_el1.xml */ 421register ID_ISAR3_EL1 ro armv8_sysreg(ID_ISAR3_EL1) "AArch32 Instruction Set Attribute Register 3" { 422 T32EE 4 "Indicates the implemented T32EE instructions. Defined values are:"; 423 TrueNOP 4 "Indicates the implemented true NOP instructions. Defined values are:"; 424 T32Copy 4 "Indicates the support for T32 non flag-setting MOV instructions. Defined values are:"; 425 TabBranch 4 "Indicates the implemented Table Branch instructions in the T32 instruction set. Defined values are:"; 426 SynchPrim 4 "Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions. Defined values are:"; 427 SVC 4 "Indicates the implemented SVC instructions. Defined values are:"; 428 SIMD 4 "Indicates the implemented SIMD instructions. Defined values are:"; 429 Saturate 4 "Indicates the implemented Saturate instructions. Defined values are:"; 430}; 431 432/* Source: AArch64-icc_ctlr_el3.xml */ 433register ICC_CTLR_EL3 rw armv8_sysreg(ICC_CTLR_EL3) "Interrupt Controller Control Register (EL3)" { 434 _ 14 mbz "Reserved, RES0."; 435 nDS 1 "Disable Security not supported. Read-only and writes are ignored. Possible values are:"; 436 _ 1 mbz "Reserved, RES0."; 437 A3V 1 "Affinity 3 Valid. Read-only and writes are ignored. Possible values are:"; 438 SEIS 1 "SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports generation of SEIs:"; 439 IDbits 3 "Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:"; 440 PRIbits 3 "Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one."; 441 _ 1 mbz "Reserved, RES0."; 442 PMHE 1 "Priority Mask Hint Enable."; 443 RM 1 "Routing Modifier. For legacy operation of EL1 software with GICC_CTLR.FIQen set to 1, this bit indicates whether interrupts can be acknowledged or observed as the Highest Priority Pending Interrupt, or whether a special INTID value is returned."; 444 EOImode_EL1NS 1 "EOI mode for interrupts handled at Non-secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt:"; 445 EOImode_EL1S 1 "EOI mode for interrupts handled at Secure EL1. Controls whether a write to an End of Interrupt register also deactivates the interrupt:"; 446 EOImode_EL3 1 "EOI mode for interrupts handled at EL3. Controls whether a write to an End of Interrupt register also deactivates the interrupt:"; 447 CBPR_EL1NS 1 "Common Binary Point Register, EL1 Non-secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2:"; 448 CBPR_EL1S 1 "Common Binary Point Register, EL1 Secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts at EL1:"; 449}; 450 451/* Source: AArch64-icc_sgi1r_el1.xml */ 452register ICC_SGI1R_EL1 wo armv8_sysreg(ICC_SGI1R_EL1) "Interrupt Controller Software Generated Interrupt Group 1 Register" { 453 _ 8 mbz "Reserved, RES0."; 454 Aff3 8 "The affinity 3 value of the affinity path of the cluster for which SGI interrupts will be generated."; 455 _ 7 mbz "Reserved, RES0."; 456 IRM 1 "Interrupt Routing Mode. Determines how the generated interrupts are distributed to PEs. Possible values are:"; 457 Aff2 8 "The affinity 2 value of the affinity path of the cluster for which SGI interrupts will be generated."; 458 _ 4 mbz "Reserved, RES0."; 459 INTID 4 "The INTID of the SGI."; 460 Aff1 8 "The affinity 1 value of the affinity path of the cluster for which SGI interrupts will be generated."; 461 TargetList 16 "Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number."; 462}; 463 464/* Source: AArch64-contextidr_el2.xml */ 465register CONTEXTIDR_EL2 rw armv8_sysreg(CONTEXTIDR_EL2) "Context ID Register (EL2)" { 466 PROCID 32 "Process Identifier. This field must be programmed with a unique value that identifies the current process."; 467}; 468 469/* Source: AArch64-id_aa64mmfr1_el1.xml */ 470register ID_AA64MMFR1_EL1 ro armv8_sysreg(ID_AA64MMFR1_EL1) "AArch64 Memory Model Feature Register 1" { 471 _ 32 mbz "Reserved, RES0."; 472 XNX 4 "Indicates support for Execute Never control distinction at stage 2 bit. Defined values are:"; 473 SpecSEI 4 "Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:"; 474 PAN 4 "Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. Defined values are:"; 475 LO 4 "LORegions. Indicates support for LORegions. Defined values are:"; 476 HPDS 4 "Hierarchical permission disables bits in translation tables. Defined values are:"; 477 VH 4 "Virtualization Host Extensions. Defined values are:"; 478 VMIDBits 4 "Number of VMID bits. Defined values are:"; 479 HAFDBS 4 "Hardware updates to Access flag and Dirty state in translation tables. Defined values are:"; 480}; 481 482/* Source: AArch64-pmintenclr_el1.xml */ 483register PMINTENCLR_EL1 rw armv8_sysreg(PMINTENCLR_EL1) "Performance Monitors Interrupt Enable Clear register" { 484 C 1 "PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are:"; 485 P 31 "Event counter overflow interrupt request disable bit for PMEVCNTR<n>_EL0."; 486}; 487 488/* Source: AArch64-tcr_el1.xml */ 489register TCR_EL1 rw armv8_sysreg(TCR_EL1) "Translation Control Register (EL1)" { 490 _ 9 mbz "Reserved, RES0."; 491 NFD1 1 "Present only if is implemented."; 492 NFD0 1 "Present only if is implemented."; 493 _ 2 mbz "Reserved, RES0."; 494 HWU162 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1."; 495 HWU161 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1."; 496 HWU160 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1."; 497 HWU159 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1."; 498 HWU062 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1."; 499 HWU061 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1."; 500 HWU060 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1."; 501 HWU059 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1."; 502 HPD1 1 "Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR1_EL1."; 503 HPD0 1 "Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL1."; 504 HD 1 "Hardware management of dirty state in stage 1 translations from EL0 and EL1."; 505 HA 1 "Hardware Access flag update in stage 1 translations from EL0 and EL1."; 506 TBI1 1 "Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values are:"; 507 TBI0 1 "Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values are:"; 508 AS 1 type(ASID_size) "ASID Size. Defined values are:"; 509 _ 1 mbz "Reserved, RES0."; 510 IPS 3 "Intermediate Physical Address Size."; 511 TG1 2 type(granule) "Granule size for the TTBR1_EL1."; 512 SH1 2 type(shareability) "Shareability attribute for memory associated with translation table walks using TTBR1_EL1. Defined values are:"; 513 ORGN1 2 type(cacheability) "Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1."; 514 IRGN1 2 type(cacheability) "Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1."; 515 EPD1 1 "Translation table walk disable for translations using TTBR1_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1_EL1. The encoding of this bit is:"; 516 A1 1 "Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:"; 517 T1SZ 6 "The size offset of the memory region addressed by TTBR1_EL1. The region size is 2(64-T1SZ) bytes."; 518 TG0 2 type(granule) "Granule size for the TTBR0_EL1."; 519 SH0 2 type(shareability) "Shareability attribute for memory associated with translation table walks using TTBR0_EL1."; 520 ORGN0 2 type(cacheability) "Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1."; 521 IRGN0 2 type(cacheability) "Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1."; 522 EPD0 1 "Translation table walk disable for translations using TTBR0_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0_EL1. The encoding of this bit is:"; 523 _ 1 mbz "Reserved, RES0."; 524 T0SZ 6 "The size offset of the memory region addressed by TTBR0_EL1. The region size is 2(64-T0SZ) bytes."; 525}; 526 527/* Source: AArch64-tcr_el3.xml */ 528register TCR_EL3 rw armv8_sysreg(TCR_EL3) "Translation Control Register (EL3)" { 529 _ 1 mb1 "Reserved, RES1."; 530 _ 2 mbz "Reserved, RES0."; 531 HWU62 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1."; 532 HWU61 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1."; 533 HWU60 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1."; 534 HWU59 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1."; 535 HPD 1 "Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL3."; 536 _ 1 mb1 "Reserved, RES1."; 537 HD 1 "Hardware management of dirty state in stage 1 translations from EL3."; 538 HA 1 "Hardware Access flag update in stage 1 translations from EL3."; 539 TBI 1 "Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL3 region, or ignored and used for tagged addresses."; 540 _ 1 mbz "Reserved, RES0."; 541 PS 3 "Physical Address Size."; 542 TG0 2 "Granule size for the TTBR0_EL3."; 543 SH0 2 "Shareability attribute for memory associated with translation table walks using TTBR0_EL3."; 544 ORGN0 2 "Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3."; 545 IRGN0 2 "Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3."; 546 _ 2 mbz "Reserved, RES0."; 547 T0SZ 6 "The size offset of the memory region addressed by TTBR0_EL3. The region size is 2(64-T0SZ) bytes."; 548}; 549 550/* Source: AArch64-icc_iar0_el1.xml */ 551register ICC_IAR0_EL1 ro armv8_sysreg(ICC_IAR0_EL1) "Interrupt Controller Interrupt Acknowledge Register 0" { 552 _ 8 mbz "Reserved, RES0."; 553 INTID 24 "The INTID of the signaled interrupt."; 554}; 555 556/* Source: AArch64-actlr_el3.xml */ 557register ACTLR_EL3 rw armv8_sysreg(ACTLR_EL3) "Auxiliary Control Register (EL3)" { 558 IMPLEMENTATION_DEFINED 64 "IMPLEMENTATION DEFINED."; 559}; 560 561/* Source: AArch64-id_mmfr4_el1.xml */ 562register ID_MMFR4_EL1 ro armv8_sysreg(ID_MMFR4_EL1) "AArch32 Memory Model Feature Register 4" { 563 _ 8 mbz "Reserved, RAZ."; 564 LSM 4 "Indicates support for LSMAOE and nTLSMD bits in HSCTLR and SCTLR. Defined values are:"; 565 HPDS 4 "Hierarchical permission disables bits in translation tables. Defined values are:"; 566 CnP 4 "Common not Private translations. Defined values are:"; 567 XNX 4 "Support for execute never control distinction at stage 2 bit. Defined values are:"; 568 AC2 4 "Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2. Defined values are:"; 569 SpecSEI 4 "Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:"; 570}; 571 572/* Source: AArch64-daif.xml */ 573register DAIF rw armv8_sysreg(DAIF) "Interrupt Mask Bits" { 574 _ 22 mbz "Reserved, RES0."; 575 D 1 "Process state D mask. The possible values of this bit are:"; 576 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 577 I 1 "IRQ mask bit. The possible values of this bit are:"; 578 F 1 "FIQ mask bit. The possible values of this bit are:"; 579 _ 6 mbz "Reserved, RES0."; 580}; 581 582/* Source: AArch64-elr_el3.xml */ 583register ELR_EL3 rw armv8_sysreg(ELR_EL3) "Exception Link Register (EL3)" type(uint64); 584 585/* Source: AArch64-dbgprcr_el1.xml */ 586register DBGPRCR_EL1 rw armv8_sysreg(DBGPRCR_EL1) "Debug Power Control Register" { 587 _ 31 mbz "Reserved, RES0."; 588 CORENPDRQ 1 "Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are:"; 589}; 590 591/* Source: AArch64-pmuserenr_el0.xml */ 592register PMUSERENR_EL0 rw armv8_sysreg(PMUSERENR_EL0) "Performance Monitors User Enable Register" { 593 _ 28 mbz "Reserved, RES0."; 594 ER 1 "Event counter read trap control:"; 595 CR 1 "Cycle counter read trap control:"; 596 SW 1 "Software Increment write trap control:"; 597 EN 1 "Traps EL0 accesses to the Performance Monitors registers to EL1, from both Execution states:"; 598}; 599 600/* Source: AArch64-cntps_tval_el1.xml */ 601register CNTPS_TVAL_EL1 rw armv8_sysreg(CNTPS_TVAL_EL1) "Counter-timer Physical Secure Timer TimerValue register" { 602 TimerValue 32 "The TimerValue view of the secure physical timer."; 603}; 604 605/* Source: AArch64-pmselr_el0.xml */ 606register PMSELR_EL0 rw armv8_sysreg(PMSELR_EL0) "Performance Monitors Event Counter Selection Register" { 607 _ 27 mbz "Reserved, RES0."; 608 SEL 5 "Selects event counter, PMEVCNTR<n>, where n is the value held in this field. This value identifies which event counter is accessed when a subsequent access to PMXEVTYPER_EL0 or PMXEVCNTR_EL0 occurs."; 609}; 610 611/* Source: AArch64-rmr_el2.xml */ 612register RMR_EL2 rw armv8_sysreg(RMR_EL2) "Reset Management Register (EL2)" { 613 _ 30 mbz "Reserved, RES0."; 614 RR 1 "Reset Request. Setting this bit to 1 requests a Warm reset."; 615 AA64 1 "When EL2 can use AArch32, determines which Execution state the PE boots into after a Warm reset:"; 616}; 617 618/* Source: AArch64-spsr_el1.xml */ 619register SPSR_EL1 rw armv8_sysreg(SPSR_EL1) "Saved Program Status Register (EL1)" { 620 N 1 "Set to the value of the N condition flag on taking an exception to EL1, and copied to the N condition flag on executing an exception return operation in EL1."; 621 Z 1 "Set to the value of the Z condition flag on taking an exception to EL1, and copied to the Z condition flag on executing an exception return operation in EL1."; 622 C 1 "Set to the value of the C condition flag on taking an exception to EL1, and copied to the C condition flag on executing an exception return operation in EL1."; 623 V 1 "Set to the value of the V condition flag on taking an exception to EL1, and copied to the V condition flag on executing an exception return operation in EL1."; 624 _ 4 mbz "Reserved, RES0."; 625 UAO 1 "When is implemented, set to the value of PSTATE.UAO on taking an exception to EL1, and copied to PSTATE.UAO on executing an exception return operation in EL1."; 626 PAN 1 "When is implemented, set to the value of PSTATE.PAN on taking an exception to EL1, and copied to PSTATE.PAN on executing an exception return operation in EL1."; 627 SS 1 "Software step. Shows the value of PSTATE.SS immediately before the exception was taken."; 628 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 629 _ 10 mbz "Reserved, RES0."; 630 D 1 "Process state D mask. The possible values of this bit are:"; 631 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 632 I 1 "IRQ mask bit. The possible values of this bit are:"; 633 F 1 "FIQ mask bit. The possible values of this bit are:"; 634 _ 1 mbz "Reserved, RES0."; 635 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 636 M_lo 4 "AArch64 state (Exception level and selected SP) that an exception was taken from. The possible values are:"; 637}; 638 639/* Source: AArch64-pmswinc_el0.xml */ 640register PMSWINC_EL0 wo armv8_sysreg(PMSWINC_EL0) "Performance Monitors Software Increment register" { 641 _ 1 mbz "Reserved, RES0."; 642 P 31 "Event counter software increment bit for PMEVCNTR<n>_EL0."; 643}; 644 645/* Source: AArch64-osdtrtx_el1.xml */ 646register OSDTRTX_EL1 rw armv8_sysreg(OSDTRTX_EL1) "OS Lock Data Transfer Register, Transmit" type(uint32); 647 648/* Source: AArch64-lorn_el1.xml */ 649register LORN_EL1 rw armv8_sysreg(LORN_EL1) "LORegion Number (EL1)" { 650 _ 56 mbz "Reserved, RES0."; 651 Num 8 "Number of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS."; 652}; 653 654/* Source: AArch64-dbgvcr32_el2.xml */ 655register DBGVCR32_EL2 rw armv8_sysreg(DBGVCR32_EL2) "Debug Vector Catch Register" { 656 NSF 1 "FIQ vector catch enable in Non-secure state."; 657 NSI 1 "IRQ vector catch enable in Non-secure state."; 658 _ 1 mbz "Reserved, RES0."; 659 NSD 1 "Data Abort vector catch enable in Non-secure state."; 660 NSP 1 "Prefetch Abort vector catch enable in Non-secure state."; 661 NSS 1 "Supervisor Call (SVC) vector catch enable in Non-secure state."; 662 NSU 1 "Undefined Instruction vector catch enable in Non-secure state."; 663 _ 17 mbz "Reserved, RES0."; 664 SF 1 "FIQ vector catch enable in Secure state."; 665 SI 1 "IRQ vector catch enable in Secure state."; 666 _ 1 mbz "Reserved, RES0."; 667 SD 1 "Data Abort vector catch enable in Secure state."; 668 SP 1 "Prefetch Abort vector catch enable in Secure state."; 669 SS 1 "Supervisor Call (SVC) vector catch enable in Secure state."; 670 SU 1 "Undefined Instruction vector catch enable in Secure state."; 671 _ 1 mbz "Reserved, RES0."; 672}; 673 674/* Source: AArch64-uao.xml */ 675register UAO rw armv8_sysreg(UAO) "User Access Override" { 676 _ 8 mbz "Reserved, RES0."; 677 UAO 1 "User Access Override. Defined values are:"; 678 _ 23 mbz "Reserved, RES0."; 679}; 680 681/* Source: AArch64-spsr_el3.xml */ 682register SPSR_EL3 rw armv8_sysreg(SPSR_EL3) "Saved Program Status Register (EL3)" { 683 N 1 "Set to the value of the N condition flag on taking an exception to EL3, and copied to the N condition flag on executing an exception return operation in EL3."; 684 Z 1 "Set to the value of the Z condition flag on taking an exception to EL3, and copied to the Z condition flag on executing an exception return operation in EL3."; 685 C 1 "Set to the value of the C condition flag on taking an exception to EL3, and copied to the C condition flag on executing an exception return operation in EL3."; 686 V 1 "Set to the value of the V condition flag on taking an exception to EL3, and copied to the V condition flag on executing an exception return operation in EL3."; 687 _ 4 mbz "Reserved, RES0."; 688 UAO 1 "When is implemented, set to the value of PSTATE.UAO on taking an exception to EL3, and copied to PSTATE.UAO on executing an exception return operation in EL3."; 689 PAN 1 "When is implemented, set to the value of PSTATE.PAN on taking an exception to EL3, and copied to PSTATE.PAN on executing an exception return operation in EL3."; 690 SS 1 "Software step. Shows the value of PSTATE.SS immediately before the exception was taken."; 691 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 692 _ 10 mbz "Reserved, RES0."; 693 D 1 "Process state D mask. The possible values of this bit are:"; 694 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 695 I 1 "IRQ mask bit. The possible values of this bit are:"; 696 F 1 "FIQ mask bit. The possible values of this bit are:"; 697 _ 1 mbz "Reserved, RES0."; 698 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 699 M_lo 4 "AArch64 state (Exception level and selected SP) that an exception was taken from. The possible values are:"; 700}; 701 702/* Source: AArch64-cntkctl_el1.xml */ 703register CNTKCTL_EL1 rw armv8_sysreg(CNTKCTL_EL1) "Counter-timer Kernel Control register" { 704 _ 22 mbz "Reserved, RES0."; 705 EL0PTEN 1 "When is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 accesses to the physical timer registers to EL1."; 706 EL0VTEN 1 "When is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 accesses to the virtual timer registers to EL1."; 707 EVNTI 4 "Selects which bit (0 to 15) of the counter register CNTVCT_EL0 is the trigger for the event stream generated from that counter, when that stream is enabled."; 708 EVNTDIR 1 "Controls which transition of the counter register CNTVCT_EL0 trigger bit, defined by EVNTI, generates an event when the event stream is enabled:"; 709 EVNTEN 1 "When is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, enables the generation of an event stream from the counter register CNTVCT_EL0:"; 710 EL0VCTEN 1 "When is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 accesses to the frequency register and virtual counter register to EL1."; 711 EL0PCTEN 1 "When is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 accesses to the frequency register and physical counter register to EL1."; 712}; 713 714/* Source: AArch64-ctr_el0.xml */ 715register CTR_EL0 ro armv8_sysreg(CTR_EL0) "Cache Type Register" { 716 _ 1 mb1 "Reserved, RES1."; 717 _ 3 mbz "Reserved, RES0."; 718 CWG 4 "Cache writeback granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified."; 719 ERG 4 "Exclusives reservation granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions."; 720 DminLine 4 "Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE."; 721 L1Ip 2 "Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache. Possible values of this field are:"; 722 _ 10 mbz "Reserved, RES0."; 723 IminLine 4 "Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE."; 724}; 725 726/* Source: AArch64-id_aa64mmfr0_el1.xml */ 727register ID_AA64MMFR0_EL1 ro armv8_sysreg(ID_AA64MMFR0_EL1) "AArch64 Memory Model Feature Register 0" { 728 _ 32 mbz "Reserved, RES0."; 729 TGran4 4 "Support for 4KB memory translation granule size. Defined values are:"; 730 TGran64 4 "Support for 64KB memory translation granule size. Defined values are:"; 731 TGran16 4 "Support for 16KB memory translation granule size. Defined values are:"; 732 BigEndEL0 4 "Mixed-endian support at EL0 only. Defined values are:"; 733 SNSMem 4 "Secure versus Non-secure Memory distinction. Defined values are:"; 734 BigEnd 4 "Mixed-endian configuration support. Defined values are:"; 735 ASIDBits 4 "Number of ASID bits. Defined values are:"; 736 PARange 4 "Physical Address range supported. Defined values are:"; 737}; 738 739/* Source: AArch64-tpidrro_el0.xml */ 740register TPIDRRO_EL0 rw armv8_sysreg(TPIDRRO_EL0) "EL0 Read-Only Software Thread ID Register" type(uint64); 741 742/* Source: AArch64-pmevcntrn_el0.xml */ 743register PMEVCNTR0_EL0 rw armv8_sysreg(PMEVCNTR0_EL0) "Performance Monitors Event Count Registers" type(uint32); 744register PMEVCNTR1_EL0 rw armv8_sysreg(PMEVCNTR1_EL0) "Performance Monitors Event Count Registers" type(uint32); 745register PMEVCNTR2_EL0 rw armv8_sysreg(PMEVCNTR2_EL0) "Performance Monitors Event Count Registers" type(uint32); 746register PMEVCNTR3_EL0 rw armv8_sysreg(PMEVCNTR3_EL0) "Performance Monitors Event Count Registers" type(uint32); 747register PMEVCNTR4_EL0 rw armv8_sysreg(PMEVCNTR4_EL0) "Performance Monitors Event Count Registers" type(uint32); 748register PMEVCNTR5_EL0 rw armv8_sysreg(PMEVCNTR5_EL0) "Performance Monitors Event Count Registers" type(uint32); 749register PMEVCNTR6_EL0 rw armv8_sysreg(PMEVCNTR6_EL0) "Performance Monitors Event Count Registers" type(uint32); 750register PMEVCNTR7_EL0 rw armv8_sysreg(PMEVCNTR7_EL0) "Performance Monitors Event Count Registers" type(uint32); 751register PMEVCNTR8_EL0 rw armv8_sysreg(PMEVCNTR8_EL0) "Performance Monitors Event Count Registers" type(uint32); 752register PMEVCNTR9_EL0 rw armv8_sysreg(PMEVCNTR9_EL0) "Performance Monitors Event Count Registers" type(uint32); 753register PMEVCNTR10_EL0 rw armv8_sysreg(PMEVCNTR10_EL0) "Performance Monitors Event Count Registers" type(uint32); 754register PMEVCNTR11_EL0 rw armv8_sysreg(PMEVCNTR11_EL0) "Performance Monitors Event Count Registers" type(uint32); 755register PMEVCNTR12_EL0 rw armv8_sysreg(PMEVCNTR12_EL0) "Performance Monitors Event Count Registers" type(uint32); 756register PMEVCNTR13_EL0 rw armv8_sysreg(PMEVCNTR13_EL0) "Performance Monitors Event Count Registers" type(uint32); 757register PMEVCNTR14_EL0 rw armv8_sysreg(PMEVCNTR14_EL0) "Performance Monitors Event Count Registers" type(uint32); 758register PMEVCNTR15_EL0 rw armv8_sysreg(PMEVCNTR15_EL0) "Performance Monitors Event Count Registers" type(uint32); 759register PMEVCNTR16_EL0 rw armv8_sysreg(PMEVCNTR16_EL0) "Performance Monitors Event Count Registers" type(uint32); 760register PMEVCNTR17_EL0 rw armv8_sysreg(PMEVCNTR17_EL0) "Performance Monitors Event Count Registers" type(uint32); 761register PMEVCNTR18_EL0 rw armv8_sysreg(PMEVCNTR18_EL0) "Performance Monitors Event Count Registers" type(uint32); 762register PMEVCNTR19_EL0 rw armv8_sysreg(PMEVCNTR19_EL0) "Performance Monitors Event Count Registers" type(uint32); 763register PMEVCNTR20_EL0 rw armv8_sysreg(PMEVCNTR20_EL0) "Performance Monitors Event Count Registers" type(uint32); 764register PMEVCNTR21_EL0 rw armv8_sysreg(PMEVCNTR21_EL0) "Performance Monitors Event Count Registers" type(uint32); 765register PMEVCNTR22_EL0 rw armv8_sysreg(PMEVCNTR22_EL0) "Performance Monitors Event Count Registers" type(uint32); 766register PMEVCNTR23_EL0 rw armv8_sysreg(PMEVCNTR23_EL0) "Performance Monitors Event Count Registers" type(uint32); 767register PMEVCNTR24_EL0 rw armv8_sysreg(PMEVCNTR24_EL0) "Performance Monitors Event Count Registers" type(uint32); 768register PMEVCNTR25_EL0 rw armv8_sysreg(PMEVCNTR25_EL0) "Performance Monitors Event Count Registers" type(uint32); 769register PMEVCNTR26_EL0 rw armv8_sysreg(PMEVCNTR26_EL0) "Performance Monitors Event Count Registers" type(uint32); 770register PMEVCNTR27_EL0 rw armv8_sysreg(PMEVCNTR27_EL0) "Performance Monitors Event Count Registers" type(uint32); 771register PMEVCNTR28_EL0 rw armv8_sysreg(PMEVCNTR28_EL0) "Performance Monitors Event Count Registers" type(uint32); 772register PMEVCNTR29_EL0 rw armv8_sysreg(PMEVCNTR29_EL0) "Performance Monitors Event Count Registers" type(uint32); 773 774/* Source: AArch64-ich_hcr_el2.xml */ 775register ICH_HCR_EL2 rw armv8_sysreg(ICH_HCR_EL2) "Interrupt Controller Hyp Control Register" { 776 EOIcount 5 "This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either:"; 777 _ 12 mbz "Reserved, RES0."; 778 TDIR 1 "Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR_EL1."; 779 TSEI 1 "Trap all locally generated SEIs. This bit allows the hypervisor to intercept locally generated SEIs that would otherwise be taken at Non-secure EL1."; 780 TALL1 1 "Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2."; 781 TALL0 1 "Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2."; 782 TC 1 "Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2."; 783 _ 2 mbz "Reserved, RES0."; 784 VGrp1DIE 1 "VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is disabled:"; 785 VGrp1EIE 1 "VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is enabled:"; 786 VGrp0DIE 1 "VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is disabled:"; 787 VGrp0EIE 1 "VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is enabled:"; 788 NPIE 1 "No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt while no pending interrupts are present in the List registers:"; 789 LRENPIE 1 "List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request:"; 790 UIE 1 "Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry:"; 791 En 1 "Enable. Global enable bit for the virtual CPU interface:"; 792}; 793 794/* Source: AArch64-icc_igrpen1_el3.xml */ 795register ICC_IGRPEN1_EL3 rw armv8_sysreg(ICC_IGRPEN1_EL3) "Interrupt Controller Interrupt Group 1 Enable register (EL3)" { 796 _ 30 mbz "Reserved, RES0."; 797 EnableGrp1S 1 "Enables Group 1 interrupts for the Secure state."; 798 EnableGrp1NS 1 "Enables Group 1 interrupts for the Non-secure state."; 799}; 800 801/* Source: AArch64-mdcr_el3.xml */ 802register MDCR_EL3 rw armv8_sysreg(MDCR_EL3) "Monitor Debug Configuration Register (EL3)" { 803 _ 10 mbz "Reserved, RES0."; 804 EPMAD 1 "External debug interface Performance Monitors registers disable. This disables access to these registers by an external debugger:"; 805 EDAD 1 "External debug interface breakpoint and watchpoint register access disable. This disables access to these registers by an external debugger:"; 806 _ 2 mbz "Reserved, RES0."; 807 SPME 1 "Secure Performance Monitors enable. This allows event counting in Secure state:"; 808 SDD 1 "AArch64 Secure self-hosted invasive debug disable. Disables Software debug exceptions in Secure state, other than Breakpoint Instruction exceptions."; 809 SPD32 2 "AArch32 Secure self-hosted privileged invasive debug control. Enables or disables debug exceptions from Secure EL1 using AArch32, other than Breakpoint Instruction exceptions. Valid values for this field are:"; 810 NSPB 2 "Non-secure Profiling Buffer. When the Statistical Profiling Extension is implemented, this field controls the owning translation regime and accesses to Statistical Profiling and Profiling Buffer control registers. The possible values of this field are:"; 811 _ 1 mbz "Reserved, RES0."; 812 TDOSA 1 "Trap debug OS-related register access. Traps EL2 and EL1 System register accesses to the powerdown debug registers to EL3:"; 813 TDA 1 "Trap Debug Access. Traps EL2, EL1, and EL0 System register accesses to those debug System registers that cannot be trapped using the MDCR_EL3.TDOSA field. When MDCR_EL3.TDA is:"; 814 _ 2 mbz "Reserved, RES0."; 815 TPM 1 "Trap Performance Monitors accesses. Traps EL2, EL1, and EL0 accesses to all Performance Monitors registers to EL3, from both Security states and both Execution states."; 816 _ 6 mbz "Reserved, RES0."; 817}; 818 819/* Source: AArch64-tpidr_el2.xml */ 820register TPIDR_EL2 rw armv8_sysreg(TPIDR_EL2) "EL2 Software Thread ID Register" type(uint64); 821 822/* Source: AArch64-spsr_irq.xml */ 823register SPSR_irq rw armv8_sysreg(SPSR_irq) "Saved Program Status Register (IRQ mode)" { 824 N 1 "Set to the value of CPSR.N on taking an exception to IRQ mode, and copied to CPSR.N on executing an exception return operation in IRQ mode."; 825 Z 1 "Set to the value of CPSR.Z on taking an exception to IRQ mode, and copied to CPSR.Z on executing an exception return operation in IRQ mode."; 826 C 1 "Set to the value of CPSR.C on taking an exception to IRQ mode, and copied to CPSR.C on executing an exception return operation in IRQ mode."; 827 V 1 "Set to the value of CPSR.V on taking an exception to IRQ mode, and copied to CPSR.V on executing an exception return operation in IRQ mode."; 828 Q 1 "Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions."; 829 IT_lo 2 "IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field."; 830 J 1 "RES0."; 831 _ 1 mbz "Reserved, RES0."; 832 PAN 1 "When is implemented, set to the value of CPSR.PAN on taking an exception to IRQ mode, and copied to CPSR.PAN on executing an exception return operation in IRQ mode."; 833 _ 1 mbz "Reserved, RES0."; 834 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 835 GE 4 "Greater than or Equal flags, for parallel addition and subtraction."; 836 IT_hi 6 "IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts."; 837 E 1 "Endianness state bit. Controls the load and store endianness for data accesses:"; 838 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 839 I 1 "IRQ mask bit. The possible values of this bit are:"; 840 F 1 "FIQ mask bit. The possible values of this bit are:"; 841 T 1 "T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:"; 842 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 843 M_lo 4 "AArch32 mode that an exception was taken from. The possible values are:"; 844}; 845 846/* Source: AArch64-icc_hppir0_el1.xml */ 847register ICC_HPPIR0_EL1 ro armv8_sysreg(ICC_HPPIR0_EL1) "Interrupt Controller Highest Priority Pending Interrupt Register 0" { 848 _ 8 mbz "Reserved, RES0."; 849 INTID 24 "The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level."; 850}; 851 852/* Source: AArch64-pmceid0_el0.xml */ 853register PMCEID0_EL0 ro armv8_sysreg(PMCEID0_EL0) "Performance Monitors Common Event Identification register 0" { 854 ID_hi 32 "PMCEID0_EL0[63:32] maps to common events 0x4000 to 0x401F. For a list of event numbers and descriptions, see ."; 855 ID_lo 32 "PMCEID0_EL0[31:0] maps to common events 0x0000 to 0x001F. For a list of event numbers and descriptions, see ."; 856}; 857 858/* Source: AArch64-fpsr.xml */ 859register FPSR rw armv8_sysreg(FPSR) "Floating-point Status Register" { 860 N 1 "Negative condition flag for AArch32 floating-point comparison operations. AArch64 floating-point comparisons set the PSTATE.N flag instead."; 861 Z 1 "Zero condition flag for AArch32 floating-point comparison operations. AArch64 floating-point comparisons set the PSTATE.Z flag instead."; 862 C 1 "Carry condition flag for AArch32 floating-point comparison operations. AArch64 floating-point comparisons set the PSTATE.C flag instead."; 863 V 1 "Overflow condition flag for AArch32 floating-point comparison operations. AArch64 floating-point comparisons set the PSTATE.V flag instead."; 864 QC 1 "Cumulative saturation bit, Advanced SIMD only. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since 0 was last written to this bit."; 865 _ 19 mbz "Reserved, RES0."; 866 IDC 1 "Input Denormal cumulative floating-point exception bit. This bit is set to 1 to indicate that the Input Denormal floating-point exception has occurred since 0 was last written to this bit."; 867 _ 2 mbz "Reserved, RES0."; 868 IXC 1 "Inexact cumulative floating-point exception bit. This bit is set to 1 to indicate that the Inexact exception floating-point has occurred since 0 was last written to this bit."; 869 UFC 1 "Underflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Underflow floating-point exception has occurred since 0 was last written to this bit."; 870 OFC 1 "Overflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Overflow floating-point exception has occurred since 0 was last written to this bit."; 871 DZC 1 "Divide by Zero cumulative floating-point exception bit. This bit is set to 1 to indicate that the Divide by Zero floating-point exception has occurred since 0 was last written to this bit."; 872 IOC 1 "Invalid Operation cumulative floating-point exception bit. This bit is set to 1 to indicate that the Invalid Operation floating-point exception has occurred since 0 was last written to this bit."; 873}; 874 875/* Source: AArch64-ich_vmcr_el2.xml */ 876register ICH_VMCR_EL2 rw armv8_sysreg(ICH_VMCR_EL2) "Interrupt Controller Virtual Machine Control Register" { 877 VPMR 8 "Virtual Priority Mask. The priority mask level for the virtual CPU interface. If the priority of a pending virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE."; 878 VBPR0 3 "Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 1."; 879 VBPR1 3 "Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 0."; 880 _ 8 mbz "Reserved, RES0."; 881 VEOIM 1 "Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:"; 882 _ 4 mbz "Reserved, RES0."; 883 VCBPR 1 "Virtual Common Binary Point Register. Possible values of this bit are:"; 884 VFIQEn 1 "Virtual FIQ enable. Possible values of this bit are:"; 885 VAckCtl 1 "Virtual AckCtl. Possible values of this bit are:"; 886 VENG1 1 "Virtual Group 1 interrupt enable. Possible values of this bit are:"; 887 VENG0 1 "Virtual Group 0 interrupt enable. Possible values of this bit are:"; 888}; 889 890/* Source: AArch64-dlr_el0.xml */ 891register DLR_EL0 rw armv8_sysreg(DLR_EL0) "Debug Link Register" type(uint64); 892 893/* Source: AArch64-spsr_abt.xml */ 894register SPSR_abt rw armv8_sysreg(SPSR_abt) "Saved Program Status Register (Abort mode)" { 895 N 1 "Set to the value of CPSR.N on taking an exception to Abort mode, and copied to CPSR.N on executing an exception return operation in Abort mode."; 896 Z 1 "Set to the value of CPSR.Z on taking an exception to Abort mode, and copied to CPSR.Z on executing an exception return operation in Abort mode."; 897 C 1 "Set to the value of CPSR.C on taking an exception to Abort mode, and copied to CPSR.C on executing an exception return operation in Abort mode."; 898 V 1 "Set to the value of CPSR.V on taking an exception to Abort mode, and copied to CPSR.V on executing an exception return operation in Abort mode."; 899 Q 1 "Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions."; 900 IT_lo 2 "IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field."; 901 J 1 "RES0."; 902 _ 1 mbz "Reserved, RES0."; 903 PAN 1 "When is implemented, set to the value of CPSR.PAN on taking an exception to Abort mode, and copied to CPSR.PAN on executing an exception return operation in Abort mode."; 904 _ 1 mbz "Reserved, RES0."; 905 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 906 GE 4 "Greater than or Equal flags, for parallel addition and subtraction."; 907 IT_hi 6 "IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts."; 908 E 1 "Endianness state bit. Controls the load and store endianness for data accesses:"; 909 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 910 I 1 "IRQ mask bit. The possible values of this bit are:"; 911 F 1 "FIQ mask bit. The possible values of this bit are:"; 912 T 1 "T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:"; 913 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 914 M_lo 4 "AArch32 mode that an exception was taken from. The possible values are:"; 915}; 916 917/* Source: AArch64-mvfr0_el1.xml */ 918register MVFR0_EL1 ro armv8_sysreg(MVFR0_EL1) "AArch32 Media and VFP Feature Register 0" { 919 FPRound 4 "Floating-Point Rounding modes. Indicates whether the floating-point implementation provides support for rounding modes. Defined values are:"; 920 FPShVec 4 "Short Vectors. Indicates whether the floating-point implementation provides support for the use of short vectors. Defined values are:"; 921 FPSqrt 4 "Square Root. Indicates whether the floating-point implementation provides support for the ARMv6 VFP square root operations. Defined values are:"; 922 FPDivide 4 "Indicates whether the floating-point implementation provides support for VFP divide operations. Defined values are:"; 923 FPTrap 4 "Floating Point Exception Trapping. Indicates whether the floating-point implementation provides support for exception trapping. Defined values are:"; 924 FPDP 4 "Double Precision. Indicates whether the floating-point implementation provides support for double-precision operations. Defined values are:"; 925 FPSP 4 "Single Precision. Indicates whether the floating-point implementation provides support for single-precision operations. Defined values are:"; 926 SIMDReg 4 "Advanced SIMD registers. Indicates whether the Advanced SIMD and floating-point implementation provides support for the Advanced SIMD and floating-point register bank. Defined values are:"; 927}; 928 929/* Source: AArch64-hpfar_el2.xml */ 930register HPFAR_EL2 rw armv8_sysreg(HPFAR_EL2) "Hypervisor IPA Fault Address Register" { 931 _ 20 mbz "Reserved, RES0."; 932 FIPA_hi 4 "Extension to FIPA[47:12]. See FIPA[47:12] for more details."; 933 FIPA_lo 36 "Bits [47:12] of the faulting intermediate physical address. When is implemented, and 52-bit addresses and a 64KB translation granule are in use, FIPA[51:48] form the upper part of the address value. Otherwise, for implementations with fewer than 52 physical address bits, FIPA[51:48] are RES0."; 934 _ 4 mbz "Reserved, RES0."; 935}; 936 937/* Source: AArch64-id_isar5_el1.xml */ 938register ID_ISAR5_EL1 ro armv8_sysreg(ID_ISAR5_EL1) "AArch32 Instruction Set Attribute Register 5" { 939 _ 4 mbz "Reserved, RES0."; 940 RDM 4 "Indicates whether the VQRDMLAH and VQRDMLSH instructions are implemented in AArch32 state. Defined values are:"; 941 _ 4 mbz "Reserved, RES0."; 942 CRC32 4 "Indicates whether the CRC32 instructions are implemented in AArch32 state."; 943 SHA2 4 "Indicates whether the SHA2 instructions are implemented in AArch32 state."; 944 SHA1 4 "Indicates whether the SHA1 instructions are implemented in AArch32 state."; 945 AES 4 "Indicates whether the AES instructions are implemented in AArch32 state."; 946 SEVL 4 "Indicates whether the SEVL instruction is implemented in AArch32 state."; 947}; 948 949/* Source: AArch64-cntps_cval_el1.xml */ 950register CNTPS_CVAL_EL1 rw armv8_sysreg(CNTPS_CVAL_EL1) "Counter-timer Physical Secure Timer CompareValue register" { 951 CompareValue 64 "Holds the secure physical timer CompareValue."; 952}; 953 954/* Source: AArch64-esr_el1.xml */ 955register ESR_EL1 rw armv8_sysreg(ESR_EL1) "Exception Syndrome Register (EL1)" { 956 EC 6 "Exception Class. Indicates the reason for the exception that this register holds information about. Possible values of this field are:"; 957 IL 1 "Instruction Length for synchronous exceptions. Possible values of this bit are:"; 958 ISS 25 "Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class."; 959}; 960 961/* Source: AArch64-vpidr_el2.xml */ 962register VPIDR_EL2 rw armv8_sysreg(VPIDR_EL2) "Virtualization Processor ID Register" { 963 Implementer 8 "The Implementer code. This field must hold an implementer code that has been assigned by ARM. Assigned codes include the following:"; 964 Variant 4 "An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product."; 965 Architecture 4 "The permitted values of this field are:"; 966 PartNum 12 "An IMPLEMENTATION DEFINED primary part number for the device."; 967 Revision 4 "An IMPLEMENTATION DEFINED revision number for the device."; 968}; 969 970/* Source: AArch64-mvfr1_el1.xml */ 971register MVFR1_EL1 ro armv8_sysreg(MVFR1_EL1) "AArch32 Media and VFP Feature Register 1" { 972 SIMDFMAC 4 "Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions. Defined values are:"; 973 FPHP 4 "Floating Point Half Precision. Indicates the level of half-precision floating-point support. Defined values are:"; 974 SIMDHP 4 "Advanced SIMD Half Precision. Indicates the level of half-precision floating-point support. Defined values are:"; 975 SIMDSP 4 "Advanced SIMD Single Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions. Defined values are:"; 976 SIMDInt 4 "Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions. Defined values are:"; 977 SIMDLS 4 "Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions. Defined values are:"; 978 FPDNaN 4 "Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode. Defined values are:"; 979 FPFtZ 4 "Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation. Defined values are:"; 980}; 981 982/* Source: AArch64-sp_el2.xml */ 983register SP_EL2 rw armv8_sysreg(SP_EL2) "Stack Pointer (EL2)" type(uint64); 984 985/* Source: AArch64-ich_vtr_el2.xml */ 986register ICH_VTR_EL2 ro armv8_sysreg(ICH_VTR_EL2) "Interrupt Controller VGIC Type Register" { 987 PRIbits 3 "Priority bits. The number of virtual priority bits implemented, minus one."; 988 PREbits 3 "The number of virtual preemption bits implemented, minus one."; 989 IDbits 3 "The number of virtual interrupt identifier bits supported:"; 990 SEIS 1 "SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs:"; 991 A3V 1 "Affinity 3 Valid. Possible values are:"; 992 nV4 1 "Direct injection of virtual interrupts not supported. Possible values are:"; 993 TDS 1 "Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported."; 994 _ 14 mbz "Reserved, RES0."; 995 ListRegs 5 "The number of implemented List registers, minus one. For example, a value of 0b01111 indicates that the maximum of 16 List registers are implemented."; 996}; 997 998/* Source: AArch64-vtcr_el2.xml */ 999register VTCR_EL2 rw armv8_sysreg(VTCR_EL2) "Virtualization Translation Control Register" { 1000 _ 1 mb1 "Reserved, RES1."; 1001 _ 2 mbz "Reserved, RES0."; 1002 HWU62 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 2 translation table block or level 3 entry."; 1003 HWU61 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 2 translation table block or level 3 entry."; 1004 HWU60 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 2 translation table block or level 3 entry."; 1005 HWU59 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 2 translation table block or level 3 entry."; 1006 _ 2 mbz "Reserved, RES0."; 1007 HD 1 "Hardware management of dirty state in stage 2 translations from Non-secure EL0 and EL1."; 1008 HA 1 "Hardware Access flag update in stage 2 translations from Non-secure EL0 and EL1."; 1009 _ 1 mbz "Reserved, RES0."; 1010 VS 1 "VMID Size."; 1011 PS 3 "Physical Address Size."; 1012 TG0 2 "Granule size for the VTTBR_EL2."; 1013 SH0 2 "Shareability attribute for memory associated with translation table walks using VTTBR_EL2."; 1014 ORGN0 2 "Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2."; 1015 IRGN0 2 "Inner cacheability attribute for memory associated with translation table walks using VTTBR_EL2."; 1016 SL0 2 "Starting level of the VTCR_EL2 addressed region. The meaning of this field depends on the value of VTCR_EL2.TG0 (the granule size)."; 1017 T0SZ 6 "The size offset of the memory region addressed by VTTBR_EL2. The region size is 2(64-T0SZ) bytes."; 1018}; 1019 1020/* Source: AArch64-vttbr_el2.xml */ 1021register VTTBR_EL2 rw armv8_sysreg(VTTBR_EL2) "Virtualization Translation Table Base Register" { 1022 VMID_hi 8 "Extension to VMID[7:0]. See VMID[7:0] for more details."; 1023 VMID_lo 8 "The VMID for the translation table."; 1024 BADDR 47 "Translation table base address, A[47:x] or A[51:x], bits[47:1]."; 1025 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by VTTBR_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of VTTBR_EL2.CnP is 1."; 1026}; 1027 1028/* Source: AArch64-pmxevcntr_el0.xml */ 1029register PMXEVCNTR_EL0 rw armv8_sysreg(PMXEVCNTR_EL0) "Performance Monitors Selected Event Count Register" { 1030 PMEVCNTR 32 "Value of the selected event counter, PMEVCNTR<n>_EL0, where n is the value stored in PMSELR_EL0.SEL."; 1031}; 1032 1033/* Source: AArch64-fpcr.xml */ 1034register FPCR rw armv8_sysreg(FPCR) "Floating-point Control Register" { 1035 _ 5 mbz "Reserved, RES0."; 1036 AHP 1 "Alternative half-precision control bit:"; 1037 DN 1 "Default NaN mode control bit:"; 1038 FZ 1 "Flush-to-zero mode control bit:"; 1039 RMode 2 "Rounding Mode control field. The encoding of this field is:"; 1040 Stride 2 "This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Stride field."; 1041 FZ16 1 "When is implemented, flush-to-zero mode control bit on half-precision data-processing instructions:"; 1042 Len 3 "This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Len field."; 1043 IDE 1 "Input Denormal floating-point exception trap enable. Possible values are:"; 1044 _ 2 mbz "Reserved, RES0."; 1045 IXE 1 "Inexact floating-point exception trap enable. Possible values are:"; 1046 UFE 1 "Underflow floating-point exception trap enable. Possible values are:"; 1047 OFE 1 "Overflow floating-point exception trap enable. Possible values are:"; 1048 DZE 1 "Divide by Zero floating-point exception trap enable. Possible values are:"; 1049 IOE 1 "Invalid Operation floating-point exception trap enable. Possible values are:"; 1050 _ 8 mbz "Reserved, RES0."; 1051}; 1052 1053/* Source: AArch64-aidr_el1.xml */ 1054register AIDR_EL1 ro armv8_sysreg(AIDR_EL1) "Auxiliary ID Register" { 1055 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1056}; 1057 1058/* Source: AArch64-cnthv_tval_el2.xml */ 1059register CNTHV_TVAL_EL2 rw armv8_sysreg(CNTHV_TVAL_EL2) "Counter-timer Virtual Timer TimerValue register (EL2)" { 1060 TimerValue 32 "The TimerValue view of the EL2 virtual timer."; 1061}; 1062 1063/* Source: AArch64-icc_dir_el1.xml */ 1064register ICC_DIR_EL1 wo armv8_sysreg(ICC_DIR_EL1) "Interrupt Controller Deactivate Interrupt Register" { 1065 _ 8 mbz "Reserved, RES0."; 1066 INTID 24 "The INTID of the interrupt to be deactivated."; 1067}; 1068 1069/* Source: AArch64-tcr_el2.xml */ 1070register TCR_EL2 rw armv8_sysreg(TCR_EL2) "Translation Control Register (EL2)" { 1071 _ 32 mbz "Reserved, RES0."; 1072 _ 1 mb1 "Reserved, RES1."; 1073 _ 2 mbz "Reserved, RES0."; 1074 HWU62 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry if the TCR_EL2.HPD value is 1."; 1075 HWU61 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry if the TCR_EL2.HPD value is 1."; 1076 HWU60 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry if the TCR_EL2.HPD value is 1."; 1077 HWU59 1 "Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry if the TCR_EL2.HPD value is 1."; 1078 HPD 1 "Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL2."; 1079 _ 1 mb1 "Reserved, RES1."; 1080 HD 1 "Hardware management of dirty state in stage 1 translations from EL2."; 1081 HA 1 "Hardware Access flag update in stage 1 translations from EL2."; 1082 TBI 1 "Additionally, this affects changes to the program counter, when TBI is 1, caused by:"; 1083 _ 1 mbz "Reserved, RES0."; 1084 PS 3 "Physical Address Size."; 1085 TG0 2 type(granule) "Granule size for the TTBR0_EL2."; 1086 SH0 2 type(shareability) "Shareability attribute for memory associated with translation table walks using TTBR0_EL2."; 1087 ORGN0 2 type(cacheability) "Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2."; 1088 IRGN0 2 type(cacheability) "Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2."; 1089 _ 2 mbz "Reserved, RES0."; 1090 T0SZ 6 "The size offset of the memory region addressed by TTBR0_EL2. The region size is 2(64-T0SZ) bytes."; 1091}; 1092 1093/* Source: AArch64-oslsr_el1.xml */ 1094register OSLSR_EL1 ro armv8_sysreg(OSLSR_EL1) "OS Lock Status Register" { 1095 _ 28 mbz "Reserved, RES0."; 1096 OSLM_hi 1 "See below for description of the OSLM field."; 1097 nTT 1 "Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS Lock Access Register."; 1098 OSLK 1 "OS Lock Status. The possible values are:"; 1099 OSLM_lo 1 "OS lock model implemented. Identifies the form of OS save and restore mechanism implemented. In ARMv8 these bits are as follows:"; 1100}; 1101 1102/* Source: AArch64-revidr_el1.xml */ 1103register REVIDR_EL1 ro armv8_sysreg(REVIDR_EL1) "Revision ID Register" { 1104 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1105}; 1106 1107/* Source: AArch64-icc_eoir1_el1.xml */ 1108register ICC_EOIR1_EL1 wo armv8_sysreg(ICC_EOIR1_EL1) "Interrupt Controller End Of Interrupt Register 1" { 1109 _ 8 mbz "Reserved, RES0."; 1110 INTID 24 "The INTID from the corresponding ICC_IAR1_EL1 access."; 1111}; 1112 1113/* Source: AArch64-spsel.xml */ 1114register SPSel rw armv8_sysreg(SPSel) "Stack Pointer Select" { 1115 _ 31 mbz "Reserved, RES0."; 1116 SP 1 "Stack pointer to use. Possible values of this bit are:"; 1117}; 1118 1119/* Source: AArch64-id_mmfr0_el1.xml */ 1120register ID_MMFR0_EL1 ro armv8_sysreg(ID_MMFR0_EL1) "AArch32 Memory Model Feature Register 0" { 1121 InnerShr 4 "Innermost Shareability. Indicates the innermost shareability domain implemented. Defined values are:"; 1122 FCSE 4 "Indicates whether the implementation includes the FCSE. Defined values are:"; 1123 AuxReg 4 "Auxiliary Registers. Indicates support for Auxiliary registers. Defined values are:"; 1124 TCM 4 "Indicates support for TCMs and associated DMAs. Defined values are:"; 1125 ShareLvl 4 "Shareability Levels. Indicates the number of shareability levels implemented. Defined values are:"; 1126 OuterShr 4 "Outermost Shareability. Indicates the outermost shareability domain implemented. Defined values are:"; 1127 PMSA 4 "Indicates support for a PMSA. Defined values are:"; 1128 VMSA 4 "Indicates support for a VMSA. Defined values are:"; 1129}; 1130 1131/* Source: AArch64-icc_ap0rn_el1.xml */ 1132regtype ICC_AP0R_EL1_type "Interrupt Controller Active Priorities Group 0 Registers" { 1133 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1134}; 1135register ICC_AP0R0_EL1 rw armv8_sysreg(ICC_AP0R0_EL1) "Interrupt Controller Active Priorities Group 0 Registers" type(ICC_AP0R_EL1_type); 1136register ICC_AP0R1_EL1 rw armv8_sysreg(ICC_AP0R1_EL1) "Interrupt Controller Active Priorities Group 0 Registers" type(ICC_AP0R_EL1_type); 1137register ICC_AP0R2_EL1 rw armv8_sysreg(ICC_AP0R2_EL1) "Interrupt Controller Active Priorities Group 0 Registers" type(ICC_AP0R_EL1_type); 1138 1139/* Source: AArch64-id_mmfr2_el1.xml */ 1140register ID_MMFR2_EL1 ro armv8_sysreg(ID_MMFR2_EL1) "AArch32 Memory Model Feature Register 2" { 1141 HWAccFlg 4 "Hardware Access Flag. In earlier versions of the ARM Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:"; 1142 WFIStall 4 "Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:"; 1143 MemBarr 4 "Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==1111) encoding space:"; 1144 UniTLB 4 "Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:"; 1145 HvdTLB 4 "If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. ARM deprecates the use of this field by software."; 1146 L1HvdRng 4 "Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:"; 1147 L1HvdBG 4 "Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:"; 1148 L1HvdFG 4 "Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:"; 1149}; 1150 1151/* Source: AArch64-pmintenset_el1.xml */ 1152register PMINTENSET_EL1 rw armv8_sysreg(PMINTENSET_EL1) "Performance Monitors Interrupt Enable Set register" { 1153 C 1 "PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are:"; 1154 P 31 "Event counter overflow interrupt request enable bit for PMEVCNTR<n>_EL0."; 1155}; 1156 1157/* Source: AArch64-id_isar0_el1.xml */ 1158register ID_ISAR0_EL1 ro armv8_sysreg(ID_ISAR0_EL1) "AArch32 Instruction Set Attribute Register 0" { 1159 _ 4 mbz "Reserved, RES0."; 1160 Divide 4 "Indicates the implemented Divide instructions. Defined values are:"; 1161 Debug 4 "Indicates the implemented Debug instructions. Defined values are:"; 1162 Coproc 4 "Indicates the implemented System register access instructions. Defined values are:"; 1163 CmpBranch 4 "Indicates the implemented combined Compare and Branch instructions in the T32 instruction set. Defined values are:"; 1164 BitField 4 "Indicates the implemented BitField instructions. Defined values are:"; 1165 BitCount 4 "Indicates the implemented Bit Counting instructions. Defined values are:"; 1166 Swap 4 "Indicates the implemented Swap instructions in the A32 instruction set. Defined values are:"; 1167}; 1168 1169/* Source: AArch64-currentel.xml */ 1170register CurrentEL ro armv8_sysreg(CurrentEL) "Current Exception Level" { 1171 _ 28 mbz "Reserved, RES0."; 1172 EL 2 "Current Exception level. Possible values of this field are:"; 1173 _ 2 mbz "Reserved, RES0."; 1174}; 1175 1176/* Source: AArch64-actlr_el2.xml */ 1177register ACTLR_EL2 rw armv8_sysreg(ACTLR_EL2) "Auxiliary Control Register (EL2)" { 1178 IMPLEMENTATION_DEFINED 64 "IMPLEMENTATION DEFINED."; 1179}; 1180 1181/* Source: AArch64-ttbr0_el3.xml */ 1182register TTBR0_EL3 rw armv8_sysreg(TTBR0_EL3) "Translation Table Base Register 0 (EL3)" { 1183 _ 16 mbz "Reserved, RES0."; 1184 BADDR 47 "Translation table base address, A[47:x] or A[51:x]."; 1185 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by TTBR0_EL3 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1."; 1186}; 1187 1188/* Source: AArch64-icc_rpr_el1.xml */ 1189register ICC_RPR_EL1 ro armv8_sysreg(ICC_RPR_EL1) "Interrupt Controller Running Priority Register" { 1190 _ 24 mbz "Reserved, RES0."; 1191 Priority 8 "The current running priority on the CPU interface. This is the group priority of the current active interrupt."; 1192}; 1193 1194/* Source: AArch64-icc_sre_el2.xml */ 1195register ICC_SRE_EL2 rw armv8_sysreg(ICC_SRE_EL2) "Interrupt Controller System Register Enable register (EL2)" { 1196 _ 28 mbz "Reserved, RES0."; 1197 Enable 1 "Enable. Enables lower Exception level access to ICC_SRE_EL1."; 1198 DIB 1 "Disable IRQ bypass."; 1199 DFB 1 "Disable FIQ bypass."; 1200 SRE 1 "System Register Enable."; 1201}; 1202 1203/* Source: AArch64-elr_el1.xml */ 1204register ELR_EL1 rw armv8_sysreg(ELR_EL1) "Exception Link Register (EL1)" type(uint64); 1205 1206/* Source: AArch64-cnthp_ctl_el2.xml */ 1207register CNTHP_CTL_EL2 rw armv8_sysreg(CNTHP_CTL_EL2) "Counter-timer Hypervisor Physical Timer Control register" { 1208 _ 29 mbz "Reserved, RES0."; 1209 ISTATUS 1 "The status of the timer. This bit indicates whether the timer condition is met:"; 1210 IMASK 1 "Timer interrupt mask bit. Permitted values are:"; 1211 ENABLE 1 "Enables the timer. Permitted values are:"; 1212}; 1213 1214/* Source: AArch64-cntps_ctl_el1.xml */ 1215register CNTPS_CTL_EL1 rw armv8_sysreg(CNTPS_CTL_EL1) "Counter-timer Physical Secure Timer Control register" { 1216 _ 29 mbz "Reserved, RES0."; 1217 ISTATUS 1 "The status of the timer. This bit indicates whether the timer condition is met:"; 1218 IMASK 1 "Timer interrupt mask bit. Permitted values are:"; 1219 ENABLE 1 "Enables the timer. Permitted values are:"; 1220}; 1221 1222/* Source: AArch64-dbgauthstatus_el1.xml */ 1223register DBGAUTHSTATUS_EL1 ro armv8_sysreg(DBGAUTHSTATUS_EL1) "Debug Authentication Status register" { 1224 _ 24 mbz "Reserved, RES0."; 1225 SNID 2 "Secure non-invasive debug. Possible values of this field are:"; 1226 SID 2 "Secure invasive debug. Possible values of this field are:"; 1227 NSNID 2 "Non-secure non-invasive debug. Possible values of this field are:"; 1228 NSID 2 "Non-secure invasive debug. Possible values of this field are:"; 1229}; 1230 1231/* Source: AArch64-afsr0_el2.xml */ 1232register AFSR0_EL2 rw armv8_sysreg(AFSR0_EL2) "Auxiliary Fault Status Register 0 (EL2)" { 1233 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1234}; 1235 1236/* Source: AArch64-pmxevtyper_el0.xml */ 1237register PMXEVTYPER_EL0 rw armv8_sysreg(PMXEVTYPER_EL0) "Performance Monitors Selected Event Type Register" type(uint32); 1238 1239/* Source: AArch64-rmr_el3.xml */ 1240register RMR_EL3 rw armv8_sysreg(RMR_EL3) "Reset Management Register (EL3)" { 1241 _ 30 mbz "Reserved, RES0."; 1242 RR 1 "Reset Request. Setting this bit to 1 requests a Warm reset."; 1243 AA64 1 "When EL3 can use AArch32, determines which Execution state the PE boots into after a Warm reset:"; 1244}; 1245 1246/* Source: AArch64-ich_lrn_el2.xml */ 1247regtype ICH_LR_EL2_type "Interrupt Controller List Registers" { 1248 State 2 "The state of the interrupt:"; 1249 HW 1 "Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the pINTID field indicates."; 1250 Group 1 "Indicates the group for this virtual interrupt."; 1251 _ 4 mbz "Reserved, RES0."; 1252 Priority 8 "The priority of this interrupt."; 1253 _ 6 mbz "Reserved, RES0."; 1254 pINTID 10 "Physical INTID, for hardware interrupts."; 1255 vINTID 32 "Virtual INTID of the interrupt."; 1256}; 1257register ICH_LR0_EL2 rw armv8_sysreg(ICH_LR0_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1258register ICH_LR1_EL2 rw armv8_sysreg(ICH_LR1_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1259register ICH_LR2_EL2 rw armv8_sysreg(ICH_LR2_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1260register ICH_LR3_EL2 rw armv8_sysreg(ICH_LR3_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1261register ICH_LR4_EL2 rw armv8_sysreg(ICH_LR4_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1262register ICH_LR5_EL2 rw armv8_sysreg(ICH_LR5_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1263register ICH_LR6_EL2 rw armv8_sysreg(ICH_LR6_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1264register ICH_LR7_EL2 rw armv8_sysreg(ICH_LR7_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1265register ICH_LR8_EL2 rw armv8_sysreg(ICH_LR8_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1266register ICH_LR9_EL2 rw armv8_sysreg(ICH_LR9_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1267register ICH_LR10_EL2 rw armv8_sysreg(ICH_LR10_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1268register ICH_LR11_EL2 rw armv8_sysreg(ICH_LR11_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1269register ICH_LR12_EL2 rw armv8_sysreg(ICH_LR12_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1270register ICH_LR13_EL2 rw armv8_sysreg(ICH_LR13_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1271register ICH_LR14_EL2 rw armv8_sysreg(ICH_LR14_EL2) "Interrupt Controller List Registers" type(ICH_LR_EL2_type); 1272 1273/* Source: AArch64-dbgdtrrx_el0.xml */ 1274register DBGDTRRX_EL0 ro armv8_sysreg(DBGDTRRX_EL0) "Debug Data Transfer Register, Receive" type(uint32); 1275 1276/* Source: AArch64-icc_eoir0_el1.xml */ 1277register ICC_EOIR0_EL1 wo armv8_sysreg(ICC_EOIR0_EL1) "Interrupt Controller End Of Interrupt Register 0" { 1278 _ 8 mbz "Reserved, RES0."; 1279 INTID 24 "The INTID from the corresponding ICC_IAR0_EL1 access."; 1280}; 1281 1282/* Source: AArch64-ttbr0_el2.xml */ 1283register TTBR0_EL2 rw armv8_sysreg(TTBR0_EL2) "Translation Table Base Register 0 (EL2)" { 1284 ASID 16 "When HCR_EL2.E2H is 0, this field is RES0."; 1285 BADDR 47 "Translation table base address, A[47:x] or A[51:x], bits[47:1]."; 1286 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1."; 1287}; 1288 1289/* Source: AArch64-cnthv_cval_el2.xml */ 1290register CNTHV_CVAL_EL2 rw armv8_sysreg(CNTHV_CVAL_EL2) "Counter-timer Virtual Timer CompareValue register (EL2)" { 1291 CompareValue 64 "Holds the EL2 virtual timer CompareValue."; 1292}; 1293 1294/* Source: AArch64-icc_igrpen0_el1.xml */ 1295register ICC_IGRPEN0_EL1 rw armv8_sysreg(ICC_IGRPEN0_EL1) "Interrupt Controller Interrupt Group 0 Enable register" { 1296 _ 31 mbz "Reserved, RES0."; 1297 Enable 1 "Enables Group 0 interrupts."; 1298}; 1299 1300/* Source: AArch64-tpidr_el3.xml */ 1301register TPIDR_EL3 rw armv8_sysreg(TPIDR_EL3) "EL3 Software Thread ID Register" type(uint64); 1302 1303/* Source: AArch64-pan.xml */ 1304register PAN rw armv8_sysreg(PAN) "Privileged Access Never" { 1305 _ 9 mbz "Reserved, RES0."; 1306 PAN 1 "Privileged Access Never. Defined values are:"; 1307 _ 22 mbz "Reserved, RES0."; 1308}; 1309 1310/* Source: AArch64-id_isar2_el1.xml */ 1311register ID_ISAR2_EL1 ro armv8_sysreg(ID_ISAR2_EL1) "AArch32 Instruction Set Attribute Register 2" { 1312 Reversal 4 "Indicates the implemented Reversal instructions. Defined values are:"; 1313 PSR_AR 4 "Indicates the implemented A and R profile instructions to manipulate the PSR. Defined values are:"; 1314 MultU 4 "Indicates the implemented advanced unsigned Multiply instructions. Defined values are:"; 1315 MultS 4 "Indicates the implemented advanced signed Multiply instructions. Defined values are:"; 1316 Mult 4 "Indicates the implemented additional Multiply instructions. Defined values are:"; 1317 MultiAccessInt 4 "Indicates the support for interruptible multi-access instructions. Defined values are:"; 1318 MemHint 4 "Indicates the implemented Memory Hint instructions. Defined values are:"; 1319 LoadStore 4 "Indicates the implemented additional load/store instructions. Defined values are:"; 1320}; 1321 1322/* Source: AArch64-par_el1.xml */ 1323register PAR_EL1 rw armv8_sysreg(PAR_EL1) "Physical Address Register" { 1324 ATTR 8 "Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR_EL1, MAIR_EL2, and MAIR_EL3."; 1325 _ 4 mbz "Reserved, RES0."; 1326 PA_hi 4 "Extension to PA[47:12]. See PA[47:12] for more details."; 1327 PA_lo 36 "Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[47:12]."; 1328 _ 1 mb1 "Reserved, RES1."; 1329 IMP_DEF 1 "IMPLEMENTATION DEFINED."; 1330 NS 1 "Non-secure. The NS attribute for a translation table entry from a Secure translation regime."; 1331 SH 2 "Shareability attribute, for the returned output address. Permitted values are:"; 1332 _ 6 mbz "Reserved, RES0."; 1333 F 1 "Indicates whether the instruction performed a successful address translation."; 1334}; 1335 1336/* Source: AArch64-id_pfr0_el1.xml */ 1337register ID_PFR0_EL1 ro armv8_sysreg(ID_PFR0_EL1) "AArch32 Processor Feature Register 0" { 1338 RAS 4 "RAS Extension version. The defined values of this field are:"; 1339 _ 12 mbz "Reserved, RES0."; 1340 State3 4 "T32EE instruction set support. Defined values are:"; 1341 State2 4 "Jazelle extension support. Defined values are:"; 1342 State1 4 "T32 instruction set support. Defined values are:"; 1343 State0 4 "A32 instruction set support. Defined values are:"; 1344}; 1345 1346/* Source: AArch64-sder32_el3.xml */ 1347register SDER32_EL3 rw armv8_sysreg(SDER_EL3) "AArch32 Secure Debug Enable Register" { 1348 _ 30 mbz "Reserved, RES0."; 1349 SUNIDEN 1 "Secure User Non-Invasive Debug Enable:"; 1350 SUIDEN 1 "Secure User Invasive Debug Enable:"; 1351}; 1352 1353/* Source: AArch64-icc_iar1_el1.xml */ 1354register ICC_IAR1_EL1 ro armv8_sysreg(ICC_IAR1_EL1) "Interrupt Controller Interrupt Acknowledge Register 1" { 1355 _ 8 mbz "Reserved, RES0."; 1356 INTID 24 "The INTID of the signaled interrupt."; 1357}; 1358 1359/* Source: AArch64-ttbr1_el2.xml */ 1360register TTBR1_EL2 rw armv8_sysreg(TTBR1_EL2) "Translation Table Base Register 1 (EL2)" { 1361 ASID 16 "An ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID."; 1362 BADDR 47 "Translation table base address, A[47:x] or A[51:x], bits[47:1]."; 1363 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by TBR1_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1_EL2.CnP is 1."; 1364}; 1365 1366/* Source: AArch64-vbar_el1.xml */ 1367register VBAR_EL1 rw armv8_sysreg(VBAR_EL1) "Vector Base Address Register (EL1)" { 1368 None 53 "Vector Base Address. Base address of the exception vectors for exceptions taken to EL1."; 1369 _ 11 mbz "Reserved, RES0."; 1370}; 1371 1372/* Source: AArch64-dbgdtrtx_el0.xml */ 1373register DBGDTRTX_EL0 wo armv8_sysreg(DBGDTRTX_EL0) "Debug Data Transfer Register, Transmit" type(uint32); 1374 1375/* Source: AArch64-esr_el3.xml */ 1376register ESR_EL3 rw armv8_sysreg(ESR_EL3) "Exception Syndrome Register (EL3)" { 1377 EC 6 "Exception Class. Indicates the reason for the exception that this register holds information about. Possible values of this field are:"; 1378 IL 1 "Instruction Length for synchronous exceptions. Possible values of this bit are:"; 1379 ISS 25 "Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class."; 1380}; 1381 1382/* Source: AArch64-vbar_el3.xml */ 1383register VBAR_EL3 rw armv8_sysreg(VBAR_EL3) "Vector Base Address Register (EL3)" { 1384 None 53 "Vector Base Address. Base address of the exception vectors for exceptions taken to EL3."; 1385 _ 11 mbz "Reserved, RES0."; 1386}; 1387 1388/* Source: AArch64-cntv_ctl_el0.xml */ 1389register CNTV_CTL_EL0 rw armv8_sysreg(CNTV_CTL_EL02) "Counter-timer Virtual Timer Control register" { 1390 _ 29 mbz "Reserved, RES0."; 1391 ISTATUS 1 "The status of the timer. This bit indicates whether the timer condition is met:"; 1392 IMASK 1 "Timer interrupt mask bit. Permitted values are:"; 1393 ENABLE 1 "Enables the timer. Permitted values are:"; 1394}; 1395 1396/* Source: AArch64-far_el3.xml */ 1397register FAR_EL3 rw armv8_sysreg(FAR_EL3) "Fault Address Register (EL3)" type(uint64); 1398 1399/* Source: AArch64-scr_el3.xml */ 1400register SCR_EL3 rw armv8_sysreg(SCR_EL3) "Secure Configuration Register" { 1401 _ 16 mbz "Reserved, RES0."; 1402 TERR 1 "Trap Error record accesses. If the RAS Extension is implemented, the possible values of this bit are:"; 1403 TLOR 1 "Trap LOR registers. Traps accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from EL1 and EL2 to EL3, unless the access has been trapped to EL2."; 1404 TWE 1 "Traps EL2, EL1, and EL0 execution of WFE instructions to EL3, from both Security states and both Execution states."; 1405 TWI 1 "Traps EL2, EL1, and EL0 execution of WFI instructions to EL3, from both Security states and both Execution states."; 1406 ST 1 "Traps Secure EL1 accesses to the Counter-timer Physical Secure timer registers to EL3, from AArch64 state only."; 1407 RW 1 "Execution state control for lower Exception levels."; 1408 SIF 1 "Secure instruction fetch. When the PE is in Secure state, this bit disables instruction fetch from Non-secure memory. The possible values for this bit are:"; 1409 HCE 1 "Hypervisor Call instruction enable. Enables HVC instructions at EL3, EL2, and Non-secure EL1, in both Execution states."; 1410 SMD 1 "Secure Monitor Call disable. Disables SMC instructions at EL1 and above, from both Security states and both Execution states."; 1411 _ 1 mbz "Reserved, RES0."; 1412 _ 2 mb1 "Reserved, RES1."; 1413 EA 1 "External Abort and SError Interrupt Routing."; 1414 FIQ 1 "Physical FIQ Routing."; 1415 IRQ 1 "Physical IRQ Routing."; 1416 NS 1 "Non-secure bit."; 1417}; 1418 1419/* Source: AArch64-actlr_el1.xml */ 1420register ACTLR_EL1 rw armv8_sysreg(ACTLR_EL1) "Auxiliary Control Register (EL1)" { 1421 IMPLEMENTATION_DEFINED 64 "IMPLEMENTATION DEFINED."; 1422}; 1423 1424/* Source: AArch64-lorid_el1.xml */ 1425register LORID_EL1 rw armv8_sysreg(LORID_EL1) "LORegionID (EL1)" { 1426 _ 40 mbz "Reserved, RES0."; 1427 LD 8 "Number of LORegion descriptors supported by the PE. This is an 8-bit binary number."; 1428 _ 8 mbz "Reserved, RES0."; 1429 LR 8 "Number of LORegions supported by the PE. This is an 8-bit binary number."; 1430}; 1431 1432/* Source: AArch64-id_afr0_el1.xml */ 1433register ID_AFR0_EL1 ro armv8_sysreg(ID_AFR0_EL1) "AArch32 Auxiliary Feature Register 0" { 1434 _ 16 mbz "Reserved, RES0."; 1435 IMPLEMENTATION_DEFINED_4 4 "IMPLEMENTATION DEFINED."; 1436 IMPLEMENTATION_DEFINED_3 4 "IMPLEMENTATION DEFINED."; 1437 IMPLEMENTATION_DEFINED_2 4 "IMPLEMENTATION DEFINED."; 1438 IMPLEMENTATION_DEFINED_1 4 "IMPLEMENTATION DEFINED."; 1439}; 1440 1441/* Source: AArch64-afsr1_el2.xml */ 1442register AFSR1_EL2 rw armv8_sysreg(AFSR1_EL2) "Auxiliary Fault Status Register 1 (EL2)" { 1443 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1444}; 1445 1446/* Source: AArch64-sctlr_el3.xml */ 1447register SCTLR_EL3 rw armv8_sysreg(SCTLR_EL3) "System Control Register (EL3)" { 1448 _ 2 mbz "Reserved, RES0."; 1449 _ 2 mb1 "Reserved, RES1."; 1450 _ 2 mbz "Reserved, RES0."; 1451 EE 1 "Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime."; 1452 _ 1 mbz "Reserved, RES0."; 1453 _ 2 mb1 "Reserved, RES1."; 1454 IESB 1 "Implicit Error Synchronizaition Barrier enable. Permitted values are:"; 1455 _ 1 mbz "Reserved, RES0."; 1456 WXN 1 "Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:"; 1457 _ 1 mb1 "Reserved, RES1."; 1458 _ 1 mbz "Reserved, RES0."; 1459 _ 1 mb1 "Reserved, RES1."; 1460 _ 3 mbz "Reserved, RES0."; 1461 I 1 "Instruction access Cacheability control, for accesses at EL3:"; 1462 _ 1 mb1 "Reserved, RES1."; 1463 _ 5 mbz "Reserved, RES0."; 1464 _ 2 mb1 "Reserved, RES1."; 1465 SA 1 "SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see ."; 1466 C 1 "Cacheability control, for data accesses."; 1467 A 1 "Alignment check enable. This is the enable bit for Alignment fault checking at EL3:"; 1468 M 1 "MMU enable for EL3 stage 1 address translation. Possible values of this bit are:"; 1469}; 1470 1471/* Source: AArch64-icc_sgi0r_el1.xml */ 1472register ICC_SGI0R_EL1 wo armv8_sysreg(ICC_SGI0R_EL1) "Interrupt Controller Software Generated Interrupt Group 0 Register" { 1473 _ 8 mbz "Reserved, RES0."; 1474 Aff3 8 "The affinity 3 value of the affinity path of the cluster for which SGI interrupts will be generated."; 1475 _ 7 mbz "Reserved, RES0."; 1476 IRM 1 "Interrupt Routing Mode. Determines how the generated interrupts are distributed to PEs. Possible values are:"; 1477 Aff2 8 "The affinity 2 value of the affinity path of the cluster for which SGI interrupts will be generated."; 1478 _ 4 mbz "Reserved, RES0."; 1479 INTID 4 "The INTID of the SGI."; 1480 Aff1 8 "The affinity 1 value of the affinity path of the cluster for which SGI interrupts will be generated."; 1481 TargetList 16 "Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number."; 1482}; 1483 1484/* Source: AArch64-icc_bpr0_el1.xml */ 1485register ICC_BPR0_EL1 rw armv8_sysreg(ICC_BPR0_EL1) "Interrupt Controller Binary Point Register 0" { 1486 _ 29 mbz "Reserved, RES0."; 1487 BinaryPoint 3 "The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:"; 1488}; 1489 1490/* Source: AArch64-pmevtypern_el0.xml */ 1491regtype PMEVTYPER_EL0_type "Performance Monitors Event Type Registers" { 1492 P 1 "Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:"; 1493 U 1 "User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:"; 1494 NSK 1 "Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0."; 1495 NSU 1 "Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0."; 1496 NSH 1 "Non-secure EL2 (Hypervisor) filtering. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0."; 1497 M 1 "Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0."; 1498 MT 1 "Multithreading. When the implementation is multi-threaded, the valid values for this bit are:"; 1499 _ 9 mbz "Reserved, RES0."; 1500 evtCount_hi 6 "Extension to evtCount[9:0]. See evtCount[9:0] for more details."; 1501 evtCount_lo 10 "Event to count. The event number of the event that is counted by event counter PMEVCNTR<n>_EL0."; 1502}; 1503register PMEVTYPER0_EL0 rw armv8_sysreg(PMEVTYPER0_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1504register PMEVTYPER1_EL0 rw armv8_sysreg(PMEVTYPER1_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1505register PMEVTYPER2_EL0 rw armv8_sysreg(PMEVTYPER2_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1506register PMEVTYPER3_EL0 rw armv8_sysreg(PMEVTYPER3_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1507register PMEVTYPER4_EL0 rw armv8_sysreg(PMEVTYPER4_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1508register PMEVTYPER5_EL0 rw armv8_sysreg(PMEVTYPER5_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1509register PMEVTYPER6_EL0 rw armv8_sysreg(PMEVTYPER6_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1510register PMEVTYPER7_EL0 rw armv8_sysreg(PMEVTYPER7_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1511register PMEVTYPER8_EL0 rw armv8_sysreg(PMEVTYPER8_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1512register PMEVTYPER9_EL0 rw armv8_sysreg(PMEVTYPER9_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1513register PMEVTYPER10_EL0 rw armv8_sysreg(PMEVTYPER10_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1514register PMEVTYPER11_EL0 rw armv8_sysreg(PMEVTYPER11_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1515register PMEVTYPER12_EL0 rw armv8_sysreg(PMEVTYPER12_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1516register PMEVTYPER13_EL0 rw armv8_sysreg(PMEVTYPER13_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1517register PMEVTYPER14_EL0 rw armv8_sysreg(PMEVTYPER14_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1518register PMEVTYPER15_EL0 rw armv8_sysreg(PMEVTYPER15_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1519register PMEVTYPER16_EL0 rw armv8_sysreg(PMEVTYPER16_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1520register PMEVTYPER17_EL0 rw armv8_sysreg(PMEVTYPER17_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1521register PMEVTYPER18_EL0 rw armv8_sysreg(PMEVTYPER18_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1522register PMEVTYPER19_EL0 rw armv8_sysreg(PMEVTYPER19_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1523register PMEVTYPER20_EL0 rw armv8_sysreg(PMEVTYPER20_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1524register PMEVTYPER21_EL0 rw armv8_sysreg(PMEVTYPER21_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1525register PMEVTYPER22_EL0 rw armv8_sysreg(PMEVTYPER22_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1526register PMEVTYPER23_EL0 rw armv8_sysreg(PMEVTYPER23_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1527register PMEVTYPER24_EL0 rw armv8_sysreg(PMEVTYPER24_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1528register PMEVTYPER25_EL0 rw armv8_sysreg(PMEVTYPER25_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1529register PMEVTYPER26_EL0 rw armv8_sysreg(PMEVTYPER26_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1530register PMEVTYPER27_EL0 rw armv8_sysreg(PMEVTYPER27_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1531register PMEVTYPER28_EL0 rw armv8_sysreg(PMEVTYPER28_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1532register PMEVTYPER29_EL0 rw armv8_sysreg(PMEVTYPER29_EL0) "Performance Monitors Event Type Registers" type(PMEVTYPER_EL0_type); 1533 1534/* Source: AArch64-icc_igrpen1_el1.xml */ 1535register ICC_IGRPEN1_EL1 rw armv8_sysreg(ICC_IGRPEN1_EL1) "Interrupt Controller Interrupt Group 1 Enable register" { 1536 _ 31 mbz "Reserved, RES0."; 1537 Enable 1 "Enables Group 1 interrupts for the current Security state."; 1538}; 1539 1540/* Source: AArch64-spsr_fiq.xml */ 1541register SPSR_fiq rw armv8_sysreg(SPSR_fiq) "Saved Program Status Register (FIQ mode)" { 1542 N 1 "Set to the value of CPSR.N on taking an exception to FIQ mode, and copied to CPSR.N on executing an exception return operation in FIQ mode."; 1543 Z 1 "Set to the value of CPSR.Z on taking an exception to FIQ mode, and copied to CPSR.Z on executing an exception return operation in FIQ mode."; 1544 C 1 "Set to the value of CPSR.C on taking an exception to FIQ mode, and copied to CPSR.C on executing an exception return operation in FIQ mode."; 1545 V 1 "Set to the value of CPSR.V on taking an exception to FIQ mode, and copied to CPSR.V on executing an exception return operation in FIQ mode."; 1546 Q 1 "Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions."; 1547 IT_lo 2 "IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field."; 1548 J 1 "RES0."; 1549 _ 1 mbz "Reserved, RES0."; 1550 PAN 1 "When is implemented, set to the value of CPSR.PAN on taking an exception to FIQ mode, and copied to CPSR.PAN on executing an exception return operation in FIQ mode."; 1551 _ 1 mbz "Reserved, RES0."; 1552 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 1553 GE 4 "Greater than or Equal flags, for parallel addition and subtraction."; 1554 IT_hi 6 "IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts."; 1555 E 1 "Endianness state bit. Controls the load and store endianness for data accesses:"; 1556 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 1557 I 1 "IRQ mask bit. The possible values of this bit are:"; 1558 F 1 "FIQ mask bit. The possible values of this bit are:"; 1559 T 1 "T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:"; 1560 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 1561 M_lo 4 "AArch32 mode that an exception was taken from. The possible values are:"; 1562}; 1563 1564/* Source: AArch64-id_isar1_el1.xml */ 1565register ID_ISAR1_EL1 ro armv8_sysreg(ID_ISAR1_EL1) "AArch32 Instruction Set Attribute Register 1" { 1566 Jazelle 4 "Indicates the implemented Jazelle extension instructions. Defined values are:"; 1567 Interwork 4 "Indicates the implemented Interworking instructions. Defined values are:"; 1568 Immediate 4 "Indicates the implemented data-processing instructions with long immediates. Defined values are:"; 1569 IfThen 4 "Indicates the implemented If-Then instructions in the T32 instruction set. Defined values are:"; 1570 Extend 4 "Indicates the implemented Extend instructions. Defined values are:"; 1571 Except_AR 4 "Indicates the implemented A and R profile exception-handling instructions. Defined values are:"; 1572 Except 4 "Indicates the implemented exception-handling instructions in the ARM instruction set. Defined values are:"; 1573 Endian 4 "Indicates the implemented Endian instructions. Defined values are:"; 1574}; 1575 1576/* Source: AArch64-dspsr_el0.xml */ 1577register DSPSR_EL0 rw armv8_sysreg(DSPSR_EL0) "Debug Saved Program Status Register" { 1578 N 1 "Set to the value of the N condition flag on entering Debug state, and copied to the N condition flag on exiting Debug state."; 1579 Z 1 "Set to the value of the Z condition flag on entering Debug state, and copied to the Z condition flag on exiting Debug state."; 1580 C 1 "Set to the value of the C condition flag on entering Debug state, and copied to the C condition flag on exiting Debug state."; 1581 V 1 "Set to the value of the V condition flag on entering Debug state, and copied to the V condition flag on exiting Debug state."; 1582 _ 4 mbz "Reserved, RES0."; 1583 UAO 1 "When is implemented, set to the value of PSTATE.UAO on entering Debug state, and copied to PSTATE.UAO on exiting Debug state."; 1584 PAN 1 "When is implemented, set to the value of PSTATE.PAN on entering Debug state, and copied to PSTATE.PAN on exiting Debug state."; 1585 SS 1 "Software step. Shows the value of PSTATE.SS immediately before Debug state was entered."; 1586 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before Debug state was entered."; 1587 _ 10 mbz "Reserved, RES0."; 1588 D 1 "Process state D mask. The possible values of this bit are:"; 1589 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 1590 I 1 "IRQ mask bit. The possible values of this bit are:"; 1591 F 1 "FIQ mask bit. The possible values of this bit are:"; 1592 _ 1 mbz "Reserved, RES0."; 1593 M_hi 1 "Execution state that Debug state was entered from. Possible values of this bit are:"; 1594 M_lo 4 "AArch64 state (Exception level and selected SP) that Debug state was entered from. The possible values are:"; 1595}; 1596 1597/* Source: AArch64-id_aa64isar0_el1.xml */ 1598register ID_AA64ISAR0_EL1 ro armv8_sysreg(ID_AA64ISAR0_EL1) "AArch64 Instruction Set Attribute Register 0" { 1599 _ 32 mbz "Reserved, RES0."; 1600 RDM 4 "SQRDMLAH and SQRDMLSH instructions implemented in AArch64 state. Defined values are:"; 1601 _ 4 mbz "Reserved, RES0."; 1602 Atomic 4 "Atomic instructions implemented in AArch64 state. Defined values are:"; 1603 CRC32 4 "CRC32 instructions implemented in AArch64 state. Defined values are:"; 1604 SHA2 4 "SHA2 instructions implemented in AArch64 state. Defined values are:"; 1605 SHA1 4 "SHA1 instructions implemented in AArch64 state. Defined values are:"; 1606 AES 4 "AES instructions implemented in AArch64 state. Defined values are:"; 1607 _ 4 mbz "Reserved, RES0."; 1608}; 1609 1610/* Source: AArch64-id_aa64pfr0_el1.xml */ 1611register ID_AA64PFR0_EL1 ro armv8_sysreg(ID_AA64PFR0_EL1) "AArch64 Processor Feature Register 0" { 1612 _ 28 mbz "Reserved, RES0."; 1613 SVE 4 "Scalable Vector Extension. Defined values are:"; 1614 RAS 4 "RAS Extension version. The defined values of this field are:"; 1615 GIC 4 "System register GIC interface support. Defined values are:"; 1616 AdvSIMD 4 type(ID_FEATURE) "Advanced SIMD. Defined values are:"; 1617 FP 4 type(ID_FEATURE) "Floating-point. Defined values are:"; 1618 EL3 4 type(EL_IMPLEMENTED) "EL3 Exception level handling. Defined values are:"; 1619 EL2 4 type(EL_IMPLEMENTED) "EL2 Exception level handling. Defined values are:"; 1620 EL1 4 type(EL_IMPLEMENTED) "EL1 Exception level handling. Defined values are:"; 1621 EL0 4 type(EL_IMPLEMENTED) "EL0 Exception level handling. Defined values are:"; 1622}; 1623 1624/* Source: AArch64-rvbar_el1.xml */ 1625register RVBAR_EL1 ro armv8_sysreg(RVBAR_EL1) "Reset Vector Base Address Register (if EL2 and EL3 not implemented)" type(uint64); 1626 1627/* Source: AArch64-dczid_el0.xml */ 1628register DCZID_EL0 ro armv8_sysreg(DCZID_EL0) "Data Cache Zero ID register" { 1629 _ 27 mbz "Reserved, RES0."; 1630 DZP 1 "Data Zero prohibited. Permitted values are:"; 1631 BS 4 "Log2 of the block size in words. The maximum size supported is 2KB (value == 9)."; 1632}; 1633 1634/* Source: AArch64-id_dfr0_el1.xml */ 1635register ID_DFR0_EL1 ro armv8_sysreg(ID_DFR0_EL1) "AArch32 Debug Feature Register 0" { 1636 _ 4 mbz "Reserved, RES0."; 1637 PerfMon 4 "Performance Monitors. Support for System registers-based ARM Performance Monitors Extension, using registers in the coproc == 1111 encoding space, for A and R profile processors. Defined values are:"; 1638 MProfDbg 4 "M Profile Debug. Support for memory-mapped debug model for M profile processors. Defined values are:"; 1639 MMapTrc 4 "Memory Mapped Trace. Support for memory-mapped trace model. Defined values are:"; 1640 CopTrc 4 "Support for System registers-based trace model, using registers in the coproc == 1110 encoding space. Defined values are:"; 1641 MMapDbg 4 "Memory Mapped Debug. Support for v7 memory-mapped debug model, for A and R profile processors."; 1642 CopSDbg 4 "Support for a System registers-based Secure debug model, using registers in the coproc = 1110 encoding space, for an A profile processor that includes EL3."; 1643 CopDbg 4 "Support for System registers-based debug model, using registers in the coproc == 1110 encoding space, for A and R profile processors. Defined values are:"; 1644}; 1645 1646/* Source: AArch64-spsr_el2.xml */ 1647register SPSR_EL2 rw armv8_sysreg(SPSR_EL2) "Saved Program Status Register (EL2)" { 1648 N 1 "Set to the value of the N condition flag on taking an exception to EL2, and copied to the N condition flag on executing an exception return operation in EL2."; 1649 Z 1 "Set to the value of the Z condition flag on taking an exception to EL2, and copied to the Z condition flag on executing an exception return operation in EL2."; 1650 C 1 "Set to the value of the C condition flag on taking an exception to EL2, and copied to the C condition flag on executing an exception return operation in EL2."; 1651 V 1 "Set to the value of the V condition flag on taking an exception to EL2, and copied to the V condition flag on executing an exception return operation in EL2."; 1652 _ 4 mbz "Reserved, RES0."; 1653 UAO 1 "When is implemented, set to the value of PSTATE.UAO on taking an exception to EL2, and copied to PSTATE.UAO on executing an exception return operation in EL2."; 1654 PAN 1 "When is implemented, set to the value of PSTATE.PAN on taking an exception to EL2, and copied to PSTATE.PAN on executing an exception return operation in EL2."; 1655 SS 1 "Software step. Shows the value of PSTATE.SS immediately before the exception was taken."; 1656 IL 1 "Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken."; 1657 _ 10 mbz "Reserved, RES0."; 1658 D 1 "Process state D mask. The possible values of this bit are:"; 1659 A 1 "SError interrupt mask bit. The possible values of this bit are:"; 1660 I 1 "IRQ mask bit. The possible values of this bit are:"; 1661 F 1 "FIQ mask bit. The possible values of this bit are:"; 1662 _ 1 mbz "Reserved, RES0."; 1663 M_hi 1 "Execution state that the exception was taken from. Possible values of this bit are:"; 1664 M_lo 4 "AArch64 state (Exception level and selected SP) that an exception was taken from. The possible values are:"; 1665}; 1666 1667/* Source: AArch64-mdccsr_el0.xml */ 1668register MDCCSR_EL0 ro armv8_sysreg(MDCCSR_EL0) "Monitor DCC Status Register" { 1669 _ 1 mbz "Reserved, RES0."; 1670 RXfull 1 "DTRRX full. Read-only view of the equivalent bit in the EDSCR."; 1671 TXfull 1 "DTRTX full. Read-only view of the equivalent bit in the EDSCR."; 1672 _ 10 mbz "Reserved, RES0."; 1673 _ 4 mbz "RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register."; 1674 _ 2 mbz "Reserved, RES0."; 1675 _ 1 mbz "RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register."; 1676 _ 6 mbz "Reserved, RES0."; 1677 _ 4 mbz "RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register."; 1678 _ 2 mbz "Reserved, RES0."; 1679}; 1680 1681/* Source: AArch64-ttbr0_el1.xml */ 1682register TTBR0_EL1 rw armv8_sysreg(TTBR0_EL1) "Translation Table Base Register 0 (EL1)" { 1683 ASID 16 "An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID."; 1684 BADDR 47 "Translation table base address, A[47:x] or A[51:x], bits[47:1]."; 1685 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by TTBR0_EL1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL1.CnP is 1."; 1686}; 1687 1688/* Source: AArch64-pmceid1_el0.xml */ 1689register PMCEID1_EL0 ro armv8_sysreg(PMCEID1_EL0) "Performance Monitors Common Event Identification register 1" { 1690 ID_hi 32 "PMCEID1_EL0[63:32] maps to common events 0x4020 to 0x403F. For a list of event numbers and descriptions, see ."; 1691 ID_lo 32 "PMCEID1_EL0[31:0] maps to common events 0x0020 to 0x003F. For a list of event numbers and descriptions, see ."; 1692}; 1693 1694/* Source: AArch64-ich_ap1rn_el2.xml */ 1695regtype ICH_AP1R_EL2_type "Interrupt Controller Hyp Active Priorities Group 1 Registers" { 1696 P 32 "Group 1 interrupt active priorities. Possible values of each bit are:"; 1697}; 1698register ICH_AP1R0_EL2 rw armv8_sysreg(ICH_AP1R0_EL2) "Interrupt Controller Hyp Active Priorities Group 1 Registers" type(ICH_AP1R_EL2_type); 1699register ICH_AP1R1_EL2 rw armv8_sysreg(ICH_AP1R1_EL2) "Interrupt Controller Hyp Active Priorities Group 1 Registers" type(ICH_AP1R_EL2_type); 1700register ICH_AP1R2_EL2 rw armv8_sysreg(ICH_AP1R2_EL2) "Interrupt Controller Hyp Active Priorities Group 1 Registers" type(ICH_AP1R_EL2_type); 1701 1702/* Source: AArch64-icc_pmr_el1.xml */ 1703register ICC_PMR_EL1 rw armv8_sysreg(ICC_PMR_EL1) "Interrupt Controller Interrupt Priority Mask Register" { 1704 _ 24 mbz "Reserved, RES0."; 1705 Priority 8 "The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE."; 1706}; 1707 1708/* Source: AArch64-hacr_el2.xml */ 1709register HACR_EL2 rw armv8_sysreg(HACR_EL2) "Hypervisor Auxiliary Control Register" { 1710 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1711}; 1712 1713/* Source: AArch64-icc_ap1rn_el1.xml */ 1714regtype ICC_AP1R_EL1_type "Interrupt Controller Active Priorities Group 1 Registers" { 1715 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1716}; 1717register ICC_AP1R0_EL1 rw armv8_sysreg(ICC_AP1R0_EL1) "Interrupt Controller Active Priorities Group 1 Registers" type(ICC_AP1R_EL1_type); 1718register ICC_AP1R1_EL1 rw armv8_sysreg(ICC_AP1R1_EL1) "Interrupt Controller Active Priorities Group 1 Registers" type(ICC_AP1R_EL1_type); 1719register ICC_AP1R2_EL1 rw armv8_sysreg(ICC_AP1R2_EL1) "Interrupt Controller Active Priorities Group 1 Registers" type(ICC_AP1R_EL1_type); 1720 1721/* Source: AArch64-ich_misr_el2.xml */ 1722register ICH_MISR_EL2 ro armv8_sysreg(ICH_MISR_EL2) "Interrupt Controller Maintenance Interrupt State Register" { 1723 _ 24 mbz "Reserved, RES0."; 1724 VGrp1D 1 "vPE Group 1 Disabled."; 1725 VGrp1E 1 "vPE Group 1 Enabled."; 1726 VGrp0D 1 "vPE Group 0 Disabled."; 1727 VGrp0E 1 "vPE Group 0 Enabled."; 1728 NP 1 "No Pending."; 1729 LRENP 1 "List Register Entry Not Present."; 1730 U 1 "Underflow."; 1731 EOI 1 "End Of Interrupt."; 1732}; 1733 1734/* Source: AArch64-id_aa64isar1_el1.xml */ 1735register ID_AA64ISAR1_EL1 ro armv8_sysreg(ID_AA64ISAR1_EL1) "AArch64 Instruction Set Attribute Register 1" { 1736 _ 60 mbz "Reserved, RES0."; 1737 DPB 4 "Indicates support for the DC CVAP instruction in AArch64 state. Defined values are:"; 1738}; 1739 1740/* Source: AArch64-cptr_el3.xml */ 1741register CPTR_EL3 rw armv8_sysreg(CPTR_EL3) "Architectural Feature Trap Register (EL3)" { 1742 TCPAC 1 "Traps all of the following to EL3, from both Security states and both Execution states."; 1743 _ 10 mbz "Reserved, RES0."; 1744 TTA 1 "Traps System register accesses to the trace registers, from all Exception levels, both Security states, and both Execution states, to EL3."; 1745 _ 9 mbz "Reserved, RES0."; 1746 TFP 1 "Traps all accesses to SVE, Advanced SIMD and floating-point functionality, from all Exception levels, both Security states, and both Execution states, to EL3. Defined values are:"; 1747 _ 1 mbz "Reserved, RES0."; 1748 EZ 1 "Present only if is implemented."; 1749 _ 8 mbz "Reserved, RES0."; 1750}; 1751 1752/* Source: AArch64-hcr_el2.xml */ 1753register HCR_EL2 rw armv8_sysreg(HCR_EL2) "Hypervisor Configuration Register" { 1754 _ 25 mbz "Reserved, RES0."; 1755 MIOCNCE 1 "Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1&0 translation regime."; 1756 TEA 1 "Route synchronous External Abort exceptions to EL2. If the RAS Extension is implemented, the possible values of this bit are:"; 1757 TERR 1 "Trap Error record accesses. If the RAS Extension is implemented, the possible values of this bit are:"; 1758 TLOR 1 "Trap LOR registers. Traps accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from Non-secure EL1 to EL2."; 1759 E2H 1 "EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System's applications are running in EL0."; 1760 ID 1 "Stage 2 Instruction access cacheability disable. For the Non-secure EL1&0 translation regime, when HCR_EL2.VM==1, this control forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable."; 1761 CD 1 "Stage 2 Data access cacheability disable. For the Non-secure EL1&0 translation regime, when HCR_EL2.VM==1, this control forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable."; 1762 RW 1 "Execution state control for lower Exception levels:"; 1763 TRVM 1 "Trap Reads of Virtual Memory controls. Traps Non-secure EL1 reads of the virtual memory control registers to EL2, from both Execution states. The registers for which read accesses are trapped are as follows:"; 1764 HCD 1 "HVC instruction disable. Disables Non-secure state execution of HVC instructions, from both Execution states."; 1765 TDZ 1 "Trap DC ZVA instructions. Traps Non-secure EL0 and EL1 execution of DC ZVA instructions to EL2, from AArch64 state only."; 1766 TGE 1 "Trap General Exceptions, from Non-secure EL0."; 1767 TVM 1 "Trap Virtual Memory controls. Traps Non-secure EL1 writes to the virtual memory control registers to EL2, from both Execution states. The registers for which write accesses are trapped are as follows:"; 1768 TTLB 1 "Trap TLB maintenance instructions. Traps Non-secure EL1 execution of TLB maintenance instructions to EL2, from both Execution states. This applies to the following instructions:"; 1769 TPU 1 "Trap cache maintenance instructions that operate to the Point of Unification. Traps execution of those cache maintenance instructions at Non-secure EL1 or EL0 using AArch64, and at Non-secure EL1 using AArch32, to EL2. This applies to the following instructions:"; 1770 TPCP 1 "Trap data or unified cache maintenance instructions that operate to the Point of Coherency or Persistence. Traps execution of those cache maintenance instructions at Non-secure EL1 or EL0 using AArch64, and at Non-secure EL1 using AArch32, to EL2. This applies to the following instructions:"; 1771 TSW 1 "Trap data or unified cache maintenance instructions that operate by Set/Way. Traps execution of those cache maintenance instructions at Non-secure EL1 using AArch64, and at Non-secure EL1 using AArch32, to EL2. This applies to the following instructions:"; 1772 TACR 1 "Trap Auxiliary Control Registers. Traps Non-secure EL1 accesses to the Auxiliary Control Registers to EL2, from both Execution states. This applies to the following register accesses:"; 1773 TIDCP 1 "Trap IMPLEMENTATION DEFINED functionality. Traps Non-secure EL1 accesses to the encodings reserved for IMPLEMENTATION DEFINED functionality to EL2. This applies to the following register accesses:"; 1774 TSC 1 "Trap SMC instructions. Traps Non-secure EL1 execution of SMC instructions to EL2, from both Execution states."; 1775 TID3 1 "Trap ID group 3. Traps Non-secure EL1 reads of the following registers to EL2:"; 1776 TID2 1 "Trap ID group 2. Traps the following register accesses to EL2:"; 1777 TID1 1 "Trap ID group 1. Traps Non-secure EL1 reads of the following registers are trapped to EL2:"; 1778 TID0 1 "Trap ID group 0. Traps the following register accesses to EL2:"; 1779 TWE 1 "Traps Non-secure EL0 and EL1 execution of WFE instructions to EL2, from both Execution states."; 1780 TWI 1 "Traps Non-secure EL0 and EL1 execution of WFI instructions to EL2, from both Execution states."; 1781 DC 1 "This field is permitted to be cached in a TLB."; 1782 BSU 2 "Barrier Shareability upgrade. This field determines the minimum shareability domain that is applied to any barrier instruction executed from Non-secure EL1 or Non-secure EL0:"; 1783 FB 1 "Force broadcast. Causes the following instructions to be broadcast within the Inner Shareable domain when executed from Non-secure EL1:"; 1784 VSE 1 "Virtual SError interrupt."; 1785 VI 1 "Virtual IRQ Interrupt."; 1786 VF 1 "Virtual FIQ Interrupt."; 1787 AMO 1 "Physical SError Interrupt routing."; 1788 IMO 1 "Physical IRQ Routing."; 1789 FMO 1 "Physical FIQ Routing."; 1790 PTW 1 "Protected Table Walk. In the Non-secure EL1&0 translation regime, a translation table access made as part of a stage 1 translation table walk is subject to a stage 2 translation. The combining of the memory type attributes from the two stages of translation means the access might be made to a type of Device memory. If this occurs then the value of this bit determines the behavior:"; 1791 SWIO 1 "Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way:"; 1792 VM 1 "Virtualization enable. Enables stage 2 address translation for the Non-secure EL1&0 translation regime. Possible values of this bit are:"; 1793}; 1794 1795/* Source: AArch64-sctlr_el2.xml */ 1796register SCTLR_EL2 rw armv8_sysreg(SCTLR_EL2) "System Control Register (EL2)" { 1797 _ 2 mbz "Reserved, RES0."; 1798 _ 2 mb1 "Reserved, RES1."; 1799 _ 2 mbz "Reserved, RES0."; 1800 EE 1 "Endianness of data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&0 translation regime, and stage 2 translation table walks in the EL1&0 translation regime."; 1801 _ 1 mbz "Reserved, RES0."; 1802 _ 2 mb1 "Reserved, RES1."; 1803 _ 2 mbz "Reserved, RES0."; 1804 WXN 1 "Write permission implies XN (Execute-never). For the EL2 or EL2&0 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:"; 1805 _ 1 mb1 "Reserved, RES1."; 1806 _ 1 mbz "Reserved, RES0."; 1807 _ 1 mb1 "Reserved, RES1."; 1808 _ 3 mbz "Reserved, RES0."; 1809 I 1 "Instruction access Cacheability control, for accesses at EL2:"; 1810 _ 1 mb1 "Reserved, RES1."; 1811 _ 5 mbz "Reserved, RES0."; 1812 _ 2 mb1 "Reserved, RES1."; 1813 SA 1 "SP Alignment check enable. When set to 1, if a load or store instruction executed at EL2 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see ."; 1814 C 1 "Cacheability control, for data accesses."; 1815 A 1 "Alignment check enable. This is the enable bit for Alignment fault checking at EL2:"; 1816 M 1 "MMU enable for EL2 stage 1 address translation. Possible values of this bit are:"; 1817}; 1818 1819/* Source: AArch64-rvbar_el3.xml */ 1820register RVBAR_EL3 ro armv8_sysreg(RVBAR_EL3) "Reset Vector Base Address Register (if EL3 implemented)" type(uint64); 1821 1822/* Source: AArch64-mpidr_el1.xml */ 1823register MPIDR_EL1 ro armv8_sysreg(MPIDR_EL1) "Multiprocessor Affinity Register" { 1824 _ 24 mbz "Reserved, RES0."; 1825 Aff3 8 "Affinity level 3. Highest level affinity field."; 1826 _ 1 mb1 "Reserved, RES1."; 1827 U 1 "Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:"; 1828 _ 5 mbz "Reserved, RES0."; 1829 MT 1 "Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. The possible values of this bit are:"; 1830 Aff2 8 "Affinity level 2. Second highest level affinity field."; 1831 Aff1 8 "Affinity level 1. Third highest level affinity field."; 1832 Aff0 8 "Affinity level 0. Lowest level affinity field."; 1833}; 1834 1835/* Source: AArch64-dbgclaimset_el1.xml */ 1836register DBGCLAIMSET_EL1 rw armv8_sysreg(DBGCLAIMSET_EL1) "Debug Claim Tag Set register" { 1837 _ 24 mbz "Reserved, RAZ/SBZ. Software can rely on these bits reading as zero, and must use a should-be-zero policy on writes. Implementations must ignore writes."; 1838 CLAIM 8 "Set CLAIM tag bits. RAO."; 1839}; 1840 1841/* Source: AArch64-id_aa64dfr0_el1.xml */ 1842register ID_AA64DFR0_EL1 ro armv8_sysreg(ID_AA64DFR0_EL1) "AArch64 Debug Feature Register 0" { 1843 _ 28 mbz "Reserved, RES0."; 1844 PMSVer 4 "Statistical Profiling Extension version. When the Statistical Profiling Extension is implemented, the defined values of this field are:"; 1845 CTX_CMPs 4 "Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints."; 1846 _ 4 mbz "Reserved, RES0."; 1847 WRPs 4 "Number of watchpoints, minus 1. The value of 0b0000 is reserved."; 1848 _ 4 mbz "Reserved, RES0."; 1849 BRPs 4 "Number of breakpoints, minus 1. The value of 0b0000 is reserved."; 1850 PMUVer 4 "Performance Monitors Extension version. Indicates whether System register interface to Performance Monitors extension is implemented. Defined values are:"; 1851 TraceVer 4 "Trace support. Indicates whether System register interface to a trace macrocell is implemented. Defined values are:"; 1852 DebugVer 4 "Debug architecture version. Indicates presence of ARMv8 debug architecture."; 1853}; 1854 1855/* Source: AArch64-id_pfr1_el1.xml */ 1856register ID_PFR1_EL1 ro armv8_sysreg(ID_PFR1_EL1) "AArch32 Processor Feature Register 1" { 1857 GIC 4 "System register GIC CPU interface. Defined values are:"; 1858 Virt_frac 4 "Virtualization fractional field. When the Virtualization field is 0000, determines the support for features from the ARMv7 Virtualization Extensions. Defined values are:"; 1859 Sec_frac 4 "Security fractional field. When the Security field is 0000, determines the support for features from the ARMv7 Security Extensions. Defined values are:"; 1860 GenTimer 4 "Generic Timer support. Defined values are:"; 1861 Virtualization 4 "Virtualization support. Defined values are:"; 1862 MProgMod 4 "M profile programmers' model support. Defined values are:"; 1863 Security 4 "Security support. Defined values are:"; 1864 ProgMod 4 "Support for the standard programmers' model for ARMv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes. Defined values are:"; 1865}; 1866 1867/* Source: AArch64-vmpidr_el2.xml */ 1868register VMPIDR_EL2 rw armv8_sysreg(VMPIDR_EL2) "Virtualization Multiprocessor ID Register" { 1869 _ 24 mbz "Reserved, RES0."; 1870 Aff3 8 "Affinity level 3. Highest level affinity field."; 1871 _ 1 mb1 "Reserved, RES1."; 1872 U 1 "Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:"; 1873 _ 5 mbz "Reserved, RES0."; 1874 MT 1 "Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. The possible values of this bit are:"; 1875 Aff2 8 "Affinity level 2. Second highest level affinity field."; 1876 Aff1 8 "Affinity level 1. Third highest level affinity field."; 1877 Aff0 8 "Affinity level 0. Lowest level affinity field."; 1878}; 1879 1880/* Source: AArch64-afsr0_el1.xml */ 1881register AFSR0_EL1 rw armv8_sysreg(AFSR0_EL1) "Auxiliary Fault Status Register 0 (EL1)" { 1882 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1883}; 1884 1885/* Source: AArch64-dbgwvrn_el1.xml */ 1886regtype DBGWVR_EL1_type "Debug Watchpoint Value Registers" { 1887 RESS_lo 11 "Reserved, Sign extended. Hardware and software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1."; 1888 VA_hi 4 "Extension to VA[48:2]. See VA[48:2] for more details."; 1889 VA_lo 47 "Bits[48:2] of the address value for comparison."; 1890 _ 2 mbz "Reserved, RES0."; 1891}; 1892register DBGWVR0_EL1 rw armv8_sysreg(DBGWVR0_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1893register DBGWVR1_EL1 rw armv8_sysreg(DBGWVR1_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1894register DBGWVR2_EL1 rw armv8_sysreg(DBGWVR2_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1895register DBGWVR3_EL1 rw armv8_sysreg(DBGWVR3_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1896register DBGWVR4_EL1 rw armv8_sysreg(DBGWVR4_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1897register DBGWVR5_EL1 rw armv8_sysreg(DBGWVR5_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1898register DBGWVR6_EL1 rw armv8_sysreg(DBGWVR6_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1899register DBGWVR7_EL1 rw armv8_sysreg(DBGWVR7_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1900register DBGWVR8_EL1 rw armv8_sysreg(DBGWVR8_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1901register DBGWVR9_EL1 rw armv8_sysreg(DBGWVR9_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1902register DBGWVR10_EL1 rw armv8_sysreg(DBGWVR10_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1903register DBGWVR11_EL1 rw armv8_sysreg(DBGWVR11_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1904register DBGWVR12_EL1 rw armv8_sysreg(DBGWVR12_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1905register DBGWVR13_EL1 rw armv8_sysreg(DBGWVR13_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1906register DBGWVR14_EL1 rw armv8_sysreg(DBGWVR14_EL1) "Debug Watchpoint Value Registers" type(DBGWVR_EL1_type); 1907 1908/* Source: AArch64-pmccntr_el0.xml */ 1909register PMCCNTR_EL0 rw armv8_sysreg(PMCCNTR_EL0) "Performance Monitors Cycle Count Register" { 1910 CCNT 64 "Cycle count. Depending on the values of PMCR_EL0.{LC,D}, this field increments in one of the following ways:"; 1911}; 1912 1913/* Source: AArch64-nzcv.xml */ 1914register NZCV rw armv8_sysreg(NZCV) "Condition Flags" { 1915 N 1 "Negative condition flag. Set to 1 if the result of the last flag-setting instruction was negative."; 1916 Z 1 "Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison."; 1917 C 1 "Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition."; 1918 V 1 "Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition."; 1919 _ 28 mbz "Reserved, RES0."; 1920}; 1921 1922/* Source: AArch64-mdccint_el1.xml */ 1923register MDCCINT_EL1 rw armv8_sysreg(MDCCINT_EL1) "Monitor DCC Interrupt Enable Register" { 1924 _ 1 mbz "Reserved, RES0."; 1925 RX 1 "DCC interrupt request enable control for DTRRX. Enables a common COMMIRQ interrupt request to be signaled based on the DCC status flags."; 1926 TX 1 "DCC interrupt request enable control for DTRTX. Enables a common COMMIRQ interrupt request to be signaled based on the DCC status flags."; 1927 _ 29 mbz "Reserved, RES0."; 1928}; 1929 1930/* Source: AArch64-icc_hppir1_el1.xml */ 1931register ICC_HPPIR1_EL1 ro armv8_sysreg(ICC_HPPIR1_EL1) "Interrupt Controller Highest Priority Pending Interrupt Register 1" { 1932 _ 8 mbz "Reserved, RES0."; 1933 INTID 24 "The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level."; 1934}; 1935 1936/* Source: AArch64-osdtrrx_el1.xml */ 1937register OSDTRRX_EL1 rw armv8_sysreg(OSDTRRX_EL1) "OS Lock Data Transfer Register, Receive" type(uint32); 1938 1939/* Source: AArch64-csselr_el1.xml */ 1940register CSSELR_EL1 rw armv8_sysreg(CSSELR_EL1) "Cache Size Selection Register" { 1941 _ 28 mbz "Reserved, RES0."; 1942 Level 3 "Cache level of required cache. Permitted values are:"; 1943 InD 1 "Instruction not Data bit. Permitted values are:"; 1944}; 1945 1946/* Source: AArch64-pmcntenset_el0.xml */ 1947register PMCNTENSET_EL0 rw armv8_sysreg(PMCNTENSET_EL0) "Performance Monitors Count Enable Set register" { 1948 C 1 "PMCCNTR_EL0 enable bit. Enables the cycle counter register. Possible values are:"; 1949 P 31 "Event counter enable bit for PMEVCNTR<n>_EL0."; 1950}; 1951 1952/* Source: AArch64-afsr1_el3.xml */ 1953register AFSR1_EL3 rw armv8_sysreg(AFSR1_EL3) "Auxiliary Fault Status Register 1 (EL3)" { 1954 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 1955}; 1956 1957/* Source: AArch64-cnthp_cval_el2.xml */ 1958register CNTHP_CVAL_EL2 rw armv8_sysreg(CNTHP_CVAL_EL2) "Counter-timer Hypervisor Physical Timer CompareValue register" { 1959 CompareValue 64 "Holds the EL2 physical timer CompareValue."; 1960}; 1961 1962/* Source: AArch64-mvfr2_el1.xml */ 1963register MVFR2_EL1 ro armv8_sysreg(MVFR2_EL1) "AArch32 Media and VFP Feature Register 2" { 1964 _ 24 mbz "Reserved, RES0."; 1965 FPMisc 4 "Indicates whether the floating-point implementation provides support for miscellaneous VFP features."; 1966 SIMDMisc 4 "Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features."; 1967}; 1968 1969/* Source: AArch64-oslar_el1.xml */ 1970register OSLAR_EL1 wo armv8_sysreg(OSLAR_EL1) "OS Lock Access Register" { 1971 _ 31 mbz "Reserved, RES0."; 1972 OSLK 1 "On writes to OSLAR_EL1, bit[0] is copied to the OS lock."; 1973}; 1974 1975/* Source: AArch64-ttbr1_el1.xml */ 1976register TTBR1_EL1 rw armv8_sysreg(TTBR1_EL1) "Translation Table Base Register 1 (EL1)" { 1977 ASID 16 "An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID."; 1978 BADDR 47 "Translation table base address, A[47:x] or A[51:x], bits[47:1]."; 1979 CnP 1 "Common not Private. In an implementation that includes , indicates whether each entry that is pointed to by TBR1_EL1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1_EL1.CnP is 1."; 1980}; 1981 1982/* Source: AArch64-fpexc32_el2.xml */ 1983register FPEXC32_EL2 rw armv8_sysreg(FPEXC32_EL2) "Floating-Point Exception Control register" { 1984 EX 1 "Exception bit. In ARMv8, this bit is RAZ/WI."; 1985 EN 1 "Enables access to the Advanced SIMD and floating-point functionality from all Exception levels, except that setting this field to 0 does not disable the following:"; 1986 DEX 1 "Defined synchronous exception on floating-point execution."; 1987 FP2V 1 "FPINST2 instruction valid bit. In ARMv8, this bit is RES0."; 1988 VV 1 "VECITR valid bit. In ARMv8, this bit is RES0."; 1989 TFV 1 "Trapped Fault Valid bit. Valid only when the value of FPEXC.DEX is 1. When valid, it indicates the cause of the exception and therefore whether the FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} bits are valid."; 1990 _ 15 mbz "Reserved, RES0."; 1991 VECITR 3 "Vector iteration count. In ARMv8, this field is RES1."; 1992 IDF 1 "Input Denormal trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Input Denormal exception occurred while FPSCR.IDE was 1:"; 1993 _ 2 mbz "Reserved, RES0."; 1994 IXF 1 "Inexact trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Inexact exception occurred while FPSCR.IXE was 1:"; 1995 UFF 1 "Underflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Underflow exception occurred while FPSCR.UFE was 1:"; 1996 OFF 1 "Overflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Overflow exception occurred while FPSCR.OFE was 1:"; 1997 DZF 1 "Divide by Zero trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether a Divide by Zero exception occurred while FPSCR.DZE was 1:"; 1998 IOF 1 "Invalid Operation trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Invalid Operation exception occurred while FPSCR.IOE was 1:"; 1999}; 2000 2001/* Source: AArch64-id_aa64mmfr2_el1.xml */ 2002register ID_AA64MMFR2_EL1 ro armv8_sysreg(ID_AA64MMFR2_EL1) "AArch64 Memory Model Feature Register 2" { 2003 _ 44 mbz "Reserved, RES0."; 2004 VARange 4 "Indicates support for a larger virtual address. Defined values are:"; 2005 IESB 4 "Indicates whether the implicit Error Synchronization Barrier operations are implemented. Defined values are:"; 2006 LSM 4 "Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. Defined values are:"; 2007 UAO 4 "User Access Override. Defined values are:"; 2008 CnP 4 "Common not Private translations. Defined values are:"; 2009}; 2010 2011/* Source: AArch64-cntv_cval_el0.xml */ 2012register CNTV_CVAL_EL0 rw armv8_sysreg(CNTV_CVAL_EL02) "Counter-timer Virtual Timer CompareValue register" { 2013 CompareValue 64 "Holds the EL1 virtual timer CompareValue."; 2014}; 2015 2016/* Source: AArch64-tpidr_el1.xml */ 2017register TPIDR_EL1 rw armv8_sysreg(TPIDR_EL1) "EL1 Software Thread ID Register" type(uint64); 2018 2019/* Source: AArch64-ich_eisr_el2.xml */ 2020register ICH_EISR_EL2 ro armv8_sysreg(ICH_EISR_EL2) "Interrupt Controller End of Interrupt Status Register" { 2021 _ 16 mbz "Reserved, RES0."; 2022 Status 16 "EOI maintenance interrupt status bit for List register <n>:"; 2023}; 2024 2025/* Source: AArch64-ccsidr_el1.xml */ 2026register CCSIDR_EL1 ro armv8_sysreg(CCSIDR_EL1) "Current Cache Size ID Register" { 2027 UNKNOWN 4 "Reserved, UNKNOWN."; 2028 NumSets 15 "(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2."; 2029 Associativity 10 "(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2."; 2030 LineSize 3 "(Log2(Number of bytes in cache line)) - 4. For example:"; 2031}; 2032 2033/* Source: AArch64-cntp_ctl_el0.xml */ 2034register CNTP_CTL_EL0 rw armv8_sysreg(CNTP_CTL_EL0) "Counter-timer Physical Timer Control register" { 2035 _ 29 mbz "Reserved, RES0."; 2036 ISTATUS 1 "The status of the timer. This bit indicates whether the timer condition is met:"; 2037 IMASK 1 "Timer interrupt mask bit. Permitted values are:"; 2038 ENABLE 1 "Enables the timer. Permitted values are:"; 2039}; 2040 2041/* Source: AArch64-id_mmfr1_el1.xml */ 2042register ID_MMFR1_EL1 ro armv8_sysreg(ID_MMFR1_EL1) "AArch32 Memory Model Feature Register 1" { 2043 BPred 4 "Branch Predictor. Indicates branch predictor management requirements. Defined values are:"; 2044 L1TstCln 4 "Level 1 cache Test and Clean. Indicates the supported Level 1 data cache test and clean operations, for Harvard or unified cache implementations. Defined values are:"; 2045 L1Uni 4 "Level 1 Unified cache. Indicates the supported entire Level 1 cache maintenance operations for a unified cache implementation. Defined values are:"; 2046 L1Hvd 4 "Level 1 Harvard cache. Indicates the supported entire Level 1 cache maintenance operations for a Harvard cache implementation. Defined values are:"; 2047 L1UniSW 4 "Level 1 Unified cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a unified cache implementation. Defined values are:"; 2048 L1HvdSW 4 "Level 1 Harvard cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard cache implementation. Defined values are:"; 2049 L1UniVA 4 "Level 1 Unified cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a unified cache implementation. Defined values are:"; 2050 L1HvdVA 4 "Level 1 Harvard cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a Harvard cache implementation. Defined values are:"; 2051}; 2052 2053/* Source: AArch64-ich_elrsr_el2.xml */ 2054register ICH_ELRSR_EL2 ro armv8_sysreg(ICH_ELRSR_EL2) "Interrupt Controller Empty List Register Status Register" { 2055 _ 16 mbz "Reserved, RES0."; 2056 Status 16 "Status bit for List register <n>, ICH_LR<n>_EL2:"; 2057}; 2058 2059/* Source: AArch64-sp_el1.xml */ 2060register SP_EL1 rw armv8_sysreg(SP_EL1) "Stack Pointer (EL1)" type(uint64); 2061 2062/* Source: AArch64-cnthctl_el2.xml */ 2063register CNTHCTL_EL2 rw armv8_sysreg(CNTHCTL_EL2) "Counter-timer Hypervisor Control register" { 2064 _ 24 mbz "Reserved, RES0."; 2065 EVNTI 4 "Selects which bit (0 to 15) of the counter register CNTPCT_EL0 is the trigger for the event stream generated from that counter, when that stream is enabled."; 2066 EVNTDIR 1 "Controls which transition of the counter register CNTPCT_EL0 trigger bit, defined by EVNTI, generates an event when the event stream is enabled:"; 2067 EVNTEN 1 "Enables the generation of an event stream from the counter register CNTPCT_EL0:"; 2068 EL1PCEN 1 "Traps Non-secure EL0 and EL1 accesses to the physical timer registers to EL2."; 2069 EL1PCTEN 1 "Traps Non-secure EL0 and EL1 accesses to the physical counter register to EL2."; 2070}; 2071 2072/* Source: AArch64-pmcr_el0.xml */ 2073register PMCR_EL0 rw armv8_sysreg(PMCR_EL0) "Performance Monitors Control Register" { 2074 IMP 8 "Implementer code. This field is RO with an IMPLEMENTATION DEFINED value."; 2075 IDCODE 8 "Identification code. This field is RO with an IMPLEMENTATION DEFINED value."; 2076 N 5 "Number of event counters. A RO field that indicates the number counters implemented. A value of 0b00000 in this field indicates that only the Cycle Count Register PMCCNTR_EL0 is implemented."; 2077 _ 4 mbz "Reserved, RES0."; 2078 LC 1 "Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31]."; 2079 DP 1 "Disable cycle counter when event counting is prohibited. The possible values of this bit are:"; 2080 X 1 "Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are:"; 2081 D 1 "Clock divider. The possible values of this bit are:"; 2082 C 1 "Cycle counter reset. This bit is WO. The effects of writing to this bit are:"; 2083 P 1 "Event counter reset. This bit is WO. The effects of writing to this bit are:"; 2084 E 1 "Enable. The possible values of this bit are:"; 2085}; 2086 2087/* Source: AArch64-dbgwcrn_el1.xml */ 2088regtype DBGWCR_EL1_type "Debug Watchpoint Control Registers" { 2089 _ 3 mbz "Reserved, RES0."; 2090 MASK 5 "Address mask. Only objects up to 2GB can be watched using a single mask."; 2091 _ 3 mbz "Reserved, RES0."; 2092 WT 1 "Watchpoint type. Possible values are:"; 2093 LBN 4 "Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to."; 2094 SSC 2 "Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields."; 2095 HMC 1 "Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields."; 2096 BAS 8 "Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched."; 2097 LSC 2 "Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:"; 2098 PAC 2 "Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields."; 2099 E 1 "Enable watchpoint n. Possible values are:"; 2100}; 2101register DBGWCR0_EL1 rw armv8_sysreg(DBGWCR0_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2102register DBGWCR1_EL1 rw armv8_sysreg(DBGWCR1_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2103register DBGWCR2_EL1 rw armv8_sysreg(DBGWCR2_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2104register DBGWCR3_EL1 rw armv8_sysreg(DBGWCR3_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2105register DBGWCR4_EL1 rw armv8_sysreg(DBGWCR4_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2106register DBGWCR5_EL1 rw armv8_sysreg(DBGWCR5_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2107register DBGWCR6_EL1 rw armv8_sysreg(DBGWCR6_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2108register DBGWCR7_EL1 rw armv8_sysreg(DBGWCR7_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2109register DBGWCR8_EL1 rw armv8_sysreg(DBGWCR8_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2110register DBGWCR9_EL1 rw armv8_sysreg(DBGWCR9_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2111register DBGWCR10_EL1 rw armv8_sysreg(DBGWCR10_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2112register DBGWCR11_EL1 rw armv8_sysreg(DBGWCR11_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2113register DBGWCR12_EL1 rw armv8_sysreg(DBGWCR12_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2114register DBGWCR13_EL1 rw armv8_sysreg(DBGWCR13_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2115register DBGWCR14_EL1 rw armv8_sysreg(DBGWCR14_EL1) "Debug Watchpoint Control Registers" type(DBGWCR_EL1_type); 2116 2117/* Source: AArch64-clidr_el1.xml */ 2118register CLIDR_EL1 ro armv8_sysreg(CLIDR_EL1) "Cache Level ID Register" { 2119 _ 31 mbz "Reserved, RES0."; 2120 ICB 3 "Inner cache boundary. This field indicates the boundary for caching Inner Cacheable memory regions."; 2121 LoUU 3 "Level of Unification Uniprocessor for the cache hierarchy."; 2122 LoC 3 "Level of Coherence for the cache hierarchy."; 2123 LoUIS 3 "Level of Unification Inner Shareable for the cache hierarchy."; 2124 Ctype 21 "Cache Type fields. Indicate the type of cache that is implemented and can be managed using the architected cache maintenance instructions that operate by set/way at each level, from Level 1 up to a maximum of seven levels of cache hierarchy. Possible values of each field are:"; 2125}; 2126 2127/* Source: AArch64-sp_el0.xml */ 2128register SP_EL0 rw armv8_sysreg(SP_EL0) "Stack Pointer (EL0)" type(uint64); 2129 2130/* Source: AArch64-cntfrq_el0.xml */ 2131register CNTFRQ_EL0 rw armv8_sysreg(CNTFRQ_EL0) "Counter-timer Frequency register" type(uint32); 2132 2133/* Source: AArch64-cntp_cval_el0.xml */ 2134register CNTP_CVAL_EL0 rw armv8_sysreg(CNTP_CVAL_EL0) "Counter-timer Physical Timer CompareValue register" { 2135 CompareValue 64 "Holds the EL1 physical timer CompareValue."; 2136}; 2137 2138/* Source: AArch64-cntvct_el0.xml */ 2139register CNTVCT_EL0 ro armv8_sysreg(CNTVCT_EL0) "Counter-timer Virtual Count register" type(uint64); 2140 2141/* Source: AArch64-midr_el1.xml */ 2142register MIDR_EL1 ro armv8_sysreg(MIDR_EL1) "Main ID Register" { 2143 Implementer 8 "The Implementer code. This field must hold an implementer code that has been assigned by ARM. Assigned codes include the following:"; 2144 Variant 4 "An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product."; 2145 Architecture 4 "The permitted values of this field are:"; 2146 PartNum 12 "An IMPLEMENTATION DEFINED primary part number for the device."; 2147 Revision 4 "An IMPLEMENTATION DEFINED revision number for the device."; 2148}; 2149 2150/* Source: AArch64-icc_sre_el3.xml */ 2151register ICC_SRE_EL3 rw armv8_sysreg(ICC_SRE_EL3) "Interrupt Controller System Register Enable register (EL3)" { 2152 _ 28 mbz "Reserved, RES0."; 2153 Enable 1 "Enable. Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2."; 2154 DIB 1 "Disable IRQ bypass."; 2155 DFB 1 "Disable FIQ bypass."; 2156 SRE 1 "System Register Enable."; 2157}; 2158 2159/* Source: AArch64-id_mmfr3_el1.xml */ 2160register ID_MMFR3_EL1 ro armv8_sysreg(ID_MMFR3_EL1) "AArch32 Memory Model Feature Register 3" { 2161 Supersec 4 "Supersections. On a VMSA implementation, indicates whether Supersections are supported. Defined values are:"; 2162 CMemSz 4 "Cached Memory Size. Indicates the physical memory size supported by the caches. Defined values are:"; 2163 CohWalk 4 "Coherent Walk. Indicates whether Translation table updates require a clean to the point of unification. Defined values are:"; 2164 PAN 4 "Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32. Defined values are:"; 2165 MaintBcst 4 "Maintenance Broadcast. Indicates whether Cache, TLB, and branch predictor operations are broadcast. Defined values are:"; 2166 BPMaint 4 "Branch Predictor Maintenance. Indicates the supported branch predictor maintenance operations in an implementation with hierarchical cache maintenance operations. Defined values are:"; 2167 CMaintSW 4 "Cache Maintenance by Set/Way. Indicates the supported cache maintenance operations by set/way, in an implementation with hierarchical caches. Defined values are:"; 2168 CMaintVA 4 "Cache Maintenance by Virtual Address. Indicates the supported cache maintenance operations by VA, in an implementation with hierarchical caches. Defined values are:"; 2169}; 2170 2171/* Source: AArch64-esr_el2.xml */ 2172register ESR_EL2 rw armv8_sysreg(ESR_EL2) "Exception Syndrome Register (EL2)" { 2173 EC 6 "Exception Class. Indicates the reason for the exception that this register holds information about. Possible values of this field are:"; 2174 IL 1 "Instruction Length for synchronous exceptions. Possible values of this bit are:"; 2175 ISS 25 "Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class."; 2176}; 2177 2178/* Source: AArch64-afsr1_el1.xml */ 2179register AFSR1_EL1 rw armv8_sysreg(AFSR1_EL1) "Auxiliary Fault Status Register 1 (EL1)" { 2180 IMPLEMENTATION_DEFINED 32 "IMPLEMENTATION DEFINED."; 2181}; 2182 2183/* Source: AArch64-pmcntenclr_el0.xml */ 2184register PMCNTENCLR_EL0 rw armv8_sysreg(PMCNTENCLR_EL0) "Performance Monitors Count Enable Clear register" { 2185 C 1 "PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are:"; 2186 P 31 "Event counter disable bit for PMEVCNTR<n>_EL0."; 2187}; 2188 2189/* Source: AArch64-dbgbcrn_el1.xml */ 2190regtype DBGBCR_EL1_type "Debug Breakpoint Control Registers" { 2191 _ 8 mbz "Reserved, RES0."; 2192 BT 4 "Breakpoint Type. Possible values are:"; 2193 LBN 4 "Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to."; 2194 SSC 2 "Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information, including the effect of programming the fields to a reserved set of values, see ."; 2195 HMC 1 "Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the SSC, bits [15:14] description."; 2196 _ 4 mbz "Reserved, RES0."; 2197 BAS 4 "Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and Execution state. In an AArch64-only implementation, this field is reserved, RES1."; 2198 _ 2 mbz "Reserved, RES0."; 2199 PMC 2 "Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>_EL1.SSC description."; 2200 E 1 "Enable breakpoint DBGBVR<n>_EL1. Possible values are:"; 2201}; 2202register DBGBCR0_EL1 rw armv8_sysreg(DBGBCR0_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2203register DBGBCR1_EL1 rw armv8_sysreg(DBGBCR1_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2204register DBGBCR2_EL1 rw armv8_sysreg(DBGBCR2_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2205register DBGBCR3_EL1 rw armv8_sysreg(DBGBCR3_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2206register DBGBCR4_EL1 rw armv8_sysreg(DBGBCR4_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2207register DBGBCR5_EL1 rw armv8_sysreg(DBGBCR5_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2208register DBGBCR6_EL1 rw armv8_sysreg(DBGBCR6_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2209register DBGBCR7_EL1 rw armv8_sysreg(DBGBCR7_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2210register DBGBCR8_EL1 rw armv8_sysreg(DBGBCR8_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2211register DBGBCR9_EL1 rw armv8_sysreg(DBGBCR9_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2212register DBGBCR10_EL1 rw armv8_sysreg(DBGBCR10_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2213register DBGBCR11_EL1 rw armv8_sysreg(DBGBCR11_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2214register DBGBCR12_EL1 rw armv8_sysreg(DBGBCR12_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2215register DBGBCR13_EL1 rw armv8_sysreg(DBGBCR13_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2216register DBGBCR14_EL1 rw armv8_sysreg(DBGBCR14_EL1) "Debug Breakpoint Control Registers" type(DBGBCR_EL1_type); 2217 2218/* Source: AArch64-isr_el1.xml */ 2219register ISR_EL1 ro armv8_sysreg(ISR_EL1) "Interrupt Status Register" { 2220 _ 23 mbz "Reserved, RES0."; 2221 A 1 "SError interrupt pending bit:"; 2222 I 1 "IRQ pending bit. Indicates whether an IRQ interrupt is pending:"; 2223 F 1 "FIQ pending bit. Indicates whether an FIQ interrupt is pending."; 2224 _ 6 mbz "Reserved, RES0."; 2225}; 2226 2227/* Source: AArch64-id_aa64afr0_el1.xml */ 2228register ID_AA64AFR0_EL1 ro armv8_sysreg(ID_AA64AFR0_EL1) "AArch64 Auxiliary Feature Register 0" { 2229 _ 32 mbz "Reserved, RES0."; 2230 IMPLEMENTATION_DEFINED_8 4 "IMPLEMENTATION DEFINED."; 2231 IMPLEMENTATION_DEFINED_7 4 "IMPLEMENTATION DEFINED."; 2232 IMPLEMENTATION_DEFINED_6 4 "IMPLEMENTATION DEFINED."; 2233 IMPLEMENTATION_DEFINED_5 4 "IMPLEMENTATION DEFINED."; 2234 IMPLEMENTATION_DEFINED_4 4 "IMPLEMENTATION DEFINED."; 2235 IMPLEMENTATION_DEFINED_3 4 "IMPLEMENTATION DEFINED."; 2236 IMPLEMENTATION_DEFINED_2 4 "IMPLEMENTATION DEFINED."; 2237 IMPLEMENTATION_DEFINED_1 4 "IMPLEMENTATION DEFINED."; 2238}; 2239 2240/* Source: AArch64-dbgbvrn_el1.xml */ 2241regtype DBGBVR_EL1_type "Debug Breakpoint Value Registers" { 2242 RESS_lo 11 "Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1."; 2243 VA_hi 4 "Extension to VA[48:2]. See VA[48:2] for more details."; 2244 VA_lo 47 "Bits[48:2] of the address value for comparison."; 2245 _ 2 mbz "Reserved, RES0."; 2246}; 2247register DBGBVR0_EL1 rw armv8_sysreg(DBGBVR0_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2248register DBGBVR1_EL1 rw armv8_sysreg(DBGBVR1_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2249register DBGBVR2_EL1 rw armv8_sysreg(DBGBVR2_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2250register DBGBVR3_EL1 rw armv8_sysreg(DBGBVR3_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2251register DBGBVR4_EL1 rw armv8_sysreg(DBGBVR4_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2252register DBGBVR5_EL1 rw armv8_sysreg(DBGBVR5_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2253register DBGBVR6_EL1 rw armv8_sysreg(DBGBVR6_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2254register DBGBVR7_EL1 rw armv8_sysreg(DBGBVR7_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2255register DBGBVR8_EL1 rw armv8_sysreg(DBGBVR8_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2256register DBGBVR9_EL1 rw armv8_sysreg(DBGBVR9_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2257register DBGBVR10_EL1 rw armv8_sysreg(DBGBVR10_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2258register DBGBVR11_EL1 rw armv8_sysreg(DBGBVR11_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2259register DBGBVR12_EL1 rw armv8_sysreg(DBGBVR12_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2260register DBGBVR13_EL1 rw armv8_sysreg(DBGBVR13_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2261register DBGBVR14_EL1 rw armv8_sysreg(DBGBVR14_EL1) "Debug Breakpoint Value Registers" type(DBGBVR_EL1_type); 2262 2263/* Source: AArch64-pmccfiltr_el0.xml */ 2264register PMCCFILTR_EL0 rw armv8_sysreg(PMCCFILTR_EL0) "Performance Monitors Cycle Count Filter Register" { 2265 P 1 "Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:"; 2266 U 1 "User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:"; 2267 NSK 1 "Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0."; 2268 NSU 1 "Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0."; 2269 NSH 1 "Non-secure EL2 (Hypervisor) filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0."; 2270 M 1 "Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0."; 2271 _ 26 mbz "Reserved, RES0."; 2272}; 2273 2274/* Source: AArch64-cntv_tval_el0.xml */ 2275register CNTV_TVAL_EL0 rw armv8_sysreg(CNTV_TVAL_EL02) "Counter-timer Virtual Timer TimerValue register" { 2276 TimerValue 32 "The TimerValue view of the EL1 virtual timer."; 2277}; 2278 2279/* Source: AArch64-icc_bpr1_el1.xml */ 2280register ICC_BPR1_EL1 rw armv8_sysreg(ICC_BPR1_EL1) "Interrupt Controller Binary Point Register 1" { 2281 _ 29 mbz "Reserved, RES0."; 2282 BinaryPoint 3 "If the GIC is configured to use separate binary point fields for Group 0 and Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. For more information about priorities, see ."; 2283}; 2284 2285/* Source: AArch64-elr_el2.xml */ 2286register ELR_EL2 rw armv8_sysreg(ELR_EL2) "Exception Link Register (EL2)" type(uint64); 2287 2288/* Source: AArch64-icc_sre_el1.xml */ 2289register ICC_SRE_EL1 rw armv8_sysreg(ICC_SRE_EL1) "Interrupt Controller System Register Enable register (EL1)" { 2290 _ 29 mbz "Reserved, RES0."; 2291 DIB 1 "Disable IRQ bypass."; 2292 DFB 1 "Disable FIQ bypass."; 2293 SRE 1 "System Register Enable."; 2294}; 2295 2296/* Source: AArch64-lorsa_el1.xml */ 2297register LORSA_EL1 rw armv8_sysreg(LORSA_EL1) "LORegion Start Address (EL1)" { 2298 _ 12 mbz "Reserved, RES0."; 2299 SA_hi 4 "Extension to SA[47:16]. See SA[47:16] for more details."; 2300 SA_lo 32 "Bits [47:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS. Bits[15:0] of this address are defined to be 0x0000."; 2301 _ 15 mbz "Reserved, RES0."; 2302 Valid 1 "Indicates whether the current LORegion Descriptor is enabled."; 2303}; 2304 2305/* Source: AArch64-cntp_tval_el0.xml */ 2306register CNTP_TVAL_EL0 rw armv8_sysreg(CNTP_TVAL_EL0) "Counter-timer Physical Timer TimerValue register" { 2307 TimerValue 32 "The TimerValue view of the EL1 physical timer."; 2308}; 2309 2310/* Source: AArch64-mdscr_el1.xml */ 2311register MDSCR_EL1 rw armv8_sysreg(MDSCR_EL1) "Monitor Debug System Control Register" { 2312 _ 1 mbz "Reserved, RES0."; 2313 RXfull 1 "Used for save/restore of EDSCR.RXfull."; 2314 TXfull 1 "Used for save/restore of EDSCR.TXfull."; 2315 _ 1 mbz "Reserved, RES0."; 2316 RXO 1 "Used for save/restore of EDSCR.RXO."; 2317 TXU 1 "Used for save/restore of EDSCR.TXU."; 2318 _ 2 mbz "Reserved, RES0."; 2319 INTdis 2 "Used for save/restore of EDSCR.INTdis."; 2320 TDA 1 "Used for save/restore of EDSCR.TDA."; 2321 _ 1 mbz "Reserved, RES0."; 2322 _ 1 mbz "Reserved, RES0."; 2323 _ 3 mbz "RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register."; 2324 MDE 1 "Monitor debug events. Enable Breakpoint, Watchpoint, and Vector Catch exceptions."; 2325 HDE 1 "Used for save/restore of EDSCR.HDE."; 2326 KDE 1 "Local (kernel) debug enable. If ELD is using AArch64, enable debug exceptions within ELD. Permitted values are:"; 2327 TDCC 1 "Traps EL0 accesses to the DCC registers to EL1, from both Execution states:"; 2328 _ 5 mbz "Reserved, RES0."; 2329 ERR 1 "Used for save/restore of EDSCR.ERR."; 2330 _ 5 mbz "Reserved, RES0."; 2331 SS 1 "Software step control bit. If ELD is using AArch64, enable Software step. Permitted values are:"; 2332}; 2333 2334/* Source: AArch64-cnthv_ctl_el2.xml */ 2335register CNTHV_CTL_EL2 rw armv8_sysreg(CNTHV_CTL_EL2) "Counter-timer Virtual Timer Control register (EL2)" { 2336 _ 29 mbz "Reserved, RES0."; 2337 ISTATUS 1 "The status of the timer. This bit indicates whether the timer condition is met:"; 2338 IMASK 1 "Timer interrupt mask bit. Permitted values are:"; 2339 ENABLE 1 "Enables the timer. Permitted values are:"; 2340}; 2341 2342/* Source: AArch64-icc_asgi1r_el1.xml */ 2343register ICC_ASGI1R_EL1 wo armv8_sysreg(ICC_ASGI1R_EL1) "Interrupt Controller Alias Software Generated Interrupt Group 1 Register" { 2344 _ 8 mbz "Reserved, RES0."; 2345 Aff3 8 "The affinity 3 value of the affinity path of the cluster for which SGI interrupts will be generated."; 2346 _ 7 mbz "Reserved, RES0."; 2347 IRM 1 "Interrupt Routing Mode. Determines how the generated interrupts are distributed to PEs. Possible values are:"; 2348 Aff2 8 "The affinity 2 value of the affinity path of the cluster for which SGI interrupts will be generated."; 2349 _ 4 mbz "Reserved, RES0."; 2350 INTID 4 "The INTID of the SGI."; 2351 Aff1 8 "The affinity 1 value of the affinity path of the cluster for which SGI interrupts will be generated."; 2352 TargetList 16 "Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number."; 2353}; 2354 2355/* Source: AArch64-pmovsset_el0.xml */ 2356register PMOVSSET_EL0 rw armv8_sysreg(PMOVSSET_EL0) "Performance Monitors Overflow Flag Status Set register" { 2357 C 1 "PMCCNTR_EL0 overflow bit. Possible values are:"; 2358 P 31 "Event counter overflow set bit for PMEVCNTR<n>_EL0."; 2359}; 2360 2361/* Source: AArch64-pmovsclr_el0.xml */ 2362register PMOVSCLR_EL0 rw armv8_sysreg(PMOVSCLR_EL0) "Performance Monitors Overflow Flag Status Clear Register" { 2363 C 1 "PMCCNTR_EL0 overflow bit. Possible values are:"; 2364 P 31 "Event counter overflow clear bit for PMEVCNTR<n>_EL0."; 2365}; 2366 2367/* Source: AArch64-lorea_el1.xml */ 2368register LOREA_EL1 rw armv8_sysreg(LOREA_EL1) "LORegion End Address (EL1)" { 2369 _ 12 mbz "Reserved, RES0."; 2370 EA_hi 4 "Extension to EA[47:16]. See EA[47:16] for more details."; 2371 EA_lo 32 "Bits [47:16] of the end physical address of an LORegion described in the current LORegion descriptor selected by LORC_EL1.DS. Bits[15:0] of this address are defined to be 0xFFFF."; 2372 _ 16 mbz "Reserved, RES0."; 2373}; 2374 2375/* Source: AArch64-cpacr_el1.xml */ 2376register CPACR_EL1 rw armv8_sysreg(CPACR_EL1) "Architectural Feature Access Control Register" { 2377 _ 3 mbz "Reserved, RES0."; 2378 TTA 1 "Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1, or to EL2 when SCR_EL3.NS is 1 and HCR_EL2.TGE is 1, from both Execution states."; 2379 _ 6 mbz "Reserved, RES0."; 2380 FPEN 2 type(fpen) "Traps EL0 and EL1 accesses to the SVE, Advanced SIMD, and floating-point registers to EL1, or to EL2 when SCR_EL3.NS is 1 and HCR_EL2.TGE is 1, from both Execution states, unless SVE is implemented and they are trapped by CPACR_EL1.ZEN."; 2381 _ 2 mbz "Reserved, RES0."; 2382 ZEN 2 "Traps SVE instructions and instructions that access SVE System registers at EL0 and EL1 to EL1, or to EL2 when SCR_EL3.NS and HCR_EL2.TGE are both 1. Defined values are:"; 2383 _ 16 mbz "Reserved, RES0."; 2384}; 2385 2386/* Source: AArch64-vbar_el2.xml */ 2387register VBAR_EL2 rw armv8_sysreg(VBAR_EL2) "Vector Base Address Register (EL2)" { 2388 None 53 "Vector Base Address. Base address of the exception vectors for exceptions taken to EL2."; 2389 _ 11 mbz "Reserved, RES0."; 2390}; 2391 2392};