1/*
2 * Copyright (c) 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * arm.dev
11 *
12 * DESCRIPTION: ARM architecture definitions
13 * 
14 * See:
15 *   ARM Architecture Reference Manual
16 */
17
18device arm msbfirst () "ARM architecture" {
19
20    // A.2.5
21    regtype status "Status register" {
22	n	1 "Negative result";
23	z	1 "Zero result";
24	c	1 "Carry";
25	v	1 "Overflow";
26	q	1 "DSP overflow";
27	_	19;
28	i	1 "IRQ disable";
29	f	1 "FIQ disable";
30	t	1 "Thumb mode";
31	m	5 type(cpu_mode) "Mode";
32    };
33    constants cpu_mode "CPU mode bits" {
34	user	= 0b10000 "User";
35	fiq	= 0b10001 "FIQ";
36	irq	= 0b10010 "IRQ";
37	super	= 0b10011 "Supervisor";
38	abort	= 0b10111 "Abort";
39	undef	= 0b11011 "Undefined";
40	system  = 0b11111 "System";
41    };
42
43    // A.2.6
44    constants exc_vector "Exception vector addresses" {
45	vec_reset	= 0x00000000 "Reset";
46	vec_undef	= 0x00000004 "Undefined instruction";
47	vec_swi		= 0x00000008 "Software interrupt";
48	vec_pref_abort	= 0x0000000C "Prefetch abort";
49	vec_data_abort	= 0x00000010 "Data abort";
50	vec_irq		= 0x00000018 "Interrupt";
51	vec_fiq		= 0x0000001C "Fast interrupt";
52    };
53
54    space cp15(reg, opcode) valuewise "Coprocessor 15";
55
56    // B.2.4
57    register control rw cp15(0x01) "CP15 control register" {
58	_	16 mbz;
59	l4	1 "Backwards compatible loads";
60	rr	1 "Predictable cache replacement strategy";
61	v	1 "High exception vectors enable";
62	i	1 "Instruction cache enable";
63	z	1 "Branch prediction enable";
64	f	1 "Implementation defined";
65	r	1 "ROM protection bit";
66	s	1 "System protection bit";
67	b	1 "Big endian";
68	l	1 "Late abort model";
69	d	1 "26-bit address exception checking";
70	p	1 "26/32-bit exception handler mode";
71	w	1 "Write buffer enable";
72	c	1 "Data or unified cache enable";
73	a	1 "Alignment fault checking enable";
74	m	1 "MMU enable";
75    };
76
77    // 
78    // Memory Management Unit functions
79    // 
80
81    // B.3.6.1
82    constants fault_type "Faulting access type" {
83	terminal	= 0b0010 "Terminal exception";
84	vector		= 0b0000 "Vector exception";
85	alignment	= 0b0001 "Alignment";
86	alignment_2	= 0b0011 "Alternate alignment";
87	l1extabort	= 0b1100 "Level 1 external abort on translation";
88	l2extabort	= 0b1110 "Level 2 external abort on translation";
89	sec_trans	= 0b0101 "Section translation";
90	page_trans	= 0b0111 "Page transation";
91	sec_dom		= 0b1001 "Section domain";
92	page_dom	= 0b1011 "Page domain";
93	sec_perm	= 0b1101 "Section permissions";
94	page_perm	= 0b1111 "Page permissions";
95	sec_linef	= 0b0100 "Section external abort on linefetch";
96	page_linef	= 0b0110 "Page external abort on linefetch";
97	sec_nlinef	= 0b1000 "Section external abort on non-linefetch";
98	page_nlinef	= 0b1010 "Page external abort on non-linefetch";
99    };
100
101	
102    // B.3.7.2
103    register ttbase rw cp15(0x02) "Translation table base" {
104	base	18 "Base address high bits";
105	_	14 mbz;
106    };
107
108    // B.3.7.3
109    register domacc rw cp15(0x03) "Domain access control" type(uint32);
110    
111    // B.3.7.5 
112    register faultstat rw cp15(0x05) "Fault status" {
113	_	23 mbz;
114	_	1 mbz;
115	domain	4 "Faulting domain";
116	status	4 type(fault_type) "Access type";
117    };
118
119    // 3.7.6
120    register faultaddr rw cp15(6) "Fault address" type(uint32);
121
122    // 3.7.7 XXX opcode2, and CRm dependent
123    register tlbfunc wo cp15(8) "TLB functions" type(uint32);
124    
125    // 3.7.8 XXX opcode2, and CRm dependent
126    register tlblock rw cp15(10) "TLB lockdown" {
127	entry	31 "Base and victim (variable width)";
128	p	1  "Protected from CP8 invalidates";
129    };
130};
131
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