1/* 2 * Copyright (c) 2009, ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10device amd_vmcb lsbfirst ( addr base ) "AMD Virtual Machine Control Block" 11{ 12 register cr_access addr(base, 0x000) "Intercept reads/writes to CR0-15" { 13 rdcr0 1 "Intercept reads of CR0"; 14 rdcr1 1 "Intercept reads of CR1"; 15 rdcr2 1 "Intercept reads of CR2"; 16 rdcr3 1 "Intercept reads of CR3"; 17 rdcr4 1 "Intercept reads of CR4"; 18 rdcr5 1 "Intercept reads of CR5"; 19 rdcr6 1 "Intercept reads of CR6"; 20 rdcr7 1 "Intercept reads of CR7"; 21 rdcr8 1 "Intercept reads of CR8"; 22 rdcr9 1 "Intercept reads of CR9"; 23 rdcr10 1 "Intercept reads of CR10"; 24 rdcr11 1 "Intercept reads of CR11"; 25 rdcr12 1 "Intercept reads of CR12"; 26 rdcr13 1 "Intercept reads of CR13"; 27 rdcr14 1 "Intercept reads of CR14"; 28 rdcr15 1 "Intercept reads of CR15"; 29 wrcr0 1 "Intercept writes of CR0"; 30 wrcr1 1 "Intercept writes of CR1"; 31 wrcr2 1 "Intercept writes of CR2"; 32 wrcr3 1 "Intercept writes of CR3"; 33 wrcr4 1 "Intercept writes of CR4"; 34 wrcr5 1 "Intercept writes of CR5"; 35 wrcr6 1 "Intercept writes of CR6"; 36 wrcr7 1 "Intercept writes of CR7"; 37 wrcr8 1 "Intercept writes of CR8"; 38 wrcr9 1 "Intercept writes of CR9"; 39 wrcr10 1 "Intercept writes of CR10"; 40 wrcr11 1 "Intercept writes of CR11"; 41 wrcr12 1 "Intercept writes of CR12"; 42 wrcr13 1 "Intercept writes of CR13"; 43 wrcr14 1 "Intercept writes of CR14"; 44 wrcr15 1 "Intercept writes of CR15"; 45 }; 46 47 register dr_access addr(base, 0x004) "Intercept reads/writes to DR0-15" { 48 rddr0 1 "Intercept reads of DR0"; 49 rddr1 1 "Intercept reads of DR1"; 50 rddr2 1 "Intercept reads of DR2"; 51 rddr3 1 "Intercept reads of DR3"; 52 rddr4 1 "Intercept reads of DR4"; 53 rddr5 1 "Intercept reads of DR5"; 54 rddr6 1 "Intercept reads of DR6"; 55 rddr7 1 "Intercept reads of DR7"; 56 rddr8 1 "Intercept reads of DR8"; 57 rddr9 1 "Intercept reads of DR9"; 58 rddr10 1 "Intercept reads of DR10"; 59 rddr11 1 "Intercept reads of DR11"; 60 rddr12 1 "Intercept reads of DR12"; 61 rddr13 1 "Intercept reads of DR13"; 62 rddr14 1 "Intercept reads of DR14"; 63 rddr15 1 "Intercept reads of DR15"; 64 wrdr0 1 "Intercept writes of DR0"; 65 wrdr1 1 "Intercept writes of DR1"; 66 wrdr2 1 "Intercept writes of DR2"; 67 wrdr3 1 "Intercept writes of DR3"; 68 wrdr4 1 "Intercept writes of DR4"; 69 wrdr5 1 "Intercept writes of DR5"; 70 wrdr6 1 "Intercept writes of DR6"; 71 wrdr7 1 "Intercept writes of DR7"; 72 wrdr8 1 "Intercept writes of DR8"; 73 wrdr9 1 "Intercept writes of DR9"; 74 wrdr10 1 "Intercept writes of DR10"; 75 wrdr11 1 "Intercept writes of DR11"; 76 wrdr12 1 "Intercept writes of DR12"; 77 wrdr13 1 "Intercept writes of DR13"; 78 wrdr14 1 "Intercept writes of DR14"; 79 wrdr15 1 "Intercept writes of DR15"; 80 }; 81 82 register exceptions addr(base, 0x008) "Intercept exception vectors 0-31" { 83 vector0 1 "Intercept exception vector 0"; 84 vector1 1 "Intercept exception vector 1"; 85 vector2 1 "Intercept exception vector 2"; 86 vector3 1 "Intercept exception vector 3"; 87 vector4 1 "Intercept exception vector 4"; 88 vector5 1 "Intercept exception vector 5"; 89 vector6 1 "Intercept exception vector 6"; 90 vector7 1 "Intercept exception vector 7"; 91 vector8 1 "Intercept exception vector 8"; 92 vector9 1 "Intercept exception vector 9"; 93 vector10 1 "Intercept exception vector 10"; 94 vector11 1 "Intercept exception vector 11"; 95 vector12 1 "Intercept exception vector 12"; 96 vector13 1 "Intercept exception vector 13"; 97 vector14 1 "Intercept exception vector 14"; 98 vector15 1 "Intercept exception vector 15"; 99 vector16 1 "Intercept exception vector 16"; 100 vector17 1 "Intercept exception vector 17"; 101 vector18 1 "Intercept exception vector 18"; 102 vector19 1 "Intercept exception vector 19"; 103 vector20 1 "Intercept exception vector 20"; 104 vector21 1 "Intercept exception vector 21"; 105 vector22 1 "Intercept exception vector 22"; 106 vector23 1 "Intercept exception vector 23"; 107 vector24 1 "Intercept exception vector 24"; 108 vector25 1 "Intercept exception vector 25"; 109 vector26 1 "Intercept exception vector 26"; 110 vector27 1 "Intercept exception vector 27"; 111 vector28 1 "Intercept exception vector 28"; 112 vector29 1 "Intercept exception vector 29"; 113 vector30 1 "Intercept exception vector 30"; 114 vector31 1 "Intercept exception vector 31"; 115 }; 116 117 register intercepts addr(base, 0x00c) "Various intercepts" { 118 intr 1 "Intercept INTR instruction"; 119 nmi 1 "Intercept NMI instruction"; 120 smi 1 "Intercept SMI instruction"; 121 init 1 "Intercept INIT instruction"; 122 vintr 1 "Intercept VINTR instruction"; 123 wrcr0 1 "Intercept CR0 writes that change bits other than TS or MP"; 124 rdidtr 1 "Intercept reads of IDTR"; 125 rdgdtr 1 "Intercept reads of GDTR"; 126 rdldtr 1 "Intercept reads of LDTR"; 127 rdtr 1 "Intercept reads of TR"; 128 wridtr 1 "Intercept writes of IDRT"; 129 wrgdtr 1 "Intercept writes of GDTR"; 130 wrldtr 1 "Intercept writes of LDTR"; 131 wrtr 1 "Intercept writes of TR"; 132 rdtsc 1 "Intercept RDTSC instruction"; 133 rdpmc 1 "Intercept RDPMC instruction"; 134 pushf 1 "Intercept PUSHF instruction"; 135 popf 1 "Intercept POPF instruction"; 136 cpuid 1 "Intercept CPUID instruction"; 137 rsm 1 "Intercept RSM instruction"; 138 iret 1 "Intercept IRET instruction"; 139 intn 1 "Intercept INTn instruction"; 140 invd 1 "Intercept INVD instruction"; 141 pause 1 "Intercept PAUSE instruction"; 142 hlt 1 "Intercept HLT instruction"; 143 invlpg 1 "Intercept INVLPG instruction"; 144 invlpga 1 "Intercept INVLPGA instruction"; 145 ioio_prot 1 "Intercept IN/OUT accesses to selected ports"; 146 msr_prot 1 "Intercept RDMSR or WRMSR accesses to selected MSRs"; 147 task_switch 1 "Intercept task switches"; 148 ferr_freeze 1 "Intercept processor freezing durich legacy FERR handling"; 149 shutdown 1 "Intercept shutdown events"; 150 vmrun 1 "Intercept VMRUN instruction"; 151 vmmcall 1 "Intercept VMMCALL instruction"; 152 vmload 1 "Intercept VMLOAD instruction"; 153 vmsave 1 "Intercept VMSAVE instruction"; 154 stgi 1 "Intercept STGI instruction"; 155 clgi 1 "Intercept CLGI instruction"; 156 skinit 1 "Intercept SKINIT instruction"; 157 rdtscp 1 "Intercept RDTSCP instruction"; 158 icebp 1 "Intercept ICEBP instruction"; 159 wbinvd 1 "Intercept WBINVD instruction"; 160 monitor 1 "Intercept MONITOR instruction"; 161 mwait0 1 "Intercept MWAIT instruction unconditionally"; 162 mwait1 1 "Intercept MWAIT instruction if monitor hardware is armed"; 163 _ 19 rsvd; 164 }; 165 166 register iopm_base_pa addr(base, 0x040) "Physical base address of IOPM (bits 11:0 are ignored)" type(uint64); 167 168 register msrpm_base_pa addr(base, 0x048) "Physical base address of MSRPM (bits 11:0 are ignored)" type(uint64); 169 170 register tsc_offset addr(base, 0x050) "To be added in RDTSC and RDTSCP" type(uint64); 171 172 register tlb addr(base, 0x058) "Guest TLB settings" { 173 guest_asid 32 "Guest ASID"; 174 control 8 "TLB control values"; 175 _ 24 rsvd; 176 }; 177 178 register vintr addr(base, 0x060) "Virtual interrupt settings" { 179 vtpr 8 "Virtual TPR for the guest"; 180 virq 1 "Virtual interrupt pernding"; 181 _ 7 "Reserved, SBZ"; 182 vintr_prio 4 "Priority for virtual interrupt"; 183 v_ign_tpr 1 "Virtual interrupt ignores the virtual TPR"; 184 _ 3 "Reserved, SBZ"; 185 vintr_masking 1 "Virtualize masking of INTR interrupt"; 186 _ 7 "Reserved, SBZ"; 187 vintr_vector 8 "Vector to use for this interrupt"; 188 _ 24 rsvd; 189 }; 190 191 register intr addr(base, 0x068) "Guest interrupt settings" { 192 interrupt_shadow 1 "Guest is in an interrupt shadow"; 193 _ 63 rsvd; 194 }; 195 196 register exitcode addr(base, 0x070) "Guest EXITCODE" type(uint64); 197 198 register exitinfo1 addr(base, 0x078) "Guest EXITINFO1" type(uint64); 199 200 register exitinfo2 addr(base, 0x080) "Guest EXITINFO2" type(uint64); 201 202 register exitintinfo addr(base, 0x088) "Guest EXITINTINFO" type(uint64); 203 204 register np addr(base, 0x090) "Nested paging settings" { 205 enable 1 "Enable nested paging"; 206 _ 63 rsvd; 207 }; 208 209 register eventinj addr(base, 0x0a8) "Event injection" type(uint64); 210 211 register ncr3 addr(base, 0x0b0) "Nested page table CR3 to use for nested paging" type(uint64); 212 213 register lbr addr(base, 0x0b8) "Guest LBR settings" { 214 lbr_virtualization_enable 1 "Enable LBR virtualization"; 215 _ 63 rsvd; 216 }; 217 218 /* Guest State */ 219 220 regtype seg_attrib "Segment attributes" { 221 segtype 4 "Segment type"; 222 s 1 "Segment descriptor type"; 223 dpl 2 "Descriptor privilege level"; 224 p 1 "Segment present"; 225 avl 1 "Available for use by system software"; 226 l 1 "64-bit code segment"; 227 db 1 "Default operation size (0: 16-bit, 1: 32-bit segment)"; 228 g 1 "Granularity"; 229 _ 4 rsvd; 230 }; 231 232 register es_selector addr(base, 0x400) "Guest ES selector" type(uint16); 233 register es_attrib addr(base, 0x402) "Guest ES attrib" type(seg_attrib); 234 register es_limit addr(base, 0x404) "Guest ES limit" type(uint32); 235 register es_base addr(base, 0x408) "Guest ES base" type(uint64); 236 237 register cs_selector addr(base, 0x410) "Guest CS selector" type(uint16); 238 register cs_attrib addr(base, 0x412) "Guest CS attrib" type(seg_attrib); 239 register cs_limit addr(base, 0x414) "Guest CS limit" type(uint32); 240 register cs_base addr(base, 0x418) "Guest CS base" type(uint64); 241 242 register ss_selector addr(base, 0x420) "Guest SS selector" type(uint16); 243 register ss_attrib addr(base, 0x422) "Guest SS attrib" type(seg_attrib); 244 register ss_limit addr(base, 0x424) "Guest SS limit" type(uint32); 245 register ss_base addr(base, 0x428) "Guest SS base" type(uint64); 246 247 register ds_selector addr(base, 0x430) "Guest DS selector" type(uint16); 248 register ds_attrib addr(base, 0x432) "Guest DS attrib" type(seg_attrib); 249 register ds_limit addr(base, 0x434) "Guest DS limit" type(uint32); 250 register ds_base addr(base, 0x438) "Guest DS base" type(uint64); 251 252 register fs_selector addr(base, 0x440) "Guest FS selector" type(uint16); 253 register fs_attrib addr(base, 0x442) "Guest FS attrib" type(seg_attrib); 254 register fs_limit addr(base, 0x444) "Guest FS limit" type(uint32); 255 register fs_base addr(base, 0x448) "Guest FS base" type(uint64); 256 257 register gs_selector addr(base, 0x450) "Guest GS selector" type(uint16); 258 register gs_attrib addr(base, 0x452) "Guest GS attrib" type(seg_attrib); 259 register gs_limit addr(base, 0x454) "Guest GS limit" type(uint32); 260 register gs_base addr(base, 0x458) "Guest GS base" type(uint64); 261 262 register gdtr_selector addr(base, 0x460) "Guest GTDR selector" type(uint16); 263 register gdtr_attrib addr(base, 0x462) "Guest GTDR attrib" type(seg_attrib); 264 register gdtr_limit addr(base, 0x464) "Guest GTDR limit" type(uint32); 265 register gdtr_base addr(base, 0x468) "Guest GTDR base" type(uint64); 266 267 register ldtr_selector addr(base, 0x470) "Guest LTDR selector" type(uint16); 268 register ldtr_attrib addr(base, 0x472) "Guest LTDR attrib" type(seg_attrib); 269 register ldtr_limit addr(base, 0x474) "Guest LTDR limit" type(uint32); 270 register ldtr_base addr(base, 0x478) "Guest LTDR base" type(uint64); 271 272 register idtr_selector addr(base, 0x480) "Guest ITDR selector" type(uint16); 273 register idtr_attrib addr(base, 0x482) "Guest ITDR attrib" type(seg_attrib); 274 register idtr_limit addr(base, 0x484) "Guest ITDR limit" type(uint32); 275 register idtr_base addr(base, 0x488) "Guest ITDR base" type(uint64); 276 277 register tr_selector addr(base, 0x490) "Guest TR selector" type(uint16); 278 register tr_attrib addr(base, 0x492) "Guest TR attrib" type(seg_attrib); 279 register tr_limit addr(base, 0x494) "Guest TR limit" type(uint32); 280 register tr_base addr(base, 0x498) "Guest TR base" type(uint64); 281 282 register cpl addr(base, 0x4cb) "Guest current protection level" type(uint8); 283 284 register efer addr(base, 0x4d0) "Guest EFER" { 285 sce 1 "System Call Extensions"; 286 _ 7 mbz; 287 lme 1 "Long Mode Enable"; 288 _ 1 mbz; 289 lma 1 "Long Mode Active"; 290 nxe 1 "No-Execute Enable"; 291 svme 1 "Secure Virtual Machine Enable"; 292 _ 1 mbz; 293 ffxsr 1 "Fast FXSAVE/FXRSTOR"; 294 _ 49 mbz; 295 }; 296 297 register cr4 addr(base, 0x548) "Guest CR4" { 298 vme 1 "Virtual-8086 Mode Extensions"; 299 pvi 1 "Protected-Mode Virtual Interrupts"; 300 tsd 1 "Time Stamp Disable"; 301 de 1 "Debugging Extensions"; 302 pse 1 "Page Size Extensions"; 303 pae 1 "Physical-Address Extension"; 304 mce 1 "Machine Check Enable"; 305 pge 1 "Page-Global Enable"; 306 pce 1 "Performance-Monitoring Counter Enable"; 307 osfxsr 1 "Operating System FXSAVE/FXRSTOR Support"; 308 osxmmecept 1 "Operating System Unmasked Exception Support"; 309 _ 53 mbz; 310 }; 311 312 register cr3 addr(base, 0x550) "Guest CR3" type(uint64); 313 314 register cr0 addr(base, 0x558) "Guest CR0" { 315 pe 1 "Protection Enabled"; 316 mp 1 "Monitor Coprocessor"; 317 em 1 "Emulation"; 318 ts 1 "Task Switched"; 319 et 1 ro "Extension Type"; 320 ne 1 "Numeric Error"; 321 _ 10 rsvd; 322 wp 1 "Write Protect"; 323 _ 1 rsvd; 324 am 1 "Alignment Mask"; 325 _ 10 rsvd; 326 nw 1 "Not Writethrough"; 327 cd 1 "Cache Disable"; 328 pg 1 "Paging"; 329 _ 32 mbz; 330 }; 331 332 register dr7 addr(base, 0x560) "Guest DR7" type(uint64); 333 register dr6 addr(base, 0x568) "Guest DR6" type(uint64); 334 335 register rflags addr(base, 0x570) "Guest RFLAGS" { 336 cf 1 "Carry Flag"; 337 _ 1 rsvd; 338 pf 1 "Parity Flag"; 339 _ 1 rsvd; 340 af 1 "Auxiliary Flag"; 341 _ 1 rsvd; 342 zf 1 "Zero Flag"; 343 sf 1 "Sign Flag"; 344 tf 1 "Trap Flag"; 345 intrf 1 "Interrupt Flag"; 346 df 1 "Direction Flag"; 347 of 1 "Overflow Flag"; 348 iopl 2 "I/O Privilege Level"; 349 nt 1 "Nested Task"; 350 _ 1 rsvd; 351 rf 1 "Resume Flag"; 352 vm 1 "Virtual-8086 Mode"; 353 ac 1 "Alignment Check"; 354 vif 1 "Virtual Interrupt Flag"; 355 vip 1 "Virtual Interrupt Pending"; 356 id 1 "ID Flag"; 357 _ 42 rsvd; 358 }; 359 360 register rip addr(base, 0x578) "Guest RIP" type(uint64); 361 register rsp addr(base, 0x5d8) "Guest RSP" type(uint64); 362 register rax addr(base, 0x5F8) "Guest RAX" type(uint64); 363 register star addr(base, 0x600) "Guest STAR" type(uint64); 364 register lstar addr(base, 0x608) "Guest LSTAR" type(uint64); 365 register cstar addr(base, 0x610) "Guest CSTAR" type(uint64); 366 register sfmask addr(base, 0x618) "Guest SFMASK" type(uint64); 367 register kernel_gs_base addr(base, 0x620) "Guest KernelGsBase" type(uint64); 368 register sysenter_cs addr(base, 0x628) "Guest SYSENTER_CS" type(uint64); 369 register sysenter_esp addr(base, 0x630) "Guest SYSENTER_ESP" type(uint64); 370 register sysenter_eip addr(base, 0x638) "Guest SYSENTER_EIP" type(uint64); 371 register cr2 addr(base, 0x640) "Guest CR2" type(uint64); 372 register gpat addr(base, 0x668) "Guest PAT" type(uint64); 373 register dbgctl addr(base, 0x670) "Guest DBGCTL MSR" type(uint64); 374 register br_from addr(base, 0x678) "Guest LastBranchFromIP MSR" type(uint64); 375 register br_to addr(base, 0x680) "Guest LastBranchToIP MSR" type(uint64); 376 register lastexcpfrom addr(base, 0x688) "Guest LastExceptionFromIP MSR" type(uint64); 377 register lastexcpto addr(base, 0x690) "Guest LastExceptionToIP MSR" type(uint64); 378}; 379