1/*
2 * Copyright (c) 2007, 2008, 2011 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * amd64.dev
11 *
12 * DESCRIPTION: amd64 and Intel64 architecture definitions.
13 * 
14 * This is derived from the "Intel 64 and IA-32 Architectures Software
15 * Developer's Manual", volumes 3A and 3B, "System Programming Guide,
16 * Parts 1 and 2"
17 */
18
19device amd64 msbfirst ( ) "Intel64 and AMD 64-bit architecture definitions" {
20
21    //
22    // Section 2.5: Control registers
23    //
24    register cr0 noaddr "Control register 0" {
25	pg	1 "Paging";
26	cd	1 "Cache disable";
27	nw	1 "Not write-through";
28	_	10;
29	am	1 "Alignment mask";
30	_	1;
31	wp	1 "Write protect";
32	_	10;
33	ne	1 "Numeric error";
34	et	1 "Extension type";
35	ts	1 "Task switched";
36	em	1 "Emulation";
37	mp	1 "Monitor coprocessor";
38	pe	1 "Protection enable";
39    };
40
41    // Control register 1 is reserved.
42    
43    register cr2 noaddr "Page-fault linear address" type(uint64);
44	
45    register cr3 noaddr "Control register 3 (PDBR)" {
46	pdb	52 "Page-directory base";
47	_	7;
48	pcd	1 "Page-level cache disable";
49	pwt	1 "Page-level writes transparent";
50	_	3;
51    };
52
53    register cr4 noaddr "Control register 4" {
54	_		49 mbz;
55	smxe		1 "SMX enable";
56	vmxe		1 "VMX enable";
57	_		2 mbz;
58	osxmmexcpt	1 "OS support for unmasked SIMD FP exceptions";
59	osfxsr		1 "OS support for FXSAVE and FXRSTOR instructions";
60	pce		1 "Performance-monitoring counter enable";
61	pge		1 "Page global enable";
62	mce		1 "Machine-check enable";
63	pae		1 "Physical address extensions";
64	pse		1 "Page size extensions";
65	de		1 "Debugging extensions";
66	tsd		1 "Time stamp disable";
67	pvi		1 "Protected-mode virtual interrupts";
68	vme		1 "Virtual 8086 mode extensions";
69    };
70
71    regtype cr8 "Control register 8" {
72	_	60;
73	tpl	4 "Task priority level";
74    };
75
76    //
77    // Section 3.10: PAE-Enabled Paging in IA-32e Mode
78    //
79
80    regtype pdir_entry "Page-Directory Entry" {
81	exb	1  "Execute-Disable";
82	avail	11 "Available";
83	_	12 mbz;
84	base	28 "Base address";
85	avail2	3  "Available";
86	_	2  mbz;
87	avail3	1  "Available";
88	accessed 1  "Accessed";
89	pcd	1  "Cache disabled";
90	pwt	1  "Write-through";
91	us	1  "User/Supervisor";
92	rw	1  "Read/Write";
93	present	1  "Present";
94    };
95    
96    regtype ptable_entry "Page-Table Entry" {
97	exb	1  "Execute-Disable";
98	avail	11 "Available";
99	_	12 mbz;
100	base	28 "Base address";
101	avail2	3  "Available";
102	global	1  "Global";
103	pat	1  "Page-Attribute index";
104	dirty	1  "Dirty";
105	accessed 1  "Accessed";
106	pcd	1  "Cache disabled";
107	pwt	1  "Write-through";
108	us	1  "User/Supervisor";
109	rw	1  "Read/Write";
110	present	1  "Present";
111    };
112
113};
114