1/** 2 * \brief this file contains general, type and function definitions for the 3 * EHCI controller 4 */ 5 6/* 7 * Copyright (c) 2007-2013 ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef USB_EHCI_H_ 16#define USB_EHCI_H_ 17 18// general include for types 19#include <usb/usb.h> 20 21// include for the ehci_t mackerel type 22#include "ehci_device.h" 23 24// include for the root hub 25#include <usb_hub.h> 26 27/// maximum devices supported by the host controller 28#define USB_EHCI_MAX_DEVICES 128 29 30/// the special interrupt endpoint 31#define USB_EHCI_INTR_EP 1 32 33/// the alignment of a frame used in the frame list 34#define USB_EHCI_FRAMELIST_ALIGN 0x1000 35 36/// the number of USB frames 37#define USB_EHCI_FRAMELIST_COUNT 1024 38 39/// the number of virtual USB frames 40#define USB_EHCI_VFRAMELIST_COUNT 128 41 42/* 43 * Transfer Directions 44 */ 45 46/// Transfer direction is output 47#define USB_EHCI_DIRECTION_OUT 0 48 49/// Transfer direction is input 50#define USB_EHCI_DIRECTION_IN 1 51 52/* 53 * Structure Alignment Constraints for EHCI host controller, the EHCI specs 54 * define certain alignment constraints that the hardware accessible data 55 * structures must have 56 */ 57 58/// EHCI Isochronus HS Transfer Descriptor (iTD) alignment 59#define USB_EHCI_ITD_ALIGN 64 60 61/// EHCI Split Isochronus Transfer Descriptor (siTD) alignment 62#define USB_EHCI_SITD_ALIGN 64 63 64/// EHCI Queue Element Transfer Descriptor (qTD) alignemnt 65#define USB_EHCI_QTD_ALIGN 64 66 67/// EHCI Queue Head Descriptor (QH) alignment 68#define USB_EHCI_QH_ALIGN 128 69 70/// Periodic Frame Span Traversal Node (FSTN) alignment 71#define USB_EHCI_FSTN_ALIGN 32 72 73/// Alignment of a USB EHCI buffer page 74#define USB_EHCI_PAGE_ALIGN 4096 75 76/// Size of a EHCI buffer page (4kb) 77#define USB_EHCI_BUFFER_SIZE 0x1000 78 79/* 80 * -------------------------------------------------------------------------- 81 * Next Schedule Element Pointer Types 82 * EHCI Specification, Section 3.3.1, Table 3-2 83 * -------------------------------------------------------------------------- 84 * 85 * This values indicate the type of the element referenced by the next link 86 * pointer in the respective transfer chains. 87 */ 88 89/// the number of bits the link type value is shifted 90#define USB_EHCI_LINKTYPE_SHIFT 1 91 92/// Type Isochronus Transfer Descriptor (iTD) 93#define USB_EHCI_LINKTYPE_ITD (0 << USB_EHCI_LINKTYPE_SHIFT) 94 95/// Type Queue Head (QH) 96#define USB_EHCI_LINKTYPE_QH (1 << USB_EHCI_LINKTYPE_SHIFT) 97 98/// Type Split Transaction Isochronus Transfer Descriptor (siTD) 99#define USB_EHCI_LINKTYPE_SITD (2 << USB_EHCI_LINKTYPE_SHIFT) 100 101/// Frame Span Traversal Node 102#define USB_EHCI_LINKTYPE_FSTN (3 << USB_EHCI_LINKTYPE_SHIFT) 103 104/// The link pointer field is valid 105#define USB_EHCI_LINK_VALID 0 106 107/// the link pointer field is terminate 108#define USB_EHCI_LINK_TERMINATE 1 109 110/* 111 * ========================================================================== 112 * ISOCHRONUS TRANSFER DESCRIPTOR 113 * EHCI Specification, Section 3.3 114 * ========================================================================== 115 */ 116 117/* 118 * iTD Transaction Status and Control List 119 * EHCI Specification, Section 3.3.2, Table 3-3 120 * 121 * The host controller uses the information in each transaction description 122 * plus the endpoint information contained in the first three dwords of the 123 * Buffer Page Pointer list, to execute a transaction on the USB. 124 */ 125 126/* iTD status field values */ 127 128/// Set by software to enable the execution of the transaction 129#define USB_EHCI_ITD_STATUS_ACTIVE 0x8 130 131/// Set by HC. Indicates a buffer overrun or under run of this transaction 132#define USB_EHCI_ITD_STATUS_DATA_ERR 0x4 133 134/// Set by HC The transaction generated a babble 135#define USB_EHCI_ITD_STATUS_BABBLE 0x2 136 137/// Set by HC. Transaction Error occurred because of bad response 138#define USB_EHCI_ITD_STATUS_TRANS_ERR 0x1 139 140/** 141 * iTD status field bit representation. 142 */ 143struct usb_ehci_itd_status { 144 uint32_t offset :12; ///< offset in the buffer in bytes 145 uint32_t page_select :3; ///< page buffer to use (0..6) 146 uint32_t ioc :1; ///< issue an interrupt upon completion 147 uint32_t length :12; ///< length of the data in bytes 148 uint32_t status :4; ///< transaction status record 149}; 150 151/// iTD status field type 152typedef struct usb_ehci_itd_status usb_ehci_itd_status_t; 153 154/** 155 * Representation of the buffer pointer field for the isochronus transfer 156 * descriptor. The first 3 buffer points have a additional information stored 157 * in the unused bits for the address. 158 */ 159union usb_ehci_itd_bp { 160 struct bp_0 { 161 uint32_t device_addres :7; ///< the device of for this TD 162 uint32_t endpoint :4; ///< then endpoint number for this TD 163 uint32_t _reserved :1; ///< reserved, has to be zero 164 usb_paddr_t bp :20; ///< physaddr of the buffer (4k aligned) 165 } bp_0; ///< Representation for BP 0 166 struct bp_1 { 167 uint32_t max_packet_size :11; ///< maximum packet size for this EP 168 uint32_t direction :1; ///< Direction of the transfer (1=IN) 169 usb_paddr_t bp :20; ///< physaddr of the buffer (4k aligned) 170 } bp_1; ///< Representation for BP 1 171 struct bp_2 { 172 uint32_t multi :2; ///< num of transactions per uFrame 0..3 173 uint32_t _reserved :10; ///< reserved, has to be zero 174 usb_paddr_t bp :20; ///< physaddr of the buffer (4k aligned) 175 } bp_2; ///< Representation for BP 2 176 usb_paddr_t address; ///< Representation for BP 3..6 177}; 178 179/// iTD buffer pointer type 180typedef union usb_ehci_itd_bp usb_ehci_itd_bp_t; 181 182/** 183 * Isochronus (High-Speed) Transfer Descriptor (iTD) 184 * EHCI Specification Section 3.3 185 * 186 * This structure is used only for high-speed isochronous endpoints. All other 187 * transfer types should use queue structures. Isochronous TDs must be aligned 188 * on a 32-byte boundary. 189 */ 190struct usb_ehci_itd { 191 /* hardware required fields */ 192 usb_paddr_t itd_next; ///< next link pointer 193 usb_ehci_itd_status_t itd_status[8]; ///< status fields of the transfer 194 usb_ehci_itd_bp_t itd_bp[7]; ///< buffer pointer list 195 /* extra fields for sofware management */ 196 usb_paddr_t itd_self; ///< physical address of this iTD 197 struct usb_ehci_itd *next; ///< virtual pointer of iTDs 198 struct usb_ehci_itd *prev; ///< virtual pointer of iTDs 199 struct usb_ehci_itd *obj_next; ///< virtual pointer to the next object 200}__aligned(USB_EHCI_ITD_ALIGN); 201 202/// EHCI Isochronus Transfer Descriptor Type 203typedef struct usb_ehci_itd usb_ehci_itd_t; 204 205/* 206 * ========================================================================== 207 * SPLIT ISOCHRONUS TRANSFER DESCRIPTOR 208 * EHCI Specification, Section 3.4 209 * ========================================================================== 210 */ 211 212/** 213 * siTD Endpoint Capabilities/Characteristics 214 * EHCI Specification Section 3.4.2 215 * 216 * Dwords 1 and 2 specify static information about the full-speed endpoint, 217 * the addressing of the parent transaction translator and micro-frame 218 * scheduling control. 219 */ 220struct usb_ehci_sitd_ep { 221 uint32_t device_address :7; ///< the device address of this transfer 222 uint32_t _reserved_3 :1; ///< reserved, should be zero 223 uint32_t endpoint :4; ///< endpoint number of this transfer 224 uint32_t _reserved_2 :4; ///< reserved, should be zero 225 uint32_t hub_address :7; ///< device address of the high speed hub 226 uint32_t _reserved_1 :1; ///< reserved, should be zero 227 uint32_t port_number :7; ///< port number at the high speed hub 228 uint32_t direction :1; ///< direction of the transfer 229 uint32_t s_mask :8; ///< split start mask 230 uint32_t c_mask :8; ///< split competition mask 231 uint32_t _reserved_4 :16; ///< reserved, should be zero 232}; 233 234/// siTD Endoint Capabilities/Characteristics state 235typedef struct usb_ehci_sitd_ep usb_ehci_sitd_ep_t; 236 237/** 238 * siTD Transfer State 239 * EHCI Specification Section 3.4.3 240 * 241 * Dwords 3-6 are used to manage the state of the transfer. 242 */ 243struct usb_ehci_sitd_state { 244 uint32_t status :8; ///< status of the transaction executed 245 uint32_t c_mask :8; ///< frame complete-split progress mask 246 uint32_t length :10; ///< total bytes to transfer 247 uint32_t _reserved :4; ///< reserved, should be zero 248 uint32_t page_select :1; ///< which data page pointer to use 249 uint32_t ioc :1; ///< interrupt on complete 250}; 251 252/// siTD transaction state type 253typedef struct usb_ehci_sitd_state usb_ehci_sitd_state_t; 254 255/* siTD status field values */ 256 257/// siTD status active, set by software to start the transaction 258#define USB_EHCI_SITD_STATUS_ACTIVE 0x80 259 260/// siTD status error, set by HC if there was an error 261#define USB_EHCI_SITD_STATUS_ERROR 0x40 262 263/// siTD status data buffer error upon buffer overrun or underrun 264#define USB_EHCI_SITD_STATUS_DATA_ERR 0x20 265 266/// siTD status babble detected 267#define USB_EHCI_SITD_STATUS_BABBLE 0x10 268 269/// siTD status transaction error (e.g. timeout, crc, ..) 270#define USB_EHCI_SITD_STATUS_TRANS_ERR 0x08 271 272/// siTD status missed micro frame, HC missed a requered complete-split 273#define USB_EHCI_SITD_STATUS_MISSED_FRAME 0x04 274 275/// siTD status split transaction state 0=start splitt, 1=compelte split 276#define USB_EHCI_SITD_STATUS_SPLIT 0x02 277 278/// siTD status reserved bit 0 279#define USB_EHCI_SITD_STATUS_RESERVED 0x01 280 281/* Transaction position (TP) values */ 282 283/// Transaction Position: ALL, the entire FS payload is in this transaction 284#define USB_EHCI_SITD_TP_ALL 0x0 285 286/// Transaction Position BEGIN, first data payload of a FS transaction 287#define USB_EHCI_SITD_TP_BEGIN 0x1 288 289/// Transaction Position MID, the middle payload for a FS OUT transaction 290#define USB_EHCI_SITD_TP_MID 0x2 291 292/// Transaction Position END, the last payload for a FS OUT transaction 293#define USB_EHCI_SITD_TP_END 0x3 294 295/** 296 * siTD Buffer Pointer List 297 * EHCI Specification, Section 3.4.4 298 * Dwords 4 and 5 are the data buffer page pointers for the transfer. This 299 * structure supports one physical page cross. The most significant 20 bits 300 * of each Dword in this section are the 4K (page) aligned buffer pointers. 301 * The least significant 12 bits of each Dword are used as additional 302 * transfer state. 303 */ 304union usb_ehci_sitd_bp { 305 struct usb_ehci_sitd_bp_0 { 306 usb_paddr_t offset :12; ///< offset into the page buffer 307 usb_paddr_t bp :20; ///< physical address of the buffer 308 } bp_0; ///< representation for BP 0 309 struct usb_ehci_sitd_bp_1 { 310 uint32_t count :3; ///< number of OUT start-split requests 311 uint32_t tp :2; ///< transaction position 312 uint32_t _reserved :7; ///< reserved, should be zero 313 usb_paddr_t bp :20; ///< physical address of the buffer 314 } bp_1; ///< representation for BP 1 315 usb_paddr_t address; 316}; 317 318/// siTD buffer pointer list type 319typedef union usb_ehci_sitd_bp usb_ehci_sitd_bp_t; 320 321/// siTD back link validity check 322#define USB_EHCI_SITD_BACK_LINK_VALID(sitd) \ 323 (!((sitd)->sitd_back_link) & 0x1)) 324 325/** 326 * Split Transaction Isochronous Transfer Descriptor (siTD) 327 * EHCI Specifiction Section 3.4 328 * 329 * All Full-speed isochronous transfers through Transaction Translators are 330 * managed using the siTD data structure. This data structure satisfies the 331 * operational requirements for managing the split transaction protocol. 332 */ 333struct usb_ehci_sitd { 334 /* hardware required fields */ 335 usb_paddr_t sitd_next; ///< next link pointer 336 usb_ehci_sitd_ep_t sitd_ep_char; ///< endpoint characteristics 337 usb_ehci_sitd_state_t sitd_state; ///< transaction state 338 usb_ehci_sitd_bp_t sitd_bp[2]; ///< buffer pointer list 339 usb_paddr_t sitd_back_link; ///< back link 340 /* extra fields for software managment */ 341 usb_paddr_t sitd_self; ///< the physical address of this siTD 342 struct usb_ehci_sitd *next; ///< virtual pointer to next sitD 343 struct usb_ehci_sitd *prev; ///< virtual pointer to previous siTD 344 struct usb_ehci_sitd *obj_next; ///< virtual pointer to next obj 345}__aligned(USB_EHCI_SITD_ALIGN); 346 347/// EHCI siTD type 348typedef struct usb_ehci_sitd usb_ehci_sitd_t; 349 350/* 351 * ========================================================================== 352 * QUEUE ELEMENT TRANSFER DESCRIPTOR 353 * EHCI Specification, Section 3.5 354 * ========================================================================== 355 */ 356 357/** 358 * Queue Element Transfer Descriptor Token 359 * EHCI Specification, Section 3.5.3 360 * 361 * The third DWORD of a queue element transfer descriptor contains most of the 362 * information the host controller requires to execute a USB transaction (the 363 * remaining endpoint-addressing information is specified in the queue head). 364 */ 365struct usb_ehci_qtd_token { 366 uint32_t status :8; ///< the status of this qTD element 367 uint32_t pid :2; ///< pid code [OUT|IN|SETUP] 368 uint32_t err_count :2; ///< number of consecutive errors 369 uint32_t current_page :3; ///< index into the buffer pointer list 370 uint32_t ioc :1; ///< interrupt on complete 371 uint32_t bytes :15; ///< total bytes to transfer, 372 uint32_t data_toggle :1; ///< data toggle bit 373}; 374 375typedef struct usb_ehci_qtd_token usb_ehci_qtd_token_t; 376 377/// the maximum number of bytes to transfer with one qtd (16k) 378#define USB_EHCI_QTD_MAX_BYTES 0x4000; 379 380/* qTD PID Codes */ 381 382/// qTD PID for OUT token 383#define USB_EHCI_QTD_PID_OUT 0x0 384 385/// qTD PID for IN token 386#define USB_EHCI_QTD_PID_IN 0x1 387 388/// qTD PID for SETUP token 389#define USB_EHCI_QTD_PID_SETUP 0x2 390 391/* qTD Status Codes */ 392 393/// qTD Status active, set to one to start the transaction 394#define USB_EHCI_QTD_STATUS_ACTIVE 0x80 395 396/// qTD status halted, indicates a serious error 397#define USB_EHCI_QTD_STATUS_HALTED 0x40 398 399/// qTD status data buffer error, data over/under run 400#define USB_EHCI_QTD_STATUS_DATA_ERR 0x20 401 402/// qTD status babble, a babble was detected 403#define USB_EHCI_QTD_STATUS_BABBLE 0x10 404 405/// qTD status transaction error 406#define USB_EHCI_QTD_STATUS_TRANS_ERR 0x08 407 408/// qTD status missed micro frame 409#define USB_EHCI_QTD_STATUS_MISS 0x04 410 411/// qTD status split transaction state, 0=do start split, 1=do complete split 412#define USB_EHCI_QTD_STATUS_SPLIT_STATE 0x02 413 414/// qTD status ping, 1=do ping, 0=do OUT 415#define USB_EHCI_QTD_STATUS_PING 0x01 416 417/// checks the next field for validity of a qTD 418#define USB_EHCI_QTD_VALID_NEXT(qtd) \ 419 (!(((next)->qtd_next) & 0x1)) 420 421/// checks the alternative next field of a qTD for validity 422#define USB_EHCI_QTD_VALID_ALT(qtd) \ 423 (!(((next)->qtd_alt_next) & 0x1)) 424 425/** 426 * defines the structure of the elements in the buffer pointer list inside 427 * a qTD 428 */ 429union usb_ehci_qtd_bp { 430 struct usb_ehci_qtd_bp0 { 431 uint16_t offset :12; ///< offset into the memory region 432 usb_paddr_t bp_list :20; ///< physaddr of a 4k aligned memory region 433 } bp_0; ///< representation for the first buffer page 434 usb_paddr_t address; ///< physaddr of a 5k aligned memory region 435}; 436 437/// qTD buffer page type 438typedef union usb_ehci_qtd_bp usb_ehci_qtd_bp_t; 439 440/// the number of buffers in a qtd 441#define USB_EHCI_QTD_NUM_BUFFERS 5 442 443/** 444 * Queue Element Transfer Descriptor (qTD) 445 * EHCI Specification, Section 3.5 446 * 447 * This data structure is only used with a queue head (see Section 3.6). This 448 * data structure is used for one or more USB transactions and can transfer up 449 * to 20480 (5*4096) bytes. 450 * 451 * The buffer associated with this transfer must be virtually contiguous. The 452 * buffer may start on any byte boundary. A separate buffer pointer list element 453 * must be used for each physical page in the buffer, regardless of whether the 454 * buffer is physically contiguous. 455 */ 456struct usb_ehci_qtd { 457 /* hardware required fields */ 458 usb_paddr_t qtd_next; ///< phyaddr of the next qTD to process 459 usb_paddr_t qtd_alt_next; ///< phyaddr to the next data stream 460 usb_ehci_qtd_token_t qtd_token; ///< various status fiels 461 usb_ehci_qtd_bp_t qtd_bp[5]; ///< buffer pointer lists 462 /* extra fields for software management */ 463 struct usb_ehci_qtd *alt_next; ///< virtual pointer to the alt_next 464 struct usb_ehci_qtd *obj_next; ///< virtual pointer to the next object 465 uint32_t qtd_self; ///< physical address of this qTD 466 uint32_t len; ///< length of data processed 467}__aligned(USB_EHCI_QTD_ALIGN); 468 469/// ehci queue element descriptor type 470typedef struct usb_ehci_qtd usb_ehci_qtd_t; 471 472/* 473 * ========================================================================== 474 * QUEUE HEAD TRANSFER DESCRIPTOR 475 * EHCI Specification, Section 3.6 476 * ========================================================================== 477 */ 478 479/** 480 * Queue Head Endpoint Characteristics / Capabilities 481 * EHCI Specification, Section 3.6.2 482 * 483 * The second and third Dwords of a Queue Head specifies static information 484 * about the endpoint. This information does not change over the lifetime of 485 * the endpoint. There are three types of information in this region: 486 * - Endpoint Characteristics 487 * - Endpoint Capabilities 488 * - Split Transaction Characteristics 489 */ 490struct usb_ehci_qh_ep { 491 /* endpoint characteristics */ 492 uint32_t device_address :7; ///< the device for this request 493 uint32_t inactive :1; ///< request active bit set to zero 494 uint32_t ep_number :4; ///< endpoint number for this request 495 uint32_t ep_speed :2; ///< endpoint speed 496 uint32_t data_toggle_ctrl :1; ///< initial data toggle from qTD 497 uint32_t head_reclamation :1; ///< this QH is the head of the reclamation 498 uint32_t max_packet_size :11; ///< the maximum packet size (max 1024) 499 uint32_t is_control_ep :1; ///< EP is control (for non HS EPs only) 500 uint32_t nak_count_reload :4; ///< value to re load the NAK fields 501 /* endpoint capabilities */ 502 uint32_t irq_mask :8; ///< interrupt schedule mask 503 uint32_t complete_mask :8; ///< split completition mask 504 uint32_t hub_addr :7; ///< address of the hub doint FS/LS trans 505 uint32_t port_number :7; ///< port number identifier of USB2.0 hub 506 uint32_t mult :2; ///< number of transactions issued 507}; 508 509/// queue head endpoint characteristics type 510typedef struct usb_ehci_qh_ep usb_ehci_qh_ep_t; 511 512/* endpoint field speed values */ 513 514/// QH endpoint is full speed 515#define USB_EHCI_QH_SPEED_FULL 0 516 517/// QH endpoint is low speed 518#define USB_EHCI_QH_SPEED_LOW 1 519 520/// QH endpoint is high speed 521#define USB_EHCI_QH_SPEED_HIGH 2 522 523/// QH endpoint speed reserved value 524#define USB_EHCI_QH_SPEED_RES 3 525 526/// Extract the type information of the QHLP fields 527#define USB_EHCI_QH_LINK_TYPE(qh) \ 528 ((((qh)->qh_link) >> 1) & 0x3) 529 530/// Extract the NAK count of a queue head 531#define USB_EHCI_QH_NAK_COUNT(qh) \ 532 ((((qh)->qh_alt_next_qtd) >> 1) & 0xF) 533 534/** 535 * Queue head status fields 536 */ 537struct usb_ehci_qh_status { 538 uint32_t status :8; ///< status of the transfer 539 uint32_t pid :2; ///< PID of the transfer 540 uint32_t err_count :2; ///< error counter 541 uint32_t current_page :3; ///< current buffer page 542 uint32_t ioc :1; ///< interrupt on competition flag 543 uint32_t bytes :15; ///< length of the transfer in bytes 544 uint32_t data_togglet :1; ///< data toggle control 545}; 546 547/// usb_ehci_qh_status_t type definition 548typedef struct usb_ehci_qh_status usb_ehci_qh_status_t; 549 550/** 551 * EHCI Queue Head Buffer Page bit representations 552 */ 553union usb_ehci_qh_bp { 554 struct usb_ehci_qh_bp_0 { 555 uint32_t offset :12; ///< offset into the buffer 556 usb_paddr_t address :20; ///< address of the buffer page 557 } bp_0; ///< format of buffer page 0 558 struct usb_ehci_qh_bp_1 { 559 uint32_t c_prog_mask :8; ///< split transaction progress 560 uint32_t _reserved :4; ///< reserved, should be zero 561 usb_paddr_t address :20; ///< address of the buffer page 562 } bp_1; ///< format of buffer page 1 563 struct usb_ehci_qh_bp_2 { 564 uint32_t tag :5; ///< frame tag 565 uint32_t bytes :7; ///< keeps track of bytes sent / received 566 usb_paddr_t address :20; ///< address of the buffer page 567 } bp_2; ///< format of buffer page 2 568 usb_paddr_t bp; ///< address of the buffer page (4k align) 569}; 570 571/// EHCI QH buffer pointer page type 572typedef union usb_ehci_qh_bp usb_ehci_qh_bp_t; 573 574/** 575 * Queue Head Descriptor 576 * EHCI Specification, Section 3.6 577 * 578 * Each transfer contains one queue head that has a list of qTDs linked to 579 */ 580struct usb_ehci_qh { 581 /* hardware required fields */ 582 usb_paddr_t qh_link; ///< physaddr to the next data object (QHLP) 583 usb_ehci_qh_ep_t qh_ep; ///< EP characteristics for this transfer 584 usb_paddr_t qh_curr_qtd; ///< current queue element processed 585 usb_paddr_t qh_next_qtd; ///< the next queue element 586 usb_paddr_t qh_alt_next_qtd; ///< the next alternative queue element 587 usb_ehci_qh_status_t qh_status; ///< status of the queue transfer 588 usb_ehci_qh_bp_t bp_list[5]; ///< buffer pointer list 589 /* extra fields for software management */ 590 struct usb_ehci_qh *next; ///< virtual pointer to next element 591 struct usb_ehci_qh *prev; ///< virtual pointer to previous element 592 struct usb_ehci_qh *obj_next; ///< virtual pointer to next object 593 usb_paddr_t qh_self; ///< physical address of this QH 594}__aligned(USB_EHCI_QH_ALIGN); 595 596/// USB EHCI queue head type 597typedef struct usb_ehci_qh usb_ehci_qh_t; 598 599/* 600 * ========================================================================== 601 * PERIODIC FRAME SPAN TRAVERSAL NODE 602 * EHCI Specification, Section 3.7 603 * ========================================================================== 604 */ 605 606/** 607 * Periodic Frame Span Traversal Node (FSTN) 608 * EHCI Specification, Section 3.7 609 * 610 * This data structure is to be used only for managing Full- and Low-speed 611 * transactions that span a Host-frame boundary. Software must not use an FSTN 612 * in the Asynchronous Schedule 613 */ 614struct usb_ehci_fstn { 615 usb_paddr_t fstn_link; ///< physaddr of the next data object 616 usb_paddr_t fstn_back; ///< linkpointer to a queue head 617}__aligned(USB_EHCI_FSTN_ALIGN); 618 619/// EHCI Periodic Frame Span Traversal Node type 620typedef struct usb_ehci_fstn usb_ehci_fstn_t; 621 622/// extract the type of the normal path pointer field 623#define USB_EHCI_FSTN_LINK_TYPE(fstn) \ 624 ((((fstn)->fstn_link) >> 1) & 0x3) 625/// extract the type of back path pointer field 626#define USB_EHCI_FSTN_BACK_TYPE(fstn) \ 627 ((((fstn)->fstn_back) >> 1) & 0x3) 628 629/// validity check for the normal path pointer 630#define USB_EHCI_FSTN_LINK_VALID(fstn) \ 631 (!(((fstn)->fstn_back) & 0x1)) 632 633/// validity check for the back path pointer 634#define USB_EHCI_FSTN_BACK_VALID(fstn) \ 635 (!(((fstn)->fstn_back) & 0x1)) 636 637/* 638 * ========================================================================== 639 * USB EHCI HOST CONTROLLER SOFTWARE CONTROL 640 * ========================================================================== 641 */ 642 643/** 644 * this data structure defines the structure of the EHCI root hub scratch buffer 645 * used for serving root hub requests 646 */ 647union usb_ehci_hub_descriptor { 648 struct usb_status status; 649 struct usb_hub_port_status port_status; 650 struct usb_hub_descriptor hub_desc; 651 uint8_t temp[128]; 652}; 653 654/** 655 * EHCI Controller Software Control 656 * 657 * This data structure contains data for management of the EHCI controller 658 */ 659struct usb_ehci_hc { 660 struct ehci_t ehci_base; ///< the mackerel device base 661 usb_host_controller_t *controller; ///< pointer to the generic HC 662 uint32_t enabled_interrupts; ///< the currently enabled interrupts 663 uint16_t ehci_revision; ///< host controller revision 664 665 /* root hub */ 666 union usb_ehci_hub_descriptor rh_desc; ///< root hub descriptor scratch buf 667 uint8_t rh_num_ports; ///< the number of root hub ports 668 uint8_t rh_device_address; ///< the root hub device address 669 uint8_t rh_device_config; ///< current root hub configuration 670 char rh_vendor[16]; ///< root hub vendor string 671 uint8_t rh_reset; ///< root hub reset flag 672 struct usb_device *rh_device; ///< pointer to the root hub device 673 674 /* devices */ 675 struct usb_device *devices[USB_EHCI_MAX_DEVICES]; ///< connected devices 676 677 /* free lists of allocated structures */ 678 struct usb_ehci_qh *qh_free; ///< pointer to free queue heads 679 struct usb_ehci_sitd *sidt_free; ///< pointer to free siTD 680 struct usb_ehci_itd *itd_free; ///< pointer to free iTD 681 682 /* transfers */ 683 struct usb_ehci_qh *qh_async_last; ///< pointer to the last async qh 684 struct usb_ehci_qh *qh_async_first; ///< pointer to the first async qh 685 struct usb_ehci_qh *qh_terminate; ///< pointer to terminator qh 686 687 /* interrupt transfers */ 688 struct usb_ehci_qh *qh_intr_last[USB_EHCI_VFRAMELIST_COUNT]; ///< intr qh 689 uint16_t qh_intr_stat[USB_EHCI_VFRAMELIST_COUNT]; ///< interrupt statistics 690 691 /* isochronus transfer lists */ 692 struct usb_ehci_sitd *qh_sitd_fs_last[USB_EHCI_VFRAMELIST_COUNT]; 693 struct usb_ehci_itd *qh_itd_hs_last[USB_EHCI_VFRAMELIST_COUNT]; 694 usb_paddr_t pframes_phys; ///< physical frames 695 usb_paddr_t *pframes; ///< physical frames 696}; 697 698/// USB EHCI host controller type 699typedef struct usb_ehci_hc usb_ehci_hc_t; 700 701/* Function Prototypes */ 702 703void usb_ehci_interrupt(usb_host_controller_t *host); 704usb_error_t usb_ehci_init(usb_ehci_hc_t *hc, uintptr_t controller_base); 705usb_error_t usb_ehci_hc_reset(usb_ehci_hc_t *hc); 706usb_error_t usb_ehci_initialize_controller(usb_ehci_hc_t *hc); 707 708#endif /* USB_EHCI_H_ */ 709