1#ifndef MEGARAID_H 2#define MEGARAID_H 3 4#define MEGARAID_DEBUG 5 6#include <dev/megaraid_dev.h> 7#include "queue.h" 8 9/* 10 * Device IDs and PCI 11 */ 12#define MRSAS_TBOLT 0x005b 13#define MRSAS_INVADER 0x005d 14#define MRSAS_FURY 0x005f 15#define MRSAS_PCI_BAR0 0x10 16#define MRSAS_PCI_BAR1 0x14 17#define MRSAS_PCI_BAR2 0x1C 18 19/* 20 * Firmware State Defines 21 */ 22#define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 23#define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 24#define MRSAS_FW_STATE_CHNG_INTERRUPT 1 25 26/* 27 * Message Frame Defines 28 */ 29#define MRSAS_SENSE_LEN 96 30#define MRSAS_FUSION_MAX_RESET_TRIES 3 31 32/* 33 * Miscellaneous Defines 34 */ 35#define BYTE_ALIGNMENT 1 36#define MRSAS_MAX_NAME_LENGTH 32 37#define MRSAS_VERSION "6.602.01.00" 38#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 39#define MRSAS_DEFAULT_TIMEOUT 0x14 //temp 40#define DONE 0 41#define MRSAS_PAGE_SIZE 4096 42#define MRSAS_RESET_NOTICE_INTERVAL 5 43#define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 44#define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 45#define THRESHOLD_REPLY_COUNT 50 46 47enum err { SUCCESS, FAIL }; 48 49#define MRSAS_INFO (1 << 0) 50#define MRSAS_TRACE (1 << 1) 51#define MRSAS_FAULT (1 << 2) 52#define MRSAS_OCR (1 << 3) 53#define MRSAS_TOUT MRSAS_OCR 54#define MRSAS_AEN (1 << 4) 55#define MRSAS_PRL11 (1 << 5) 56 57/**************************************************************************** 58 * Raid Context structure which describes MegaRAID specific IO Paramenters 59 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 60 ****************************************************************************/ 61 62typedef struct _RAID_CONTEXT { 63 u_int8_t Type:4; // 0x00 64 u_int8_t nseg:4; // 0x00 65 u_int8_t resvd0; // 0x01 66 u_int16_t timeoutValue; // 0x02 -0x03 67 u_int8_t regLockFlags; // 0x04 68 u_int8_t resvd1; // 0x05 69 u_int16_t VirtualDiskTgtId; // 0x06 -0x07 70 u_int64_t regLockRowLBA; // 0x08 - 0x0F 71 u_int32_t regLockLength; // 0x10 - 0x13 72 u_int16_t nextLMId; // 0x14 - 0x15 73 u_int8_t exStatus; // 0x16 74 u_int8_t status; // 0x17 status 75 u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0] 76 u_int8_t numSGE; // 0x19 numSge; not including chain entries 77 u_int16_t configSeqNum; // 0x1A -0x1B 78 u_int8_t spanArm; // 0x1C span[7:5], arm[4:0] 79 u_int8_t resvd2[3]; // 0x1D-0x1f 80} RAID_CONTEXT; 81 82 83/************************************************************************* 84 * MPI2 Defines 85 ************************************************************************/ 86 87#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 88#define MPI2_WHOINIT_HOST_DRIVER (0x04) 89#define MPI2_VERSION_MAJOR (0x02) 90#define MPI2_VERSION_MINOR (0x00) 91#define MPI2_VERSION_MAJOR_MASK (0xFF00) 92#define MPI2_VERSION_MAJOR_SHIFT (8) 93#define MPI2_VERSION_MINOR_MASK (0x00FF) 94#define MPI2_VERSION_MINOR_SHIFT (0) 95#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 96 MPI2_VERSION_MINOR) 97#define MPI2_HEADER_VERSION_UNIT (0x10) 98#define MPI2_HEADER_VERSION_DEV (0x00) 99#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 100#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 101#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 102#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 103#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 104#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 105#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 106#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 107#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 108#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 109#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 110#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 111#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 112#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 113#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 114#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 115#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 116#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 117#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 118#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 119#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 120#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 121#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 122#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 123#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 124#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 125#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 126#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 127#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 128#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 129 130#ifndef MPI2_POINTER 131#define MPI2_POINTER * 132#endif 133 134 135/*************************************** 136 * MPI2 Structures 137 ***************************************/ 138 139typedef struct _MPI25_IEEE_SGE_CHAIN64 140{ 141 u_int64_t Address; 142 u_int32_t Length; 143 u_int16_t Reserved1; 144 u_int8_t NextChainOffset; 145 u_int8_t Flags; 146} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 147 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 148 149typedef struct _MPI2_SGE_SIMPLE_UNION 150{ 151 u_int32_t FlagsLength; 152 union 153 { 154 u_int32_t Address32; 155 u_int64_t Address64; 156 } u; 157} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 158 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 159 160typedef struct 161{ 162 u_int8_t CDB[20]; /* 0x00 */ 163 u_int32_t PrimaryReferenceTag; /* 0x14 */ 164 u_int16_t PrimaryApplicationTag; /* 0x18 */ 165 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 166 u_int32_t TransferLength; /* 0x1C */ 167} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 168 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 169 170typedef struct _MPI2_SGE_CHAIN_UNION 171{ 172 u_int16_t Length; 173 u_int8_t NextChainOffset; 174 u_int8_t Flags; 175 union 176 { 177 u_int32_t Address32; 178 u_int64_t Address64; 179 } u; 180} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 181 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 182 183typedef struct _MPI2_IEEE_SGE_SIMPLE32 184{ 185 u_int32_t Address; 186 u_int32_t FlagsLength; 187} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 188 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 189typedef struct _MPI2_IEEE_SGE_SIMPLE64 190{ 191 u_int64_t Address; 192 u_int32_t Length; 193 u_int16_t Reserved1; 194 u_int8_t Reserved2; 195 u_int8_t Flags; 196} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 197 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 198 199typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 200{ 201 MPI2_IEEE_SGE_SIMPLE32 Simple32; 202 MPI2_IEEE_SGE_SIMPLE64 Simple64; 203} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 204 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 205 206typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 207typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 208 209typedef union _MPI2_IEEE_SGE_CHAIN_UNION 210{ 211 MPI2_IEEE_SGE_CHAIN32 Chain32; 212 MPI2_IEEE_SGE_CHAIN64 Chain64; 213} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 214 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 215 216typedef union _MPI2_SGE_IO_UNION 217{ 218 MPI2_SGE_SIMPLE_UNION MpiSimple; 219 MPI2_SGE_CHAIN_UNION MpiChain; 220 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 221 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 222} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 223 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 224 225typedef union 226{ 227 u_int8_t CDB32[32]; 228 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 229 MPI2_SGE_SIMPLE_UNION SGE; 230} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 231 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 232 233/* 234 * RAID SCSI IO Request Message 235 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 236 */ 237typedef struct _MPI2_RAID_SCSI_IO_REQUEST 238{ 239 u_int16_t DevHandle; /* 0x00 */ 240 u_int8_t ChainOffset; /* 0x02 */ 241 u_int8_t Function; /* 0x03 */ 242 u_int16_t Reserved1; /* 0x04 */ 243 u_int8_t Reserved2; /* 0x06 */ 244 u_int8_t MsgFlags; /* 0x07 */ 245 u_int8_t VP_ID; /* 0x08 */ 246 u_int8_t VF_ID; /* 0x09 */ 247 u_int16_t Reserved3; /* 0x0A */ 248 u_int32_t SenseBufferLowAddress; /* 0x0C */ 249 u_int16_t SGLFlags; /* 0x10 */ 250 u_int8_t SenseBufferLength; /* 0x12 */ 251 u_int8_t Reserved4; /* 0x13 */ 252 u_int8_t SGLOffset0; /* 0x14 */ 253 u_int8_t SGLOffset1; /* 0x15 */ 254 u_int8_t SGLOffset2; /* 0x16 */ 255 u_int8_t SGLOffset3; /* 0x17 */ 256 u_int32_t SkipCount; /* 0x18 */ 257 u_int32_t DataLength; /* 0x1C */ 258 u_int32_t BidirectionalDataLength; /* 0x20 */ 259 u_int16_t IoFlags; /* 0x24 */ 260 u_int16_t EEDPFlags; /* 0x26 */ 261 u_int32_t EEDPBlockSize; /* 0x28 */ 262 u_int32_t SecondaryReferenceTag; /* 0x2C */ 263 u_int16_t SecondaryApplicationTag; /* 0x30 */ 264 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 265 u_int8_t LUN[8]; /* 0x34 */ 266 u_int32_t Control; /* 0x3C */ 267 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 268 RAID_CONTEXT RaidContext; /* 0x60 */ 269 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 270} MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 271 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 272 273/* 274 * MPT RAID MFA IO Descriptor. 275 */ 276typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 277 u_int32_t RequestFlags : 8; 278 u_int32_t MessageAddress1 : 24; /* bits 31:8*/ 279 u_int32_t MessageAddress2; /* bits 61:32 */ 280} MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 281 282/* Default Request Descriptor */ 283typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 284{ 285 u_int8_t RequestFlags; /* 0x00 */ 286 u_int8_t MSIxIndex; /* 0x01 */ 287 u_int16_t SMID; /* 0x02 */ 288 u_int16_t LMID; /* 0x04 */ 289 u_int16_t DescriptorTypeDependent; /* 0x06 */ 290} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 291 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 292 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 293 294/* High Priority Request Descriptor */ 295typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 296{ 297 u_int8_t RequestFlags; /* 0x00 */ 298 u_int8_t MSIxIndex; /* 0x01 */ 299 u_int16_t SMID; /* 0x02 */ 300 u_int16_t LMID; /* 0x04 */ 301 u_int16_t Reserved1; /* 0x06 */ 302} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 303 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 304 Mpi2HighPriorityRequestDescriptor_t, 305 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 306 307/* SCSI IO Request Descriptor */ 308typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 309{ 310 u_int8_t RequestFlags; /* 0x00 */ 311 u_int8_t MSIxIndex; /* 0x01 */ 312 u_int16_t SMID; /* 0x02 */ 313 u_int16_t LMID; /* 0x04 */ 314 u_int16_t DevHandle; /* 0x06 */ 315} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 316 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 317 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 318 319/* SCSI Target Request Descriptor */ 320typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 321{ 322 u_int8_t RequestFlags; /* 0x00 */ 323 u_int8_t MSIxIndex; /* 0x01 */ 324 u_int16_t SMID; /* 0x02 */ 325 u_int16_t LMID; /* 0x04 */ 326 u_int16_t IoIndex; /* 0x06 */ 327} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 328 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 329 Mpi2SCSITargetRequestDescriptor_t, 330 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 331 332/* RAID Accelerator Request Descriptor */ 333typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 334{ 335 u_int8_t RequestFlags; /* 0x00 */ 336 u_int8_t MSIxIndex; /* 0x01 */ 337 u_int16_t SMID; /* 0x02 */ 338 u_int16_t LMID; /* 0x04 */ 339 u_int16_t Reserved; /* 0x06 */ 340} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 341 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 342 Mpi2RAIDAcceleratorRequestDescriptor_t, 343 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 344 345/* union of Request Descriptors */ 346typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION 347{ 348 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 349 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 350 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 351 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 352 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 353 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 354 union { 355 struct { 356 u_int32_t low; 357 u_int32_t high; 358 } u; 359 u_int64_t Words; 360 } addr; 361} MRSAS_REQUEST_DESCRIPTOR_UNION; 362 363/* Default Reply Descriptor */ 364typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 365{ 366 u_int8_t ReplyFlags; /* 0x00 */ 367 u_int8_t MSIxIndex; /* 0x01 */ 368 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 369 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 370} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 371 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 372 373/* Address Reply Descriptor */ 374typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 375{ 376 u_int8_t ReplyFlags; /* 0x00 */ 377 u_int8_t MSIxIndex; /* 0x01 */ 378 u_int16_t SMID; /* 0x02 */ 379 u_int32_t ReplyFrameAddress; /* 0x04 */ 380} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 381 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 382 383/* SCSI IO Success Reply Descriptor */ 384typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 385{ 386 u_int8_t ReplyFlags; /* 0x00 */ 387 u_int8_t MSIxIndex; /* 0x01 */ 388 u_int16_t SMID; /* 0x02 */ 389 u_int16_t TaskTag; /* 0x04 */ 390 u_int16_t Reserved1; /* 0x06 */ 391} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 392 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 393 Mpi2SCSIIOSuccessReplyDescriptor_t, 394 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 395 396/* TargetAssist Success Reply Descriptor */ 397typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 398{ 399 u_int8_t ReplyFlags; /* 0x00 */ 400 u_int8_t MSIxIndex; /* 0x01 */ 401 u_int16_t SMID; /* 0x02 */ 402 u_int8_t SequenceNumber; /* 0x04 */ 403 u_int8_t Reserved1; /* 0x05 */ 404 u_int16_t IoIndex; /* 0x06 */ 405} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 406 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 407 Mpi2TargetAssistSuccessReplyDescriptor_t, 408 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 409 410/* Target Command Buffer Reply Descriptor */ 411typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 412{ 413 u_int8_t ReplyFlags; /* 0x00 */ 414 u_int8_t MSIxIndex; /* 0x01 */ 415 u_int8_t VP_ID; /* 0x02 */ 416 u_int8_t Flags; /* 0x03 */ 417 u_int16_t InitiatorDevHandle; /* 0x04 */ 418 u_int16_t IoIndex; /* 0x06 */ 419} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 420 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 421 Mpi2TargetCommandBufferReplyDescriptor_t, 422 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 423 424/* RAID Accelerator Success Reply Descriptor */ 425typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 426{ 427 u_int8_t ReplyFlags; /* 0x00 */ 428 u_int8_t MSIxIndex; /* 0x01 */ 429 u_int16_t SMID; /* 0x02 */ 430 u_int32_t Reserved; /* 0x04 */ 431} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 432 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 433 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 434 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 435 436/* union of Reply Descriptors */ 437typedef union _MPI2_REPLY_DESCRIPTORS_UNION 438{ 439 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 440 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 441 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 442 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 443 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 444 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 445 u_int64_t Words; 446} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 447 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 448 449typedef struct { 450 volatile unsigned int val; 451} atomic_t; 452 453#define atomic_read(v) atomic_load_acq_int(&(v)->val) 454#define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 455#define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 456#define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 457 458/* IOCInit Request message */ 459typedef struct _MPI2_IOC_INIT_REQUEST 460{ 461 u_int8_t WhoInit; /* 0x00 */ 462 u_int8_t Reserved1; /* 0x01 */ 463 u_int8_t ChainOffset; /* 0x02 */ 464 u_int8_t Function; /* 0x03 */ 465 u_int16_t Reserved2; /* 0x04 */ 466 u_int8_t Reserved3; /* 0x06 */ 467 u_int8_t MsgFlags; /* 0x07 */ 468 u_int8_t VP_ID; /* 0x08 */ 469 u_int8_t VF_ID; /* 0x09 */ 470 u_int16_t Reserved4; /* 0x0A */ 471 u_int16_t MsgVersion; /* 0x0C */ 472 u_int16_t HeaderVersion; /* 0x0E */ 473 u_int32_t Reserved5; /* 0x10 */ 474 u_int16_t Reserved6; /* 0x14 */ 475 u_int8_t Reserved7; /* 0x16 */ 476 u_int8_t HostMSIxVectors; /* 0x17 */ 477 u_int16_t Reserved8; /* 0x18 */ 478 u_int16_t SystemRequestFrameSize; /* 0x1A */ 479 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 480 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 481 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 482 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 483 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 484 u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 485 u_int64_t ReplyFreeQueueAddress; /* 0x38 */ 486 u_int64_t TimeStamp; /* 0x40 */ 487} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 488 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 489 490/* 491 * MR private defines 492 */ 493#define MR_PD_INVALID 0xFFFF 494#define MAX_SPAN_DEPTH 8 495#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 496#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 497#define MAX_ROW_SIZE 32 498#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 499#define MAX_LOGICAL_DRIVES 64 500#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 501#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 502#define MAX_ARRAYS 128 503#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 504#define MAX_PHYSICAL_DEVICES 256 505#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 506#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD 507 508 509/******************************************************************* 510 * RAID map related structures 511 ********************************************************************/ 512 513typedef struct _MR_DEV_HANDLE_INFO { 514 u_int16_t curDevHdl; // the device handle currently used by fw to issue the command. 515 u_int8_t validHandles; // bitmap of valid device handles. 516 u_int8_t reserved; 517 u_int16_t devHandle[2]; // 0x04 dev handles for all the paths. 518} MR_DEV_HANDLE_INFO; 519 520typedef struct _MR_ARRAY_INFO { 521 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 522} MR_ARRAY_INFO; // 0x40, Total Size 523 524typedef struct _MR_QUAD_ELEMENT { 525 u_int64_t logStart; // 0x00 526 u_int64_t logEnd; // 0x08 527 u_int64_t offsetInSpan; // 0x10 528 u_int32_t diff; // 0x18 529 u_int32_t reserved1; // 0x1C 530} MR_QUAD_ELEMENT; // 0x20, Total size 531 532typedef struct _MR_SPAN_INFO { 533 u_int32_t noElements; // 0x00 534 u_int32_t reserved1; // 0x04 535 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08 536} MR_SPAN_INFO; // 0x108, Total size 537 538typedef struct _MR_LD_SPAN_ { // SPAN structure 539 u_int64_t startBlk; // 0x00, starting block number in array 540 u_int64_t numBlks; // 0x08, number of blocks 541 u_int16_t arrayRef; // 0x10, array reference 542 u_int8_t spanRowSize; // 0x11, span row size 543 u_int8_t spanRowDataSize; // 0x12, span row data size 544 u_int8_t reserved[4]; // 0x13, reserved 545} MR_LD_SPAN; // 0x18, Total Size 546 547typedef struct _MR_SPAN_BLOCK_INFO { 548 u_int64_t num_rows; // number of rows/span 549 MR_LD_SPAN span; // 0x08 550 MR_SPAN_INFO block_span_info; // 0x20 551} MR_SPAN_BLOCK_INFO; 552 553typedef struct _MR_LD_RAID { 554 struct { 555 u_int32_t fpCapable :1; 556 u_int32_t reserved5 :3; 557 u_int32_t ldPiMode :4; 558 u_int32_t pdPiMode :4; // Every Pd has to be same. 559 u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE) 560 u_int32_t fpWriteCapable :1; 561 u_int32_t fpReadCapable :1; 562 u_int32_t fpWriteAcrossStripe :1; 563 u_int32_t fpReadAcrossStripe :1; 564 u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO 565 u_int32_t reserved4 :7; 566 } capability; // 0x00 567 u_int32_t reserved6; 568 u_int64_t size; // 0x08, LD size in blocks 569 570 u_int8_t spanDepth; // 0x10, Total Number of Spans 571 u_int8_t level; // 0x11, RAID level 572 u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) 573 u_int8_t rowSize; // 0x13, number of disks in a row 574 575 u_int8_t rowDataSize; // 0x14, number of data disks in a row 576 u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK 577 u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E 578 u_int8_t SRL; // 0x17 579 580 u_int16_t targetId; // 0x18, ld Target Id. 581 u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE 582 u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc.. 583 u_int8_t modFactor; // 0x1c, same as rowSize, 584 u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 585 u_int16_t seqNum; // 0x1e, LD sequence number 586 587 struct { 588 u_int32_t ldSyncRequired:1; // This LD requires sync command before completing 589 u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead 590 u_int32_t reserved:30; 591 } flags; // 0x20 592 593 u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI 594 u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs 595 u_int8_t reserved2[3]; // 0x2D 596 u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD 597 struct { 598 u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16 599 u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK 600 u_int32_t reserved1:24; // 0x34 601 } exponent; 602 u_int8_t reserved3[0x80-0x38]; // 0x38 603} MR_LD_RAID; // 0x80, Total Size 604 605typedef struct _MR_LD_SPAN_MAP { 606 MR_LD_RAID ldRaid; // 0x00 607 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only. 608 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0 609} MR_LD_SPAN_MAP; // 0x9E0 610 611typedef struct _MR_FW_RAID_MAP { 612 u_int32_t totalSize; // total size of this structure, including this field. 613 union { 614 struct { // Simple method of version checking variables 615 u_int32_t maxLd; 616 u_int32_t maxSpanDepth; 617 u_int32_t maxRowSize; 618 u_int32_t maxPdCount; 619 u_int32_t maxArrays; 620 } validationInfo; 621 u_int32_t version[5]; 622 u_int32_t reserved1[5]; 623 } raid_desc; 624 u_int32_t ldCount; // count of lds. 625 u_int32_t Reserved1; 626 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20 627 // This doesn't correspond to 628 // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 629 // and FW LD is 2, and there is only one LD, FW will populate the 630 // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to 631 // help reduce the entire strcture size if there are few LDs or 632 // driver is looking info for 1 LD only. 633 u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs 634 u_int8_t reserved2[7]; 635 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8 636 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8 637 MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; 638} MR_FW_RAID_MAP; // 0x3288, Total Size 639 640typedef struct _LD_LOAD_BALANCE_INFO 641{ 642 u_int8_t loadBalanceFlag; 643 u_int8_t reserved1; 644 u_int16_t raid1DevHandle[2]; 645 atomic_t scsi_pending_cmds[2]; 646 u_int64_t last_accessed_block[2]; 647} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 648 649/* SPAN_SET is info caclulated from span info from Raid map per ld */ 650typedef struct _LD_SPAN_SET { 651 u_int64_t log_start_lba; 652 u_int64_t log_end_lba; 653 u_int64_t span_row_start; 654 u_int64_t span_row_end; 655 u_int64_t data_strip_start; 656 u_int64_t data_strip_end; 657 u_int64_t data_row_start; 658 u_int64_t data_row_end; 659 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 660 u_int32_t span_row_data_width; 661 u_int32_t diff; 662 u_int32_t reserved[2]; 663}LD_SPAN_SET, *PLD_SPAN_SET; 664 665typedef struct LOG_BLOCK_SPAN_INFO { 666 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 667}LD_SPAN_INFO, *PLD_SPAN_INFO; 668 669#pragma pack(1) 670typedef struct _MR_FW_RAID_MAP_ALL { 671 MR_FW_RAID_MAP raidMap; 672 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 673} MR_FW_RAID_MAP_ALL; 674#pragma pack() 675 676struct IO_REQUEST_INFO { 677 u_int64_t ldStartBlock; 678 u_int32_t numBlocks; 679 u_int16_t ldTgtId; 680 u_int8_t isRead; 681 u_int16_t devHandle; 682 u_int64_t pdBlock; 683 u_int8_t fpOkForIo; 684 u_int8_t IoforUnevenSpan; 685 u_int8_t start_span; 686 u_int8_t reserved; 687 u_int64_t start_row; 688}; 689 690typedef struct _MR_LD_TARGET_SYNC { 691 u_int8_t targetId; 692 u_int8_t reserved; 693 u_int16_t seqNum; 694} MR_LD_TARGET_SYNC; 695 696#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 697#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 698#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 699#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 700#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 701#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 702#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 703 704union desc_value { 705 u_int64_t word; 706 struct { 707 u_int32_t low; 708 u_int32_t high; 709 } u; 710}; 711 712/******************************************************************* 713 * Temporary command 714 ********************************************************************/ 715struct mrsas_tmp_dcmd { 716 void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd 717 lpaddr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD 718}; 719 720/******************************************************************* 721 * Register set, included legacy controllers 1068 and 1078, 722 * structure extended for 1078 registers 723 ********************************************************************/ 724#pragma pack(1) 725typedef struct _mrsas_register_set { 726 u_int32_t doorbell; /*0000h*/ 727 u_int32_t fusion_seq_offset; /*0004h*/ 728 u_int32_t fusion_host_diag; /*0008h*/ 729 u_int32_t reserved_01; /*000Ch*/ 730 731 u_int32_t inbound_msg_0; /*0010h*/ 732 u_int32_t inbound_msg_1; /*0014h*/ 733 u_int32_t outbound_msg_0; /*0018h*/ 734 u_int32_t outbound_msg_1; /*001Ch*/ 735 736 u_int32_t inbound_doorbell; /*0020h*/ 737 u_int32_t inbound_intr_status; /*0024h*/ 738 u_int32_t inbound_intr_mask; /*0028h*/ 739 740 u_int32_t outbound_doorbell; /*002Ch*/ 741 u_int32_t outbound_intr_status; /*0030h*/ 742 u_int32_t outbound_intr_mask; /*0034h*/ 743 744 u_int32_t reserved_1[2]; /*0038h*/ 745 746 u_int32_t inbound_queue_port; /*0040h*/ 747 u_int32_t outbound_queue_port; /*0044h*/ 748 749 u_int32_t reserved_2[9]; /*0048h*/ 750 u_int32_t reply_post_host_index; /*006Ch*/ 751 u_int32_t reserved_2_2[12]; /*0070h*/ 752 753 u_int32_t outbound_doorbell_clear; /*00A0h*/ 754 755 u_int32_t reserved_3[3]; /*00A4h*/ 756 757 u_int32_t outbound_scratch_pad ; /*00B0h*/ 758 u_int32_t outbound_scratch_pad_2; /*00B4h*/ 759 760 u_int32_t reserved_4[2]; /*00B8h*/ 761 762 u_int32_t inbound_low_queue_port ; /*00C0h*/ 763 764 u_int32_t inbound_high_queue_port ; /*00C4h*/ 765 766 u_int32_t reserved_5; /*00C8h*/ 767 u_int32_t res_6[11]; /*CCh*/ 768 u_int32_t host_diag; 769 u_int32_t seq_offset; 770 u_int32_t index_registers[807]; /*00CCh*/ 771 772} mrsas_reg_set; 773#pragma pack() 774 775/******************************************************************* 776 * Firmware Interface Defines 777 ******************************************************************* 778 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 779 * for protocol between the software and firmware. Commands are 780 * issued using "message frames". 781 ******************************************************************/ 782/* 783 * FW posts its state in upper 4 bits of outbound_msg_0 register 784 */ 785#define MFI_STATE_MASK 0xF0000000 786#define MFI_STATE_UNDEFINED 0x00000000 787#define MFI_STATE_BB_INIT 0x10000000 788#define MFI_STATE_FW_INIT 0x40000000 789#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 790#define MFI_STATE_FW_INIT_2 0x70000000 791#define MFI_STATE_DEVICE_SCAN 0x80000000 792#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 793#define MFI_STATE_FLUSH_CACHE 0xA0000000 794#define MFI_STATE_READY 0xB0000000 795#define MFI_STATE_OPERATIONAL 0xC0000000 796#define MFI_STATE_FAULT 0xF0000000 797#define MFI_RESET_REQUIRED 0x00000001 798#define MFI_RESET_ADAPTER 0x00000002 799#define MEGAMFI_FRAME_SIZE 64 800#define MRSAS_MFI_FRAME_SIZE 1024 801#define MRSAS_MFI_SENSE_SIZE 128 802 803/* 804 * During FW init, clear pending cmds & reset state using inbound_msg_0 805 * 806 * ABORT : Abort all pending cmds 807 * READY : Move from OPERATIONAL to READY state; discard queue info 808 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 809 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 810 * HOTPLUG : Resume from Hotplug 811 * MFI_STOP_ADP : Send signal to FW to stop processing 812 */ 813 814#define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20 815#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20 816#define DIAG_WRITE_ENABLE (0x00000080) 817#define DIAG_RESET_ADAPTER (0x00000004) 818 819#define MFI_ADP_RESET 0x00000040 820#define MFI_INIT_ABORT 0x00000001 821#define MFI_INIT_READY 0x00000002 822#define MFI_INIT_MFIMODE 0x00000004 823#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 824#define MFI_INIT_HOTPLUG 0x00000010 825#define MFI_STOP_ADP 0x00000020 826#define MFI_RESET_FLAGS MFI_INIT_READY| \ 827 MFI_INIT_MFIMODE| \ 828 MFI_INIT_ABORT 829 830/* 831 * MFI frame flags 832 */ 833#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 834#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 835#define MFI_FRAME_SGL32 0x0000 836#define MFI_FRAME_SGL64 0x0002 837#define MFI_FRAME_SENSE32 0x0000 838#define MFI_FRAME_SENSE64 0x0004 839#define MFI_FRAME_DIR_NONE 0x0000 840#define MFI_FRAME_DIR_WRITE 0x0008 841#define MFI_FRAME_DIR_READ 0x0010 842#define MFI_FRAME_DIR_BOTH 0x0018 843#define MFI_FRAME_IEEE 0x0020 844 845/* 846 * Definition for cmd_status 847 */ 848#define MFI_CMD_STATUS_POLL_MODE 0xFF 849 850/* 851 * MFI command opcodes 852 */ 853#define MFI_CMD_INIT 0x00 854#define MFI_CMD_LD_READ 0x01 855#define MFI_CMD_LD_WRITE 0x02 856#define MFI_CMD_LD_SCSI_IO 0x03 857#define MFI_CMD_PD_SCSI_IO 0x04 858#define MFI_CMD_DCMD 0x05 859#define MFI_CMD_ABORT 0x06 860#define MFI_CMD_SMP 0x07 861#define MFI_CMD_STP 0x08 862#define MFI_CMD_INVALID 0xff 863 864#define MR_DCMD_CTRL_GET_INFO 0x01010000 865#define MR_DCMD_LD_GET_LIST 0x03010000 866#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 867#define MR_FLUSH_CTRL_CACHE 0x01 868#define MR_FLUSH_DISK_CACHE 0x02 869 870#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 871#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 872#define MR_ENABLE_DRIVE_SPINDOWN 0x01 873 874#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 875#define MR_DCMD_CTRL_EVENT_GET 0x01040300 876#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 877#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 878 879#define MR_DCMD_CLUSTER 0x08000000 880#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 881#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 882#define MR_DCMD_PD_LIST_QUERY 0x02010100 883 884#define MR_DCMD_CTRL_MISC_CPX 0x0100e200 885#define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 886#define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 887#define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 888#define MAX_MR_ROW_SIZE 32 889#define MR_CPX_DIR_WRITE 1 890#define MR_CPX_DIR_READ 0 891#define MR_CPX_VERSION 1 892 893#define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics 894 895#define MR_EVT_CFG_CLEARED 0x0004 896 897#define MR_EVT_LD_STATE_CHANGE 0x0051 898#define MR_EVT_PD_INSERTED 0x005b 899#define MR_EVT_PD_REMOVED 0x0070 900#define MR_EVT_LD_CREATED 0x008a 901#define MR_EVT_LD_DELETED 0x008b 902#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 903#define MR_EVT_LD_OFFLINE 0x00fc 904#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 905#define MR_EVT_CTRL_PERF_COLLECTION 0x017e 906 907/* 908 * MFI command completion codes 909 */ 910enum MFI_STAT { 911 MFI_STAT_OK = 0x00, 912 MFI_STAT_INVALID_CMD = 0x01, 913 MFI_STAT_INVALID_DCMD = 0x02, 914 MFI_STAT_INVALID_PARAMETER = 0x03, 915 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 916 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 917 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 918 MFI_STAT_APP_IN_USE = 0x07, 919 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 920 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 921 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 922 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 923 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 924 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 925 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 926 MFI_STAT_FLASH_BUSY = 0x0f, 927 MFI_STAT_FLASH_ERROR = 0x10, 928 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 929 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 930 MFI_STAT_FLASH_NOT_OPEN = 0x13, 931 MFI_STAT_FLASH_NOT_STARTED = 0x14, 932 MFI_STAT_FLUSH_FAILED = 0x15, 933 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 934 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 935 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 936 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 937 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 938 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 939 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 940 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 941 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 942 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 943 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 944 MFI_STAT_MFC_HW_ERROR = 0x21, 945 MFI_STAT_NO_HW_PRESENT = 0x22, 946 MFI_STAT_NOT_FOUND = 0x23, 947 MFI_STAT_NOT_IN_ENCL = 0x24, 948 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 949 MFI_STAT_PD_TYPE_WRONG = 0x26, 950 MFI_STAT_PR_DISABLED = 0x27, 951 MFI_STAT_ROW_INDEX_INVALID = 0x28, 952 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 953 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 954 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 955 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 956 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 957 MFI_STAT_SCSI_IO_FAILED = 0x2e, 958 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 959 MFI_STAT_SHUTDOWN_FAILED = 0x30, 960 MFI_STAT_TIME_NOT_SET = 0x31, 961 MFI_STAT_WRONG_STATE = 0x32, 962 MFI_STAT_LD_OFFLINE = 0x33, 963 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 964 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 965 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 966 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 967 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 968 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 969 970 MFI_STAT_INVALID_STATUS = 0xFF 971}; 972 973/* 974 * Number of mailbox bytes in DCMD message frame 975 */ 976#define MFI_MBOX_SIZE 12 977 978enum MR_EVT_CLASS { 979 980 MR_EVT_CLASS_DEBUG = -2, 981 MR_EVT_CLASS_PROGRESS = -1, 982 MR_EVT_CLASS_INFO = 0, 983 MR_EVT_CLASS_WARNING = 1, 984 MR_EVT_CLASS_CRITICAL = 2, 985 MR_EVT_CLASS_FATAL = 3, 986 MR_EVT_CLASS_DEAD = 4, 987 988}; 989 990enum MR_EVT_LOCALE { 991 992 MR_EVT_LOCALE_LD = 0x0001, 993 MR_EVT_LOCALE_PD = 0x0002, 994 MR_EVT_LOCALE_ENCL = 0x0004, 995 MR_EVT_LOCALE_BBU = 0x0008, 996 MR_EVT_LOCALE_SAS = 0x0010, 997 MR_EVT_LOCALE_CTRL = 0x0020, 998 MR_EVT_LOCALE_CONFIG = 0x0040, 999 MR_EVT_LOCALE_CLUSTER = 0x0080, 1000 MR_EVT_LOCALE_ALL = 0xffff, 1001 1002}; 1003 1004enum MR_EVT_ARGS { 1005 1006 MR_EVT_ARGS_NONE, 1007 MR_EVT_ARGS_CDB_SENSE, 1008 MR_EVT_ARGS_LD, 1009 MR_EVT_ARGS_LD_COUNT, 1010 MR_EVT_ARGS_LD_LBA, 1011 MR_EVT_ARGS_LD_OWNER, 1012 MR_EVT_ARGS_LD_LBA_PD_LBA, 1013 MR_EVT_ARGS_LD_PROG, 1014 MR_EVT_ARGS_LD_STATE, 1015 MR_EVT_ARGS_LD_STRIP, 1016 MR_EVT_ARGS_PD, 1017 MR_EVT_ARGS_PD_ERR, 1018 MR_EVT_ARGS_PD_LBA, 1019 MR_EVT_ARGS_PD_LBA_LD, 1020 MR_EVT_ARGS_PD_PROG, 1021 MR_EVT_ARGS_PD_STATE, 1022 MR_EVT_ARGS_PCI, 1023 MR_EVT_ARGS_RATE, 1024 MR_EVT_ARGS_STR, 1025 MR_EVT_ARGS_TIME, 1026 MR_EVT_ARGS_ECC, 1027 MR_EVT_ARGS_LD_PROP, 1028 MR_EVT_ARGS_PD_SPARE, 1029 MR_EVT_ARGS_PD_INDEX, 1030 MR_EVT_ARGS_DIAG_PASS, 1031 MR_EVT_ARGS_DIAG_FAIL, 1032 MR_EVT_ARGS_PD_LBA_LBA, 1033 MR_EVT_ARGS_PORT_PHY, 1034 MR_EVT_ARGS_PD_MISSING, 1035 MR_EVT_ARGS_PD_ADDRESS, 1036 MR_EVT_ARGS_BITMAP, 1037 MR_EVT_ARGS_CONNECTOR, 1038 MR_EVT_ARGS_PD_PD, 1039 MR_EVT_ARGS_PD_FRU, 1040 MR_EVT_ARGS_PD_PATHINFO, 1041 MR_EVT_ARGS_PD_POWER_STATE, 1042 MR_EVT_ARGS_GENERIC, 1043}; 1044 1045 1046/* 1047 * Thunderbolt (and later) Defines 1048 */ 1049#define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1050#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1051#define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1052#define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1053#define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1054#define MRSAS_LOAD_BALANCE_FLAG 0x1 1055#define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1056#define HOST_DIAG_WRITE_ENABLE 0x80 1057#define HOST_DIAG_RESET_ADAPTER 0x4 1058#define MRSAS_TBOLT_MAX_RESET_TRIES 3 1059#define MRSAS_MAX_MFI_CMDS 32 1060 1061/* 1062 * Invader Defines 1063 */ 1064#define MPI2_TYPE_CUDA 0x2 1065#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1066#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1067#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1068#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1069#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1070 1071/* 1072 * T10 PI defines 1073 */ 1074#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1075#define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1076#define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1077#define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1078#define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1079#define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1080#define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1081#define MRSAS_SCSIBLOCKSIZE 512 1082 1083/* 1084 * Raid context flags 1085 */ 1086#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1087#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1088typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1089 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1090 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1091} MR_RAID_FLAGS_IO_SUB_TYPE; 1092 1093/* 1094 * Request descriptor types 1095 */ 1096#define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1097#define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1098#define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1099#define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1100#define MRSAS_FP_CMD_LEN 16 1101#define MRSAS_FUSION_IN_RESET 0 1102 1103#define RAID_CTX_SPANARM_ARM_SHIFT (0) 1104#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1105#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1106#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1107 1108/* 1109 * Define region lock types 1110 */ 1111typedef enum _REGION_TYPE { 1112 REGION_TYPE_UNUSED = 0, // lock is currently not active 1113 REGION_TYPE_SHARED_READ = 1, // shared lock (for reads) 1114 REGION_TYPE_SHARED_WRITE = 2, 1115 REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes) 1116} REGION_TYPE; 1117 1118/* 1119 * MR private defines 1120 */ 1121#define MR_PD_INVALID 0xFFFF 1122#define MAX_SPAN_DEPTH 8 1123#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 1124#define MAX_ROW_SIZE 32 1125#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 1126#define MAX_LOGICAL_DRIVES 64 1127#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 1128#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 1129#define MAX_ARRAYS 128 1130#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 1131#define MAX_PHYSICAL_DEVICES 256 1132#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 1133#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 1134 1135/* 1136 * SCSI-CAM Related Defines 1137 */ 1138#define MRSAS_SCSI_MAX_LUNS 0 //zero for now 1139#define MRSAS_SCSI_INITIATOR_ID 255 1140#define MRSAS_SCSI_MAX_CMDS 8 1141#define MRSAS_SCSI_MAX_CDB_LEN 16 1142#define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1143#define MRSAS_MAX_SGL 70 1144#define MRSAS_MAX_IO_SIZE (256 * 1024) 1145#define MRSAS_INTERNAL_CMDS 32 1146 1147/* Request types */ 1148#define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1149#define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1150#define MRSAS_REQ_TYPE_PASSTHRU 0x2 1151#define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1152#define MRSAS_REQ_TYPE_SCSI_IO 0x4 1153 1154/* Request states */ 1155#define MRSAS_REQ_STATE_FREE 0 1156#define MRSAS_REQ_STATE_BUSY 1 1157#define MRSAS_REQ_STATE_TRAN 2 1158#define MRSAS_REQ_STATE_COMPLETE 3 1159 1160enum mrsas_req_flags { 1161 MRSAS_DIR_UNKNOWN = 0x1, 1162 MRSAS_DIR_IN = 0x2, 1163 MRSAS_DIR_OUT = 0x4, 1164 MRSAS_DIR_NONE = 0x8, 1165}; 1166 1167/* 1168 * MPT Command Structure 1169 */ 1170struct mrsas_mpt_cmd { 1171 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1172 lpaddr_t io_request_phys_addr; 1173 MPI2_SGE_IO_UNION *chain_frame; 1174 lpaddr_t chain_frame_phys_addr; 1175 u_int32_t sge_count; 1176 u_int8_t *sense; 1177 lpaddr_t sense_phys_addr; 1178 u_int8_t retry_for_fw_reset; 1179 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1180 u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete 1181 u_int32_t index; 1182 u_int8_t flags; 1183 u_int8_t load_balance; 1184 size_t length; // request length 1185 u_int32_t error_code; // error during request dmamap load 1186 /* bus_dmamap_t data_dmamap; */ 1187 void *data; 1188 union ccb *ccb_ptr; // pointer to ccb 1189 /* struct callout cm_callout; */ 1190 struct megaraid_ctrl *sc; 1191 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1192}; 1193 1194/* 1195 * MFI Command Structure 1196 */ 1197struct mrsas_mfi_cmd { 1198 union mrsas_frame *frame; 1199 void *frame_mem; // mfi frame virtual addr 1200 lpaddr_t frame_phys_addr; // mfi frame physical addr 1201 u_int8_t *sense; 1202 void *sense_mem; // mfi sense virtual addr 1203 lpaddr_t sense_phys_addr; 1204 u_int32_t index; 1205 u_int8_t sync_cmd; 1206 u_int8_t cmd_status; 1207 u_int8_t abort_aen; 1208 u_int8_t retry_for_fw_reset; 1209 struct megaraid_ctrl *sc; 1210 union ccb *ccb_ptr; 1211 union { 1212 struct { 1213 u_int16_t smid; 1214 u_int16_t resvd; 1215 } context; 1216 u_int32_t frame_count; 1217 } cmd_id; 1218 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1219}; 1220 1221 1222/* 1223 * define constants for device list query options 1224 */ 1225enum MR_PD_QUERY_TYPE { 1226 MR_PD_QUERY_TYPE_ALL = 0, 1227 MR_PD_QUERY_TYPE_STATE = 1, 1228 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1229 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1230 MR_PD_QUERY_TYPE_SPEED = 4, 1231 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1232}; 1233 1234#define MR_EVT_CFG_CLEARED 0x0004 1235#define MR_EVT_LD_STATE_CHANGE 0x0051 1236#define MR_EVT_PD_INSERTED 0x005b 1237#define MR_EVT_PD_REMOVED 0x0070 1238#define MR_EVT_LD_CREATED 0x008a 1239#define MR_EVT_LD_DELETED 0x008b 1240#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1241#define MR_EVT_LD_OFFLINE 0x00fc 1242#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1243 1244enum MR_PD_STATE { 1245 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1246 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1247 MR_PD_STATE_HOT_SPARE = 0x02, 1248 MR_PD_STATE_OFFLINE = 0x10, 1249 MR_PD_STATE_FAILED = 0x11, 1250 MR_PD_STATE_REBUILD = 0x14, 1251 MR_PD_STATE_ONLINE = 0x18, 1252 MR_PD_STATE_COPYBACK = 0x20, 1253 MR_PD_STATE_SYSTEM = 0x40, 1254 }; 1255 1256 /* 1257 * defines the physical drive address structure 1258 */ 1259#pragma pack(1) 1260struct MR_PD_ADDRESS { 1261 u_int16_t deviceId; 1262 u_int16_t enclDeviceId; 1263 1264 union { 1265 struct { 1266 u_int8_t enclIndex; 1267 u_int8_t slotNumber; 1268 } mrPdAddress; 1269 struct { 1270 u_int8_t enclPosition; 1271 u_int8_t enclConnectorIndex; 1272 } mrEnclAddress; 1273 } u1; 1274 u_int8_t scsiDevType; 1275 union { 1276 u_int8_t connectedPortBitmap; 1277 u_int8_t connectedPortNumbers; 1278 } u2; 1279 u_int64_t sasAddr[2]; 1280}; 1281#pragma pack() 1282 1283/* 1284 * defines the physical drive list structure 1285 */ 1286#pragma pack(1) 1287struct MR_PD_LIST { 1288 u_int32_t size; 1289 u_int32_t count; 1290 struct MR_PD_ADDRESS addr[1]; 1291}; 1292#pragma pack() 1293 1294#pragma pack(1) 1295struct mrsas_pd_list { 1296 u_int16_t tid; 1297 u_int8_t driveType; 1298 u_int8_t driveState; 1299}; 1300#pragma pack() 1301 1302 /* 1303 * defines the logical drive reference structure 1304 */ 1305typedef union _MR_LD_REF { // LD reference structure 1306 struct { 1307 u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID) 1308 u_int8_t reserved; // reserved to make in line with MR_PD_REF 1309 u_int16_t seqNum; // Sequence Number 1310 } ld_context; 1311 u_int32_t ref; // shorthand reference to full 32-bits 1312} MR_LD_REF; // 4 bytes 1313 1314 1315/* 1316 * defines the logical drive list structure 1317 */ 1318#pragma pack(1) 1319struct MR_LD_LIST { 1320 u_int32_t ldCount; // number of LDs 1321 u_int32_t reserved; // pad to 8-byte boundary 1322 struct { 1323 MR_LD_REF ref; // LD reference 1324 u_int8_t state; // current LD state (MR_LD_STATE) 1325 u_int8_t reserved[3]; // pad to 8-byte boundary 1326 u_int64_t size; // LD size 1327 } ldList[MAX_LOGICAL_DRIVES]; 1328}; 1329#pragma pack() 1330 1331/* 1332 * SAS controller properties 1333 */ 1334#pragma pack(1) 1335struct mrsas_ctrl_prop { 1336 u_int16_t seq_num; 1337 u_int16_t pred_fail_poll_interval; 1338 u_int16_t intr_throttle_count; 1339 u_int16_t intr_throttle_timeouts; 1340 u_int8_t rebuild_rate; 1341 u_int8_t patrol_read_rate; 1342 u_int8_t bgi_rate; 1343 u_int8_t cc_rate; 1344 u_int8_t recon_rate; 1345 u_int8_t cache_flush_interval; 1346 u_int8_t spinup_drv_count; 1347 u_int8_t spinup_delay; 1348 u_int8_t cluster_enable; 1349 u_int8_t coercion_mode; 1350 u_int8_t alarm_enable; 1351 u_int8_t disable_auto_rebuild; 1352 u_int8_t disable_battery_warn; 1353 u_int8_t ecc_bucket_size; 1354 u_int16_t ecc_bucket_leak_rate; 1355 u_int8_t restore_hotspare_on_insertion; 1356 u_int8_t expose_encl_devices; 1357 u_int8_t maintainPdFailHistory; 1358 u_int8_t disallowHostRequestReordering; 1359 u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency 1360 u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE) 1361 u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes 1362 // like SGPIO, i2c SEP using h/w mechansim 1363 // like GPIO pins. 1364 // 1 - disable auto detect SGPIO, 1365 // 2 - disable i2c SEP auto detect 1366 // 3 - disable both auto detect 1367 u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in 1368 // snapshot repository, for metadata and user data. 1369 // 1=5%, 2=10%, 3=15% and so on. 1370 /* 1371 * Add properties that can be controlled by a bit in the following structure. 1372 */ 1373 struct { 1374 u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack 1375 // (0=copback enabled) 1376 u_int32_t SMARTerEnabled : 1; 1377 u_int32_t prCorrectUnconfiguredAreas : 1; 1378 u_int32_t useFdeOnly : 1; 1379 u_int32_t disableNCQ : 1; 1380 u_int32_t SSDSMARTerEnabled : 1; 1381 u_int32_t SSDPatrolReadEnabled : 1; 1382 u_int32_t enableSpinDownUnconfigured : 1; 1383 u_int32_t autoEnhancedImport : 1; 1384 u_int32_t enableSecretKeyControl : 1; 1385 u_int32_t disableOnlineCtrlReset : 1; 1386 u_int32_t allowBootWithPinnedCache : 1; 1387 u_int32_t disableSpinDownHS : 1; 1388 u_int32_t enableJBOD : 1; 1389 u_int32_t reserved :18; 1390 } OnOffProperties; 1391 u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto 1392 // snapshot in snapshot repository, for 1393 // metadata and user data. 1394 // 1=5%, 2=10%, 3=15% and so on. 1395 u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a % 1396 // of source LD capacity. 0=READ only. 1397 // 1=5%, 2=10%, 3=15% and so on 1398 u_int16_t spinDownTime; // # of idle minutes before device is spun 1399 // down (0=use FW defaults). 1400 u_int8_t reserved[24]; 1401 1402}; 1403#pragma pack() 1404 1405 1406/* 1407 * SAS controller information 1408 */ 1409//#pragma pack(1) 1410struct mrsas_ctrl_info { 1411 /* 1412 * PCI device information 1413 */ 1414 struct { 1415 u_int16_t vendor_id; 1416 u_int16_t device_id; 1417 u_int16_t sub_vendor_id; 1418 u_int16_t sub_device_id; 1419 u_int8_t reserved[24]; 1420 } __packed pci; 1421 /* 1422 * Host interface information 1423 */ 1424 struct { 1425 u_int8_t PCIX:1; 1426 u_int8_t PCIE:1; 1427 u_int8_t iSCSI:1; 1428 u_int8_t SAS_3G:1; 1429 u_int8_t reserved_0:4; 1430 u_int8_t reserved_1[6]; 1431 u_int8_t port_count; 1432 u_int64_t port_addr[8]; 1433 } __packed host_interface; 1434 /* 1435 * Device (backend) interface information 1436 */ 1437 struct { 1438 u_int8_t SPI:1; 1439 u_int8_t SAS_3G:1; 1440 u_int8_t SATA_1_5G:1; 1441 u_int8_t SATA_3G:1; 1442 u_int8_t reserved_0:4; 1443 u_int8_t reserved_1[6]; 1444 u_int8_t port_count; 1445 u_int64_t port_addr[8]; 1446 } __packed device_interface; 1447 1448 /* 1449 * List of components residing in flash. All str are null terminated 1450 */ 1451 u_int32_t image_check_word; 1452 u_int32_t image_component_count; 1453 1454 struct { 1455 char name[8]; 1456 char version[32]; 1457 char build_date[16]; 1458 char built_time[16]; 1459 } __packed image_component[8]; 1460 /* 1461 * List of flash components that have been flashed on the card, but 1462 * are not in use, pending reset of the adapter. This list will be 1463 * empty if a flash operation has not occurred. All stings are null 1464 * terminated 1465 */ 1466 u_int32_t pending_image_component_count; 1467 1468 struct { 1469 char name[8]; 1470 char version[32]; 1471 char build_date[16]; 1472 char build_time[16]; 1473 } __packed pending_image_component[8]; 1474 1475 u_int8_t max_arms; 1476 u_int8_t max_spans; 1477 u_int8_t max_arrays; 1478 u_int8_t max_lds; 1479 char product_name[80]; 1480 char serial_no[32]; 1481 1482 /* 1483 * Other physical/controller/operation information. Indicates the 1484 * presence of the hardware 1485 */ 1486 struct { 1487 u_int32_t bbu:1; 1488 u_int32_t alarm:1; 1489 u_int32_t nvram:1; 1490 u_int32_t uart:1; 1491 u_int32_t reserved:28; 1492 } __packed hw_present; 1493 1494 u_int32_t current_fw_time; 1495 1496 /* 1497 * Maximum data transfer sizes 1498 */ 1499 u_int16_t max_concurrent_cmds; 1500 u_int16_t max_sge_count; 1501 u_int32_t max_request_size; 1502 1503 /* 1504 * Logical and physical device counts 1505 */ 1506 u_int16_t ld_present_count; 1507 u_int16_t ld_degraded_count; 1508 u_int16_t ld_offline_count; 1509 1510 u_int16_t pd_present_count; 1511 u_int16_t pd_disk_present_count; 1512 u_int16_t pd_disk_pred_failure_count; 1513 u_int16_t pd_disk_failed_count; 1514 1515 /* 1516 * Memory size information 1517 */ 1518 u_int16_t nvram_size; 1519 u_int16_t memory_size; 1520 u_int16_t flash_size; 1521 1522 /* 1523 * Error counters 1524 */ 1525 u_int16_t mem_correctable_error_count; 1526 u_int16_t mem_uncorrectable_error_count; 1527 1528 /* 1529 * Cluster information 1530 */ 1531 u_int8_t cluster_permitted; 1532 u_int8_t cluster_active; 1533 1534 /* 1535 * Additional max data transfer sizes 1536 */ 1537 u_int16_t max_strips_per_io; 1538 1539 /* 1540 * Controller capabilities structures 1541 */ 1542 struct { 1543 u_int32_t raid_level_0:1; 1544 u_int32_t raid_level_1:1; 1545 u_int32_t raid_level_5:1; 1546 u_int32_t raid_level_1E:1; 1547 u_int32_t raid_level_6:1; 1548 u_int32_t reserved:27; 1549 } __packed raid_levels; 1550 1551 struct { 1552 u_int32_t rbld_rate:1; 1553 u_int32_t cc_rate:1; 1554 u_int32_t bgi_rate:1; 1555 u_int32_t recon_rate:1; 1556 u_int32_t patrol_rate:1; 1557 u_int32_t alarm_control:1; 1558 u_int32_t cluster_supported:1; 1559 u_int32_t bbu:1; 1560 u_int32_t spanning_allowed:1; 1561 u_int32_t dedicated_hotspares:1; 1562 u_int32_t revertible_hotspares:1; 1563 u_int32_t foreign_config_import:1; 1564 u_int32_t self_diagnostic:1; 1565 u_int32_t mixed_redundancy_arr:1; 1566 u_int32_t global_hot_spares:1; 1567 u_int32_t reserved:17; 1568 } __packed adapter_operations; 1569 1570 struct { 1571 u_int32_t read_policy:1; 1572 u_int32_t write_policy:1; 1573 u_int32_t io_policy:1; 1574 u_int32_t access_policy:1; 1575 u_int32_t disk_cache_policy:1; 1576 u_int32_t reserved:27; 1577 } __packed ld_operations; 1578 1579 struct { 1580 u_int8_t min; 1581 u_int8_t max; 1582 u_int8_t reserved[2]; 1583 } __packed stripe_sz_ops; 1584 1585 struct { 1586 u_int32_t force_online:1; 1587 u_int32_t force_offline:1; 1588 u_int32_t force_rebuild:1; 1589 u_int32_t reserved:29; 1590 } __packed pd_operations; 1591 1592 struct { 1593 u_int32_t ctrl_supports_sas:1; 1594 u_int32_t ctrl_supports_sata:1; 1595 u_int32_t allow_mix_in_encl:1; 1596 u_int32_t allow_mix_in_ld:1; 1597 u_int32_t allow_sata_in_cluster:1; 1598 u_int32_t reserved:27; 1599 } __packed pd_mix_support; 1600 1601 /* 1602 * Define ECC single-bit-error bucket information 1603 */ 1604 u_int8_t ecc_bucket_count; 1605 u_int8_t reserved_2[11]; 1606 1607 /* 1608 * Include the controller properties (changeable items) 1609 */ 1610 struct mrsas_ctrl_prop properties; 1611 1612 /* 1613 * Define FW pkg version (set in envt v'bles on OEM basis) 1614 */ 1615 char package_version[0x60]; 1616 1617 /* 1618 * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8, 1619 * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be 1620 * populated in deviceInterfacePortAddr2. 1621 */ 1622 u_int64_t deviceInterfacePortAddr2[8]; //0x6a0 1623 u_int8_t reserved3[128]; //0x6e0 1624 1625 struct { //0x760 1626 u_int16_t minPdRaidLevel_0 : 4; 1627 u_int16_t maxPdRaidLevel_0 : 12; 1628 1629 u_int16_t minPdRaidLevel_1 : 4; 1630 u_int16_t maxPdRaidLevel_1 : 12; 1631 1632 u_int16_t minPdRaidLevel_5 : 4; 1633 u_int16_t maxPdRaidLevel_5 : 12; 1634 1635 u_int16_t minPdRaidLevel_1E : 4; 1636 u_int16_t maxPdRaidLevel_1E : 12; 1637 1638 u_int16_t minPdRaidLevel_6 : 4; 1639 u_int16_t maxPdRaidLevel_6 : 12; 1640 1641 u_int16_t minPdRaidLevel_10 : 4; 1642 u_int16_t maxPdRaidLevel_10 : 12; 1643 1644 u_int16_t minPdRaidLevel_50 : 4; 1645 u_int16_t maxPdRaidLevel_50 : 12; 1646 1647 u_int16_t minPdRaidLevel_60 : 4; 1648 u_int16_t maxPdRaidLevel_60 : 12; 1649 1650 u_int16_t minPdRaidLevel_1E_RLQ0 : 4; 1651 u_int16_t maxPdRaidLevel_1E_RLQ0 : 12; 1652 1653 u_int16_t minPdRaidLevel_1E0_RLQ0 : 4; 1654 u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12; 1655 1656 u_int16_t reserved[6]; 1657 } pdsForRaidLevels; 1658 1659 u_int16_t maxPds; //0x780 1660 u_int16_t maxDedHSPs; //0x782 1661 u_int16_t maxGlobalHSPs; //0x784 1662 u_int16_t ddfSize; //0x786 1663 u_int8_t maxLdsPerArray; //0x788 1664 u_int8_t partitionsInDDF; //0x789 1665 u_int8_t lockKeyBinding; //0x78a 1666 u_int8_t maxPITsPerLd; //0x78b 1667 u_int8_t maxViewsPerLd; //0x78c 1668 u_int8_t maxTargetId; //0x78d 1669 u_int16_t maxBvlVdSize; //0x78e 1670 1671 u_int16_t maxConfigurableSSCSize; //0x790 1672 u_int16_t currentSSCsize; //0x792 1673 1674 char expanderFwVersion[12]; //0x794 1675 1676 u_int16_t PFKTrialTimeRemaining; //0x7A0 1677 1678 u_int16_t cacheMemorySize; //0x7A2 1679 1680 struct { //0x7A4 1681 u_int32_t supportPIcontroller :1; 1682 u_int32_t supportLdPIType1 :1; 1683 u_int32_t supportLdPIType2 :1; 1684 u_int32_t supportLdPIType3 :1; 1685 u_int32_t supportLdBBMInfo :1; 1686 u_int32_t supportShieldState :1; 1687 u_int32_t blockSSDWriteCacheChange :1; 1688 u_int32_t supportSuspendResumeBGops :1; 1689 u_int32_t supportEmergencySpares :1; 1690 u_int32_t supportSetLinkSpeed :1; 1691 u_int32_t supportBootTimePFKChange :1; 1692 u_int32_t supportJBOD :1; 1693 u_int32_t disableOnlinePFKChange :1; 1694 u_int32_t supportPerfTuning :1; 1695 u_int32_t supportSSDPatrolRead :1; 1696 u_int32_t realTimeScheduler :1; 1697 1698 u_int32_t supportResetNow :1; 1699 u_int32_t supportEmulatedDrives :1; 1700 u_int32_t headlessMode :1; 1701 u_int32_t dedicatedHotSparesLimited :1; 1702 1703 1704 u_int32_t supportUnevenSpans :1; 1705 u_int32_t reserved :11; 1706 } adapterOperations2; 1707 1708 u_int8_t driverVersion[32]; //0x7A8 1709 u_int8_t maxDAPdCountSpinup60; //0x7C8 1710 u_int8_t temperatureROC; //0x7C9 1711 u_int8_t temperatureCtrl; //0x7CA 1712 u_int8_t reserved4; //0x7CB 1713 u_int16_t maxConfigurablePds; //0x7CC 1714 1715 1716 u_int8_t reserved5[2]; //0x7CD reserved for future use 1717 1718 /* 1719 * HA cluster information 1720 */ 1721 struct { 1722 u_int32_t peerIsPresent :1; 1723 u_int32_t peerIsIncompatible :1; 1724 1725 u_int32_t hwIncompatible :1; 1726 u_int32_t fwVersionMismatch :1; 1727 u_int32_t ctrlPropIncompatible :1; 1728 u_int32_t premiumFeatureMismatch :1; 1729 u_int32_t reserved :26; 1730 } cluster; 1731 1732 char clusterId[16]; //0x7D4 1733 1734 u_int8_t pad[0x800-0x7E4]; //0x7E4 1735} __packed; 1736 1737/* 1738 * Ld and PD Max Support Defines 1739 */ 1740#define MRSAS_MAX_PD 256 1741#define MRSAS_MAX_LD 64 1742 1743/* 1744 * When SCSI mid-layer calls driver's reset routine, driver waits for 1745 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1746 * that the driver cannot _actually_ abort or reset pending commands. While 1747 * it is waiting for the commands to complete, it prints a diagnostic message 1748 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1749 */ 1750#define MRSAS_RESET_WAIT_TIME 180 1751#define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1752#define MRSAS_IOC_INIT_WAIT_TIME 60 1753#define MRSAS_RESET_NOTICE_INTERVAL 5 1754#define MRSAS_IOCTL_CMD 0 1755#define MRSAS_DEFAULT_CMD_TIMEOUT 90 1756#define MRSAS_THROTTLE_QUEUE_DEPTH 16 1757 1758/* 1759 * FW reports the maximum of number of commands that it can accept (maximum 1760 * commands that can be outstanding) at any time. The driver must report a 1761 * lower number to the mid layer because it can issue a few internal commands 1762 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1763 * is shown below 1764 */ 1765#define MRSAS_INT_CMDS 32 1766#define MRSAS_SKINNY_INT_CMDS 5 1767#define MRSAS_MAX_MSIX_QUEUES 16 1768 1769/* 1770 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1771 * SGLs based on the size of bus_addr_t 1772 */ 1773#define IS_DMA64 (sizeof(bus_addr_t) == 8) 1774 1775#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt 1776#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1777#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1778#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt 1779 1780#define MFI_OB_INTR_STATUS_MASK 0x00000002 1781#define MFI_POLL_TIMEOUT_SECS 60 1782 1783#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1784#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1785#define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1786#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1787#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1788#define MFI_1068_PCSR_OFFSET 0x84 1789#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1790#define MFI_1068_FW_READY 0xDDDD0000 1791 1792#pragma pack(1) 1793struct mrsas_sge32 { 1794 u_int32_t phys_addr; 1795 u_int32_t length; 1796}; 1797#pragma pack() 1798 1799#pragma pack(1) 1800struct mrsas_sge64 { 1801 u_int64_t phys_addr; 1802 u_int32_t length; 1803}; 1804#pragma pack() 1805 1806#pragma pack() 1807union mrsas_sgl { 1808 struct mrsas_sge32 sge32[1]; 1809 struct mrsas_sge64 sge64[1]; 1810}; 1811#pragma pack() 1812 1813#pragma pack(1) 1814struct mrsas_header { 1815 u_int8_t cmd; /*00e */ 1816 u_int8_t sense_len; /*01h */ 1817 u_int8_t cmd_status; /*02h */ 1818 u_int8_t scsi_status; /*03h */ 1819 1820 u_int8_t target_id; /*04h */ 1821 u_int8_t lun; /*05h */ 1822 u_int8_t cdb_len; /*06h */ 1823 u_int8_t sge_count; /*07h */ 1824 1825 u_int32_t context; /*08h */ 1826 u_int32_t pad_0; /*0Ch */ 1827 1828 u_int16_t flags; /*10h */ 1829 u_int16_t timeout; /*12h */ 1830 u_int32_t data_xferlen; /*14h */ 1831}; 1832#pragma pack() 1833 1834#pragma pack(1) 1835struct mrsas_init_frame { 1836 u_int8_t cmd; /*00h */ 1837 u_int8_t reserved_0; /*01h */ 1838 u_int8_t cmd_status; /*02h */ 1839 1840 u_int8_t reserved_1; /*03h */ 1841 u_int32_t reserved_2; /*04h */ 1842 1843 u_int32_t context; /*08h */ 1844 u_int32_t pad_0; /*0Ch */ 1845 1846 u_int16_t flags; /*10h */ 1847 u_int16_t reserved_3; /*12h */ 1848 u_int32_t data_xfer_len; /*14h */ 1849 1850 u_int32_t queue_info_new_phys_addr_lo; /*18h */ 1851 u_int32_t queue_info_new_phys_addr_hi; /*1Ch */ 1852 u_int32_t queue_info_old_phys_addr_lo; /*20h */ 1853 u_int32_t queue_info_old_phys_addr_hi; /*24h */ 1854 u_int32_t driver_ver_lo; /*28h */ 1855 u_int32_t driver_ver_hi; /*2Ch */ 1856 u_int32_t reserved_4[4]; /*30h */ 1857}; 1858#pragma pack() 1859 1860#pragma pack(1) 1861struct mrsas_io_frame { 1862 u_int8_t cmd; /*00h */ 1863 u_int8_t sense_len; /*01h */ 1864 u_int8_t cmd_status; /*02h */ 1865 u_int8_t scsi_status; /*03h */ 1866 1867 u_int8_t target_id; /*04h */ 1868 u_int8_t access_byte; /*05h */ 1869 u_int8_t reserved_0; /*06h */ 1870 u_int8_t sge_count; /*07h */ 1871 1872 u_int32_t context; /*08h */ 1873 u_int32_t pad_0; /*0Ch */ 1874 1875 u_int16_t flags; /*10h */ 1876 u_int16_t timeout; /*12h */ 1877 u_int32_t lba_count; /*14h */ 1878 1879 u_int32_t sense_buf_phys_addr_lo; /*18h */ 1880 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 1881 1882 u_int32_t start_lba_lo; /*20h */ 1883 u_int32_t start_lba_hi; /*24h */ 1884 1885 union mrsas_sgl sgl; /*28h */ 1886}; 1887#pragma pack() 1888 1889#pragma pack(1) 1890struct mrsas_pthru_frame { 1891 u_int8_t cmd; /*00h */ 1892 u_int8_t sense_len; /*01h */ 1893 u_int8_t cmd_status; /*02h */ 1894 u_int8_t scsi_status; /*03h */ 1895 1896 u_int8_t target_id; /*04h */ 1897 u_int8_t lun; /*05h */ 1898 u_int8_t cdb_len; /*06h */ 1899 u_int8_t sge_count; /*07h */ 1900 1901 u_int32_t context; /*08h */ 1902 u_int32_t pad_0; /*0Ch */ 1903 1904 u_int16_t flags; /*10h */ 1905 u_int16_t timeout; /*12h */ 1906 u_int32_t data_xfer_len; /*14h */ 1907 1908 u_int32_t sense_buf_phys_addr_lo; /*18h */ 1909 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 1910 1911 u_int8_t cdb[16]; /*20h */ 1912 union mrsas_sgl sgl; /*30h */ 1913}; 1914#pragma pack() 1915 1916#pragma pack(1) 1917struct mrsas_dcmd_frame { 1918 u_int8_t cmd; /*00h */ 1919 u_int8_t reserved_0; /*01h */ 1920 u_int8_t cmd_status; /*02h */ 1921 u_int8_t reserved_1[4]; /*03h */ 1922 u_int8_t sge_count; /*07h */ 1923 1924 u_int32_t context; /*08h */ 1925 u_int32_t pad_0; /*0Ch */ 1926 1927 u_int16_t flags; /*10h */ 1928 u_int16_t timeout; /*12h */ 1929 1930 u_int32_t data_xfer_len; /*14h */ 1931 u_int32_t opcode; /*18h */ 1932 1933 union { /*1Ch */ 1934 u_int8_t b[12]; 1935 u_int16_t s[6]; 1936 u_int32_t w[3]; 1937 } mbox; 1938 1939 union mrsas_sgl sgl; /*28h */ 1940}; 1941#pragma pack() 1942 1943#pragma pack(1) 1944struct mrsas_abort_frame { 1945 u_int8_t cmd; /*00h */ 1946 u_int8_t reserved_0; /*01h */ 1947 u_int8_t cmd_status; /*02h */ 1948 1949 u_int8_t reserved_1; /*03h */ 1950 u_int32_t reserved_2; /*04h */ 1951 1952 u_int32_t context; /*08h */ 1953 u_int32_t pad_0; /*0Ch */ 1954 1955 u_int16_t flags; /*10h */ 1956 u_int16_t reserved_3; /*12h */ 1957 u_int32_t reserved_4; /*14h */ 1958 1959 u_int32_t abort_context; /*18h */ 1960 u_int32_t pad_1; /*1Ch */ 1961 1962 u_int32_t abort_mfi_phys_addr_lo; /*20h */ 1963 u_int32_t abort_mfi_phys_addr_hi; /*24h */ 1964 1965 u_int32_t reserved_5[6]; /*28h */ 1966}; 1967#pragma pack() 1968 1969#pragma pack(1) 1970struct mrsas_smp_frame { 1971 u_int8_t cmd; /*00h */ 1972 u_int8_t reserved_1; /*01h */ 1973 u_int8_t cmd_status; /*02h */ 1974 u_int8_t connection_status; /*03h */ 1975 1976 u_int8_t reserved_2[3]; /*04h */ 1977 u_int8_t sge_count; /*07h */ 1978 1979 u_int32_t context; /*08h */ 1980 u_int32_t pad_0; /*0Ch */ 1981 1982 u_int16_t flags; /*10h */ 1983 u_int16_t timeout; /*12h */ 1984 1985 u_int32_t data_xfer_len; /*14h */ 1986 u_int64_t sas_addr; /*18h */ 1987 1988 union { 1989 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1990 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1991 } sgl; 1992}; 1993#pragma pack() 1994 1995 1996#pragma pack(1) 1997struct mrsas_stp_frame { 1998 u_int8_t cmd; /*00h */ 1999 u_int8_t reserved_1; /*01h */ 2000 u_int8_t cmd_status; /*02h */ 2001 u_int8_t reserved_2; /*03h */ 2002 2003 u_int8_t target_id; /*04h */ 2004 u_int8_t reserved_3[2]; /*05h */ 2005 u_int8_t sge_count; /*07h */ 2006 2007 u_int32_t context; /*08h */ 2008 u_int32_t pad_0; /*0Ch */ 2009 2010 u_int16_t flags; /*10h */ 2011 u_int16_t timeout; /*12h */ 2012 2013 u_int32_t data_xfer_len; /*14h */ 2014 2015 u_int16_t fis[10]; /*18h */ 2016 u_int32_t stp_flags; 2017 2018 union { 2019 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2020 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2021 } sgl; 2022}; 2023#pragma pack() 2024 2025union mrsas_frame { 2026 struct mrsas_header hdr; 2027 struct mrsas_init_frame init; 2028 struct mrsas_io_frame io; 2029 struct mrsas_pthru_frame pthru; 2030 struct mrsas_dcmd_frame dcmd; 2031 struct mrsas_abort_frame abort; 2032 struct mrsas_smp_frame smp; 2033 struct mrsas_stp_frame stp; 2034 u_int8_t raw_bytes[64]; 2035}; 2036 2037#pragma pack(1) 2038union mrsas_evt_class_locale { 2039 2040 struct { 2041 u_int16_t locale; 2042 u_int8_t reserved; 2043 int8_t class; 2044 } __packed members; 2045 2046 u_int32_t word; 2047 2048} __packed; 2049 2050#pragma pack() 2051 2052 2053#pragma pack(1) 2054struct mrsas_evt_log_info { 2055 u_int32_t newest_seq_num; 2056 u_int32_t oldest_seq_num; 2057 u_int32_t clear_seq_num; 2058 u_int32_t shutdown_seq_num; 2059 u_int32_t boot_seq_num; 2060 2061} __packed; 2062 2063#pragma pack() 2064 2065struct mrsas_progress { 2066 2067 u_int16_t progress; 2068 u_int16_t elapsed_seconds; 2069 2070} __packed; 2071 2072struct mrsas_evtarg_ld { 2073 2074 u_int16_t target_id; 2075 u_int8_t ld_index; 2076 u_int8_t reserved; 2077 2078} __packed; 2079 2080struct mrsas_evtarg_pd { 2081 u_int16_t device_id; 2082 u_int8_t encl_index; 2083 u_int8_t slot_number; 2084 2085} __packed; 2086 2087struct mrsas_evt_detail { 2088 2089 u_int32_t seq_num; 2090 u_int32_t time_stamp; 2091 u_int32_t code; 2092 union mrsas_evt_class_locale cl; 2093 u_int8_t arg_type; 2094 u_int8_t reserved1[15]; 2095 2096 union { 2097 struct { 2098 struct mrsas_evtarg_pd pd; 2099 u_int8_t cdb_length; 2100 u_int8_t sense_length; 2101 u_int8_t reserved[2]; 2102 u_int8_t cdb[16]; 2103 u_int8_t sense[64]; 2104 } __packed cdbSense; 2105 2106 struct mrsas_evtarg_ld ld; 2107 2108 struct { 2109 struct mrsas_evtarg_ld ld; 2110 u_int64_t count; 2111 } __packed ld_count; 2112 2113 struct { 2114 u_int64_t lba; 2115 struct mrsas_evtarg_ld ld; 2116 } __packed ld_lba; 2117 2118 struct { 2119 struct mrsas_evtarg_ld ld; 2120 u_int32_t prevOwner; 2121 u_int32_t newOwner; 2122 } __packed ld_owner; 2123 2124 struct { 2125 u_int64_t ld_lba; 2126 u_int64_t pd_lba; 2127 struct mrsas_evtarg_ld ld; 2128 struct mrsas_evtarg_pd pd; 2129 } __packed ld_lba_pd_lba; 2130 2131 struct { 2132 struct mrsas_evtarg_ld ld; 2133 struct mrsas_progress prog; 2134 } __packed ld_prog; 2135 2136 struct { 2137 struct mrsas_evtarg_ld ld; 2138 u_int32_t prev_state; 2139 u_int32_t new_state; 2140 } __packed ld_state; 2141 2142 struct { 2143 u_int64_t strip; 2144 struct mrsas_evtarg_ld ld; 2145 } __packed ld_strip; 2146 2147 struct mrsas_evtarg_pd pd; 2148 2149 struct { 2150 struct mrsas_evtarg_pd pd; 2151 u_int32_t err; 2152 } __packed pd_err; 2153 2154 struct { 2155 u_int64_t lba; 2156 struct mrsas_evtarg_pd pd; 2157 } __packed pd_lba; 2158 2159 struct { 2160 u_int64_t lba; 2161 struct mrsas_evtarg_pd pd; 2162 struct mrsas_evtarg_ld ld; 2163 } __packed pd_lba_ld; 2164 2165 struct { 2166 struct mrsas_evtarg_pd pd; 2167 struct mrsas_progress prog; 2168 } __packed pd_prog; 2169 2170 struct { 2171 struct mrsas_evtarg_pd pd; 2172 u_int32_t prevState; 2173 u_int32_t newState; 2174 } __packed pd_state; 2175 2176 struct { 2177 u_int16_t vendorId; 2178 u_int16_t deviceId; 2179 u_int16_t subVendorId; 2180 u_int16_t subDeviceId; 2181 } __packed pci; 2182 2183 u_int32_t rate; 2184 char str[96]; 2185 2186 struct { 2187 u_int32_t rtc; 2188 u_int32_t elapsedSeconds; 2189 } __packed time; 2190 2191 struct { 2192 u_int32_t ecar; 2193 u_int32_t elog; 2194 char str[64]; 2195 } __packed ecc; 2196 2197 u_int8_t b[96]; 2198 u_int16_t s[48]; 2199 u_int32_t w[24]; 2200 u_int64_t d[12]; 2201 } args; 2202 2203 char description[128]; 2204 2205} __packed; 2206 2207struct megaraid_ctrl { 2208 megaraid_t d; 2209 2210#ifndef BARRELFISH 2211 int uiofd, configfd; 2212#endif 2213 2214 uint16_t device_id; // pci device 2215 void *verbuf_mem; // verbuf mem 2216 lpaddr_t verbuf_phys_addr; // verbuf physical addr 2217 void *sense_mem; // pointer to sense buf 2218 lpaddr_t sense_phys_addr; // bus dma verbuf mem 2219 void *io_request_mem; // bus dma io request mem 2220 lpaddr_t io_request_phys_addr; // io request physical address 2221 void *chain_frame_mem; // bus dma chain frame mem 2222 lpaddr_t chain_frame_phys_addr; // chain frame phys address 2223 void *reply_desc_mem; // bus dma io request mem 2224 lpaddr_t reply_desc_phys_addr; // bus dma io request mem 2225 void *ioc_init_mem; // bus dma io request mem 2226 lpaddr_t ioc_init_phys_mem; // io request physical address 2227 /* struct cam_sim *sim_0; // SIM pointer */ 2228 /* struct cam_sim *sim_1; // SIM pointer */ 2229 /* struct cam_path *path_0; // ldio path pointer to CAM */ 2230 /* struct cam_path *path_1; // syspd path pointer to CAM */ 2231 /* struct mtx sim_lock; // sim lock */ 2232 /* struct mtx pci_lock; // serialize pci access */ 2233 /* struct mtx io_lock; // IO lock */ 2234 /* struct mtx ioctl_lock; // IOCTL lock */ 2235 /* struct mtx mpt_cmd_pool_lock; // lock for cmd pool linked list */ 2236 /* struct mtx mfi_cmd_pool_lock; // lock for cmd pool linked list */ 2237 /* struct mtx raidmap_lock; // lock for raid map access/update */ 2238 /* struct mtx aen_lock; // aen lock */ 2239 uint32_t max_fw_cmds; // Max commands from FW 2240 uint32_t max_num_sge; // Max number of SGEs 2241 /* struct resource *mrsas_irq; // interrupt interface window */ 2242 void *intr_handle; // handle 2243 int irq_id; // intr resource id 2244 struct mrsas_mpt_cmd **mpt_cmd_list; 2245 struct mrsas_mfi_cmd **mfi_cmd_list; 2246 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 2247 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 2248 lpaddr_t req_frames_desc_phys; 2249 u_int8_t *req_frames_desc; 2250 u_int8_t *req_desc; 2251 lpaddr_t io_request_frames_phys; 2252 u_int8_t *io_request_frames; 2253 lpaddr_t reply_frames_desc_phys; 2254 u_int16_t last_reply_idx; 2255 u_int32_t reply_q_depth; 2256 u_int32_t request_alloc_sz; 2257 u_int32_t reply_alloc_sz; 2258 u_int32_t io_frames_alloc_sz; 2259 u_int32_t chain_frames_alloc_sz; 2260 u_int16_t max_sge_in_main_msg; 2261 u_int16_t max_sge_in_chain; 2262 u_int8_t chain_offset_io_request; 2263 u_int8_t chain_offset_mfi_pthru; 2264 u_int32_t map_sz; 2265 u_int64_t map_id; 2266 struct mrsas_mfi_cmd *map_update_cmd; 2267 struct mrsas_mfi_cmd *aen_cmd; 2268 u_int8_t fast_path_io; 2269 void* chan; 2270 void* ocr_chan; 2271 u_int8_t adprecovery; 2272 u_int8_t remove_in_progress; 2273 u_int8_t ocr_thread_active; 2274 u_int8_t do_timedout_reset; 2275 u_int32_t reset_in_progress; 2276 u_int32_t reset_count; 2277 void *raidmap_mem[2]; // bus dma mem RAID map 2278 lpaddr_t raidmap_phys_addr[2]; // RAID map physical address 2279 struct mrsas_evt_detail *evt_detail_mem; // event detail mem 2280 lpaddr_t evt_detail_phys_addr; // event detail physical addr 2281 void *ctlr_info_mem; // get ctlr info cmd virtual addr 2282 lpaddr_t ctlr_info_phys_addr; //get ctlr info cmd physical addr 2283 u_int32_t max_sectors_per_req; 2284 u_int8_t disableOnlineCtrlReset; 2285 atomic_t fw_outstanding; 2286 u_int32_t mrsas_debug; 2287 u_int32_t mrsas_io_timeout; 2288 u_int32_t mrsas_fw_fault_check_delay; 2289 u_int32_t io_cmds_highwater; 2290 u_int8_t UnevenSpanSupport; 2291 /* struct sysctl_ctx_list sysctl_ctx; */ 2292 /* struct sysctl_oid *sysctl_tree; */ 2293 /* struct proc *ocr_thread; */ 2294 u_int32_t last_seq_num; 2295 void *el_info_mem; // get event log info cmd virtual addr 2296 lpaddr_t el_info_phys_addr; //get event log info cmd physical addr 2297 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 2298 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 2299 u_int8_t ld_ids[MRSAS_MAX_LD]; 2300 /* struct taskqueue *ev_tq; //taskqueue for events */ 2301 /* struct task ev_task; */ 2302 u_int32_t CurLdCount; 2303 u_int64_t reset_flags; 2304 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 2305 /* LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES]; */ 2306 2307 /* uint32_t max_num_sge; // Max number of SGEs */ 2308 /* uint32_t reply_q_depth; */ 2309 /* uint32_t request_alloc_sz; */ 2310 /* uint32_t reply_alloc_sz; */ 2311 /* uint32_t io_frames_alloc_sz; */ 2312 /* uint32_t chain_frames_alloc_sz; */ 2313 /* uint16_t max_sge_in_main_msg; */ 2314 /* uint16_t max_sge_in_chain; */ 2315 /* uint8_t chain_offset_io_request; */ 2316 /* uint8_t chain_offset_mfi_pthru; */ 2317 2318 /* uint8_t *req_desc; */ 2319}; 2320 2321uintptr_t v2p(void *ptr, size_t len); 2322 2323#define TARGET_DEVICE_ID 1 2324#define BLOCK_SIZE 512 2325 2326#ifdef MEGARAID_DEBUG 2327# define DEBUG(x...) printf("megaraid: " x) 2328#else 2329# define DEBUG(x...) do {} while (0) 2330#endif 2331 2332struct mrsas_mpt_cmd* mrsas_get_mpt_cmd(void); 2333MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_get_request_desc(u_int16_t idx); 2334void mrsas_fire_cmd(u_int32_t req_desc_lo, u_int32_t req_desc_hi); 2335int megaraid_driver_init(int argc, const char **argv); 2336int mrsas_complete_cmd(void); 2337 2338extern struct megaraid_ctrl *sc; 2339extern bool poll_mode; 2340 2341#endif 2342