1/* 2 * Copyright (c) 2014 ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10#ifndef IOAT_DEVICE_H_ 11#define IOAT_DEVICE_H_ 12 13#include <dma/dma_device.h> 14#include <pci/pci_types.h> 15 16enum device_type { 17 IOAT_DEVICE_INVAL, 18 IOAT_DEVICE_IVB, 19 IOAT_DEVICE_HSW 20}; 21 22/* CB device ID's */ 23#define IOAT_PCI_D5000 0x1A38 24#define IOAT_PCI_DCNB 0x360B 25#define IOAT_PCI_DSCNB 0x65FF 26#define IOAT_PCI_DSNB 0x402F 27 28 29/* 30 * Intel I/O AT Device IDs for Ivy Bridge 31 */ 32#define PCI_DEVICE_IOAT_IVB0 0x0e20 33#define PCI_DEVICE_IOAT_IVB1 0x0e21 34#define PCI_DEVICE_IOAT_IVB2 0x0e22 35#define PCI_DEVICE_IOAT_IVB3 0x0e23 36#define PCI_DEVICE_IOAT_IVB4 0x0e24 37#define PCI_DEVICE_IOAT_IVB5 0x0e25 38#define PCI_DEVICE_IOAT_IVB6 0x0e26 39#define PCI_DEVICE_IOAT_IVB7 0x0e27 40#define PCI_DEVICE_IOAT_IVB8 0x0e2e 41#define PCI_DEVICE_IOAT_IVB9 0x0e2f 42#define PCI_DEVICE_IOAT_IVB_CNT 10 43/* 44 * Intel I/O AT Device IDs for Haswell 45 */ 46#define PCI_DEVICE_IOAT_HSW0 0x2f20 47#define PCI_DEVICE_IOAT_HSW1 0x2f21 48#define PCI_DEVICE_IOAT_HSW2 0x2f22 49#define PCI_DEVICE_IOAT_HSW3 0x2f23 50#define PCI_DEVICE_IOAT_HSW4 0x2f24 51#define PCI_DEVICE_IOAT_HSW5 0x2f25 52#define PCI_DEVICE_IOAT_HSW6 0x2f26 53#define PCI_DEVICE_IOAT_HSW7 0x2f27 54#define PCI_DEVICE_IOAT_HSW8 0x2f2e 55#define PCI_DEVICE_IOAT_HSW9 0x2f2f 56#define PCI_DEVICE_IOAT_HSW_CNT 10 57 58 59 60#define IOAT_DMA_CHAN_COUNT 8 61 62#define IOAT_DMA_BAR_COUNT 1 63 64errval_t ioat_device_discovery(struct pci_addr addr, 65 enum device_type devtype, 66 uint8_t is_dev_mgr); 67 68struct ioat_dma_device *ioat_device_get_next(void); 69 70errval_t ioat_device_poll(void); 71 72 73#endif /* IOAT_DEVICE_H_ */ 74