1 2#include <aboot/aboot.h> 3#include <aboot/io.h> 4#include <omap4/mux.h> 5#include <omap4/hw.h> 6 7#define PANDA_BOARD_ID_2_GPIO 171 8 9void board_late_init(void) 10{ 11} 12 13void board_mux_init(void) 14{ 15 MV(CP(GPMC_AD0) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat0 */ 16 MV(CP(GPMC_AD1) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat1 */ 17 MV(CP(GPMC_AD2) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat2 */ 18 MV(CP(GPMC_AD3) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat3 */ 19 MV(CP(GPMC_AD4) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat4 */ 20 MV(CP(GPMC_AD5) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat5 */ 21 MV(CP(GPMC_AD6) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat6 */ 22 MV(CP(GPMC_AD7) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat7 */ 23 MV(CP(GPMC_AD8) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)); /* gpio_32 */ 24 MV(CP(GPMC_AD9) , (PTU | IEN | M3)); /* gpio_33 */ 25 MV(CP(GPMC_AD10) , (PTU | IEN | M3)); /* gpio_34 */ 26 MV(CP(GPMC_AD11) , (PTU | IEN | M3)); /* gpio_35 */ 27 MV(CP(GPMC_AD12) , (PTU | IEN | M3)); /* gpio_36 */ 28 MV(CP(GPMC_AD13) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_37 */ 29 MV(CP(GPMC_AD14) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_38 */ 30 MV(CP(GPMC_AD15) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_39 */ 31 MV(CP(GPMC_A16) , (M3)); /* gpio_40 */ 32 MV(CP(GPMC_A17) , (PTD | M3)); /* gpio_41 */ 33 MV(CP(GPMC_A18) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row6 */ 34 MV(CP(GPMC_A19) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row7 */ 35 MV(CP(GPMC_A20) , (IEN | M3)); /* gpio_44 */ 36 MV(CP(GPMC_A21) , (M3)); /* gpio_45 */ 37 MV(CP(GPMC_A22) , (M3)); /* gpio_46 */ 38 MV(CP(GPMC_A23) , (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col7 */ 39 MV(CP(GPMC_A24) , (PTD | M3)); /* gpio_48 */ 40 MV(CP(GPMC_A25) , (PTD | M3)); /* gpio_49 */ 41 MV(CP(GPMC_NCS0) , (M3)); /* gpio_50 */ 42 MV(CP(GPMC_NCS1) , (IEN | M3)); /* gpio_51 */ 43 MV(CP(GPMC_NCS2) , (IEN | M3)); /* gpio_52 */ 44 MV(CP(GPMC_NCS3) , (IEN | M3)); /* gpio_53 */ 45 MV(CP(GPMC_NWP) , (M3)); /* gpio_54 */ 46 MV(CP(GPMC_CLK) , (PTD | M3)); /* gpio_55 */ 47 MV(CP(GPMC_NADV_ALE) , (M3)); /* gpio_56 */ 48 MV(CP(GPMC_NOE) , (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)); /* sdmmc2_clk */ 49 MV(CP(GPMC_NWE) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_cmd */ 50 MV(CP(GPMC_NBE0_CLE) , (M3)); /* gpio_59 */ 51 MV(CP(GPMC_NBE1) , (PTD | M3)); /* gpio_60 */ 52 MV(CP(GPMC_WAIT0) , (PTU | IEN | M3)); /* gpio_61 */ 53 MV(CP(GPMC_WAIT1) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_62 */ 54 MV(CP(C2C_DATA11) , (PTD | M3)); /* gpio_100 */ 55 MV(CP(C2C_DATA12) , (PTU | IEN | M3)); /* gpio_101 */ 56 MV(CP(C2C_DATA13) , (PTD | M3)); /* gpio_102 */ 57 MV(CP(C2C_DATA14) , ( M1)); /* dsi2_te0 */ 58 MV(CP(C2C_DATA15) , (PTD | M3)); /* gpio_104 */ 59 MV(CP(HDMI_HPD) , (M0)); /* hdmi_hpd */ 60 MV(CP(HDMI_CEC) , (M0)); /* hdmi_cec */ 61 MV(CP(HDMI_DDC_SCL) , (PTU | M0)); /* hdmi_ddc_scl */ 62 MV(CP(HDMI_DDC_SDA) , (PTU | IEN | M0)); /* hdmi_ddc_sda */ 63 MV(CP(CSI21_DX0) , (IEN | M0)); /* csi21_dx0 */ 64 MV(CP(CSI21_DY0) , (IEN | M0)); /* csi21_dy0 */ 65 MV(CP(CSI21_DX1) , (IEN | M0)); /* csi21_dx1 */ 66 MV(CP(CSI21_DY1) , (IEN | M0)); /* csi21_dy1 */ 67 MV(CP(CSI21_DX2) , (IEN | M0)); /* csi21_dx2 */ 68 MV(CP(CSI21_DY2) , (IEN | M0)); /* csi21_dy2 */ 69 MV(CP(CSI21_DX3) , (PTD | M7)); /* csi21_dx3 */ 70 MV(CP(CSI21_DY3) , (PTD | M7)); /* csi21_dy3 */ 71 MV(CP(CSI21_DX4) , (PTD | OFF_EN | OFF_PD | OFF_IN | M7)); /* csi21_dx4 */ 72 MV(CP(CSI21_DY4) , (PTD | OFF_EN | OFF_PD | OFF_IN | M7)); /* csi21_dy4 */ 73 MV(CP(CSI22_DX0) , (IEN | M0)); /* csi22_dx0 */ 74 MV(CP(CSI22_DY0) , (IEN | M0)); /* csi22_dy0 */ 75 MV(CP(CSI22_DX1) , (IEN | M0)); /* csi22_dx1 */ 76 MV(CP(CSI22_DY1) , (IEN | M0)); /* csi22_dy1 */ 77 MV(CP(CAM_SHUTTER) , (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* cam_shutter */ 78 MV(CP(CAM_STROBE) , (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* cam_strobe */ 79 MV(CP(CAM_GLOBALRESET) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_83 */ 80 MV(CP(USBB1_ULPITLL_CLK) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_clk */ 81 MV(CP(USBB1_ULPITLL_STP) , (OFF_EN | OFF_OUT_PTD | M4)); /* usbb1_ulpiphy_stp */ 82 MV(CP(USBB1_ULPITLL_DIR) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dir */ 83 MV(CP(USBB1_ULPITLL_NXT) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_nxt */ 84 MV(CP(USBB1_ULPITLL_DAT0) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat0 */ 85 MV(CP(USBB1_ULPITLL_DAT1) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat1 */ 86 MV(CP(USBB1_ULPITLL_DAT2) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat2 */ 87 MV(CP(USBB1_ULPITLL_DAT3) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat3 */ 88 MV(CP(USBB1_ULPITLL_DAT4) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat4 */ 89 MV(CP(USBB1_ULPITLL_DAT5) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat5 */ 90 MV(CP(USBB1_ULPITLL_DAT6) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat6 */ 91 MV(CP(USBB1_ULPITLL_DAT7) , (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat7 */ 92 MV(CP(USBB1_HSIC_DATA) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usbb1_hsic_data */ 93 MV(CP(USBB1_HSIC_STROBE) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usbb1_hsic_strobe */ 94 MV(CP(USBC1_ICUSB_DP) , (IEN | M0)); /* usbc1_icusb_dp */ 95 MV(CP(USBC1_ICUSB_DM) , (IEN | M0)); /* usbc1_icusb_dm */ 96 MV(CP(SDMMC1_CLK) , (PTU | OFF_EN | OFF_OUT_PTD | M0)); /* sdmmc1_clk */ 97 MV(CP(SDMMC1_CMD) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_cmd */ 98 MV(CP(SDMMC1_DAT0) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat0 */ 99 MV(CP(SDMMC1_DAT1) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat1 */ 100 MV(CP(SDMMC1_DAT2) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat2 */ 101 MV(CP(SDMMC1_DAT3) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat3 */ 102 MV(CP(SDMMC1_DAT4) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat4 */ 103 MV(CP(SDMMC1_DAT5) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat5 */ 104 MV(CP(SDMMC1_DAT6) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat6 */ 105 MV(CP(SDMMC1_DAT7) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat7 */ 106 MV(CP(ABE_MCBSP2_CLKX) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp2_clkx */ 107 MV(CP(ABE_MCBSP2_DR) , (IEN | OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp2_dr */ 108 MV(CP(ABE_MCBSP2_DX) , (OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp2_dx */ 109 MV(CP(ABE_MCBSP2_FSX) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp2_fsx */ 110 MV(CP(ABE_MCBSP1_CLKX) , (IEN | M1)); /* abe_slimbus1_clock */ 111 MV(CP(ABE_MCBSP1_DR) , (IEN | M1)); /* abe_slimbus1_data */ 112 MV(CP(ABE_MCBSP1_DX) , (OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp1_dx */ 113 MV(CP(ABE_MCBSP1_FSX) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp1_fsx */ 114 MV(CP(ABE_PDM_UL_DATA) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_ul_data */ 115 MV(CP(ABE_PDM_DL_DATA) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_dl_data */ 116 MV(CP(ABE_PDM_FRAME) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_frame */ 117 MV(CP(ABE_PDM_LB_CLK) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_lb_clk */ 118 MV(CP(ABE_CLKS) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_clks */ 119 MV(CP(ABE_DMIC_CLK1) , (M0)); /* abe_dmic_clk1 */ 120 MV(CP(ABE_DMIC_DIN1) , (IEN | M0)); /* abe_dmic_din1 */ 121 MV(CP(ABE_DMIC_DIN2), (PTU | IEN | M3)); 122 MV(CP(ABE_DMIC_DIN3) , (IEN | M0)); /* abe_dmic_din3 */ 123 MV(CP(UART2_CTS) , (PTU | IEN | M0)); /* uart2_cts */ 124 MV(CP(UART2_RTS) , (M0)); /* uart2_rts */ 125 MV(CP(UART2_RX) , (PTU | IEN | M0)); /* uart2_rx */ 126 MV(CP(UART2_TX) , (M0)); /* uart2_tx */ 127 MV(CP(HDQ_SIO) , (M3)); /* gpio_127 */ 128 MV(CP(I2C1_SCL) , (PTU | IEN | M0)); /* i2c1_scl */ 129 MV(CP(I2C1_SDA) , (PTU | IEN | M0)); /* i2c1_sda */ 130 MV(CP(I2C2_SCL) , (PTU | IEN | M0)); /* i2c2_scl */ 131 MV(CP(I2C2_SDA) , (PTU | IEN | M0)); /* i2c2_sda */ 132 MV(CP(I2C3_SCL) , (PTU | IEN | M0)); /* i2c3_scl */ 133 MV(CP(I2C3_SDA) , (PTU | IEN | M0)); /* i2c3_sda */ 134 MV(CP(I2C4_SCL) , (PTU | IEN | M0)); /* i2c4_scl */ 135 MV(CP(I2C4_SDA) , (PTU | IEN | M0)); /* i2c4_sda */ 136 MV(CP(MCSPI1_CLK) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_clk */ 137 MV(CP(MCSPI1_SOMI) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_somi */ 138 MV(CP(MCSPI1_SIMO) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_simo */ 139 MV(CP(MCSPI1_CS0) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_cs0 */ 140 MV(CP(MCSPI1_CS1) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)); /* mcspi1_cs1 */ 141 MV(CP(MCSPI1_CS2) , (PTU | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_139 */ 142 MV(CP(MCSPI1_CS3) , (PTU | IEN | M3)); /* gpio_140 */ 143 MV(CP(UART3_CTS_RCTX) , (PTU | IEN | M0)); /* uart3_tx */ 144 MV(CP(UART3_RTS_SD) , (M0)); /* uart3_rts_sd */ 145 MV(CP(UART3_RX_IRRX) , (IEN | M0)); /* uart3_rx */ 146 MV(CP(UART3_TX_IRTX) , (M0)); /* uart3_tx */ 147 MV(CP(SDMMC5_CLK) , (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)); /* sdmmc5_clk */ 148 MV(CP(SDMMC5_CMD) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_cmd */ 149 MV(CP(SDMMC5_DAT0) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat0 */ 150 MV(CP(SDMMC5_DAT1) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat1 */ 151 MV(CP(SDMMC5_DAT2) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat2 */ 152 MV(CP(SDMMC5_DAT3) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat3 */ 153 MV(CP(MCSPI4_CLK) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_clk */ 154 MV(CP(MCSPI4_SIMO) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_simo */ 155 MV(CP(MCSPI4_SOMI) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_somi */ 156 MV(CP(MCSPI4_CS0) , (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_cs0 */ 157 MV(CP(UART4_RX) , (IEN | M0)); /* uart4_rx */ 158 MV(CP(UART4_TX) , (M0)); /* uart4_tx */ 159 MV(CP(USBB2_ULPITLL_CLK) , (IEN | M3)); /* gpio_157 */ 160 MV(CP(USBB2_ULPITLL_STP) , (IEN | M5)); /* dispc2_data23 */ 161 MV(CP(USBB2_ULPITLL_DIR) , (IEN | M5)); /* dispc2_data22 */ 162 MV(CP(USBB2_ULPITLL_NXT) , (IEN | M5)); /* dispc2_data21 */ 163 MV(CP(USBB2_ULPITLL_DAT0) , (IEN | M5)); /* dispc2_data20 */ 164 MV(CP(USBB2_ULPITLL_DAT1) , (IEN | M5)); /* dispc2_data19 */ 165 MV(CP(USBB2_ULPITLL_DAT2) , (IEN | M5)); /* dispc2_data18 */ 166 MV(CP(USBB2_ULPITLL_DAT3) , (IEN | M5)); /* dispc2_data15 */ 167 MV(CP(USBB2_ULPITLL_DAT4) , (IEN | M5)); /* dispc2_data14 */ 168 MV(CP(USBB2_ULPITLL_DAT5) , (IEN | M5)); /* dispc2_data13 */ 169 MV(CP(USBB2_ULPITLL_DAT6) , (IEN | M5)); /* dispc2_data12 */ 170 MV(CP(USBB2_ULPITLL_DAT7) , (IEN | M5)); /* dispc2_data11 */ 171 MV(CP(USBB2_HSIC_DATA) , (PTD | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_169 */ 172 MV(CP(USBB2_HSIC_STROBE) , (PTD | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_170 */ 173 MV(CP(UNIPRO_TX0) , (PTD | IEN | M3)); /* gpio_171 */ 174 MV(CP(UNIPRO_TY0) , (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col1 */ 175 MV(CP(UNIPRO_TX1) , (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col2 */ 176 MV(CP(UNIPRO_TY1) , (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col3 */ 177 MV(CP(UNIPRO_TX2) , (PTU | IEN | M3)); /* gpio_0 */ 178 MV(CP(UNIPRO_TY2) , (PTU | IEN | M3)); /* gpio_1 */ 179 MV(CP(UNIPRO_RX0) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row0 */ 180 MV(CP(UNIPRO_RY0) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row1 */ 181 MV(CP(UNIPRO_RX1) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row2 */ 182 MV(CP(UNIPRO_RY1) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row3 */ 183 MV(CP(UNIPRO_RX2) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row4 */ 184 MV(CP(UNIPRO_RY2) , (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row5 */ 185 MV(CP(USBA0_OTG_CE) , (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* usba0_otg_ce */ 186 MV(CP(USBA0_OTG_DP) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usba0_otg_dp */ 187 MV(CP(USBA0_OTG_DM) , (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usba0_otg_dm */ 188 MV(CP(FREF_CLK1_OUT) , (M0)); /* fref_clk1_out */ 189 MV(CP(FREF_CLK2_OUT) , (PTU | IEN | M3)); /* gpio_182 */ 190 MV(CP(SYS_NIRQ1) , (PTU | IEN | M0)); /* sys_nirq1 */ 191 MV(CP(SYS_NIRQ2) , (PTU | IEN | M0)); /* sys_nirq2 */ 192 MV(CP(SYS_BOOT0) , (PTU | IEN | M3)); /* gpio_184 */ 193 MV(CP(SYS_BOOT1) , (M3)); /* gpio_185 */ 194 MV(CP(SYS_BOOT2) , (PTD | IEN | M3)); /* gpio_186 */ 195 MV(CP(SYS_BOOT3) , (M3)); /* gpio_187 */ 196 MV(CP(SYS_BOOT4) , (M3)); /* gpio_188 */ 197 MV(CP(SYS_BOOT5) , (PTD | IEN | M3)); /* gpio_189 */ 198 MV(CP(DPM_EMU0) , (IEN | M0)); /* dpm_emu0 */ 199 MV(CP(DPM_EMU1) , (IEN | M0)); /* dpm_emu1 */ 200 MV(CP(DPM_EMU2) , (IEN | M0)); /* dpm_emu2 */ 201 MV(CP(DPM_EMU3) , (IEN | M5)); /* dispc2_data10 */ 202 MV(CP(DPM_EMU4) , (IEN | M5)); /* dispc2_data9 */ 203 MV(CP(DPM_EMU5) , (IEN | M5)); /* dispc2_data16 */ 204 MV(CP(DPM_EMU6) , (IEN | M5)); /* dispc2_data17 */ 205 MV(CP(DPM_EMU7) , (IEN | M5)); /* dispc2_hsync */ 206 MV(CP(DPM_EMU8) , (IEN | M5)); /* dispc2_pclk */ 207 MV(CP(DPM_EMU9) , (IEN | M5)); /* dispc2_vsync */ 208 MV(CP(DPM_EMU10) , (IEN | M5)); /* dispc2_de */ 209 MV(CP(DPM_EMU11) , (IEN | M5)); /* dispc2_data8 */ 210 MV(CP(DPM_EMU12) , (IEN | M5)); /* dispc2_data7 */ 211 MV(CP(DPM_EMU13) , (IEN | M5)); /* dispc2_data6 */ 212 MV(CP(DPM_EMU14) , (IEN | M5)); /* dispc2_data5 */ 213 MV(CP(DPM_EMU15) , (IEN | M5)); /* dispc2_data4 */ 214 MV(CP(DPM_EMU16) , (M3)); /* gpio_27 */ 215 MV(CP(DPM_EMU17) , (IEN | M5)); /* dispc2_data2 */ 216 MV(CP(DPM_EMU18) , (IEN | M5)); /* dispc2_data1 */ 217 MV(CP(DPM_EMU19) , (IEN | M5)); /* dispc2_data0 */ 218 MV1(WK(PAD0_SIM_IO) , (IEN | M0)); /* sim_io */ 219 MV1(WK(PAD1_SIM_CLK) , (M0)); /* sim_clk */ 220 MV1(WK(PAD0_SIM_RESET) , (M0)); /* sim_reset */ 221 MV1(WK(PAD1_SIM_CD) , (PTU | IEN | M0)); /* sim_cd */ 222 MV1(WK(PAD0_SIM_PWRCTRL) , (M0)); /* sim_pwrctrl */ 223 MV1(WK(PAD1_SR_SCL) , (PTU | IEN | M0)); /* sr_scl */ 224 MV1(WK(PAD0_SR_SDA) , (PTU | IEN | M0)); /* sr_sda */ 225 MV1(WK(PAD1_FREF_XTAL_IN) , (M0)); /* # */ 226 MV1(WK(PAD0_FREF_SLICER_IN) , (M0)); /* fref_slicer_in */ 227 MV1(WK(PAD1_FREF_CLK_IOREQ) , (M0)); /* fref_clk_ioreq */ 228 MV1(WK(PAD0_FREF_CLK0_OUT) , (M2)); /* sys_drm_msecure */ 229 MV1(WK(PAD1_FREF_CLK3_REQ) , (M3)); /* gpio_wk30 */ 230 MV1(WK(PAD0_FREF_CLK3_OUT) , (M0)); /* fref_clk3_out */ 231 MV1(WK(PAD1_FREF_CLK4_REQ) , (PTU | IEN | M0)); /* # */ 232 MV1(WK(PAD0_FREF_CLK4_OUT) , (M0)); /* # */ 233 MV1(WK(PAD1_SYS_32K) , (IEN | M0)); /* sys_32k */ 234 MV1(WK(PAD0_SYS_NRESPWRON) , (M0)); /* sys_nrespwron */ 235 MV1(WK(PAD1_SYS_NRESWARM) , (M0)); /* sys_nreswarm */ 236 MV1(WK(PAD0_SYS_PWR_REQ) , (PTU | M0)); /* sys_pwr_req */ 237 MV1(WK(PAD1_SYS_PWRON_RESET) , (M3)); /* gpio_wk29 */ 238 MV1(WK(PAD0_SYS_BOOT6) , (IEN | M3)); /* gpio_wk9 */ 239 MV1(WK(PAD1_SYS_BOOT7) , (IEN | M3)); /* gpio_wk10 */ 240 MV1(WK(PAD1_FREF_CLK3_REQ), (M3)); /* gpio_wk30 */ 241 MV1(WK(PAD1_FREF_CLK4_REQ), (M3)); /* gpio_wk7 */ 242 MV1(WK(PAD0_FREF_CLK4_OUT), (M3)); /* gpio_wk8 */ 243} 244 245 246static struct ddr_regs elpida2G_400mhz_2cs = { 247 /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ 248 .tim1 = 0x10eb0662, 249 .tim2 = 0x20370dd2, 250 .tim3 = 0x00b1c33f, 251 .phy_ctrl_1 = 0x849FF408, 252 .ref_ctrl = 0x00000618, 253 .config_init = 0x80000eb9, 254 .config_final = 0x80001ab9, 255 .zq_config = 0xD00b3215, 256 .mr1 = 0x83, 257 .mr2 = 0x4 258}; 259 260static struct ddr_regs elpida2G_400mhz_1cs = { 261 /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ 262 .tim1 = 0x10eb0662, 263 .tim2 = 0x20370dd2, 264 .tim3 = 0x00b1c33f, 265 .phy_ctrl_1 = 0x849FF408, 266 // .phy_ctrl_1 = 0x049FF418, // U-Boot version 267 .ref_ctrl = 0x00000618, 268 .config_init = 0x80800eb2, 269 .config_final = 0x80801ab2, 270 .zq_config = 0x500b3215, 271 .mr1 = 0x83, 272 // .mr1 = 0x23, // U-Boot version 273 .mr2 = 0x4 274}; 275 276static int is_panda_es_rev_b3(void) 277{ 278 // Is rev B3? 279 MV(CP(UNIPRO_TX0), (PTD | IEN | M3)); /* gpio_171 */ 280 281 /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ 282 return gpio_read(PANDA_BOARD_ID_2_GPIO); 283} 284 285void board_ddr_init(void) 286{ 287 struct ddr_regs *myregs = &elpida2G_400mhz_2cs; 288 289 /* 1GB, 128B interleaved */ 290 writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0); 291 writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2); 292 writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3); 293 294 if (get_omap_rev() >= OMAP_4460_ES1_DOT_0) { 295 writel(0x80640300, MA_BASE + DMM_LISA_MAP_0); 296 elpida2G_400mhz_2cs.phy_ctrl_1 = 0x449FF408; 297 298 if(is_panda_es_rev_b3()) { 299 myregs = &elpida2G_400mhz_1cs; 300 } 301 } 302 303 omap4_ddr_init(myregs, myregs); 304 305} 306