1/* 2 * sdram.c 3 * 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. 5 * 6 * Texas Instruments, <www.ti.com> 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Aneesh V <aneesh@ti.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * * Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * * Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * * Neither the name Texas Instruments nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <aboot/aboot.h> 39#include <aboot/io.h> 40#include <omap4/hw.h> 41 42#define CONFIG_OMAP4_SDC 1 43 44#define MR0_ADDR 0 45#define MR1_ADDR 1 46#define MR2_ADDR 2 47#define MR4_ADDR 4 48#define MR10_ADDR 10 49#define MR16_ADDR 16 50#define REF_EN 0x40000000 51 52/* defines for MR1 */ 53#define MR1_BL4 2 54#define MR1_BL8 3 55#define MR1_BL16 4 56 57#define MR1_BT_SEQ 0 58#define BT_INT 1 59 60#define MR1_WC 0 61#define MR1_NWC 1 62 63#define MR1_NWR3 1 64#define MR1_NWR4 2 65#define MR1_NWR5 3 66#define MR1_NWR6 4 67#define MR1_NWR7 5 68#define MR1_NWR8 6 69 70#define MR1_VALUE (MR1_NWR3<<5) | (MR1_WC<<4) | (MR1_BT_SEQ<<3) | (MR1_BL8<<0) 71 72/* defines for MR2 */ 73#define MR2_RL3_WL1 1 74#define MR2_RL4_WL2 2 75#define MR2_RL5_WL2 3 76#define MR2_RL6_WL3 4 77 78/* defines for MR10 */ 79#define MR10_ZQINIT 0xFF 80#define MR10_ZQRESET 0xC3 81#define MR10_ZQCL 0xAB 82#define MR10_ZQCS 0x56 83 84 85/* TODO: FREQ update method is not working so shadow registers programming 86 * is just for same of completeness. This would be safer if auto 87 * trasnitions are working 88 */ 89#define FREQ_UPDATE_EMIF 90 91/* EMIF Needs to be configured@19.2 MHz and shadow registers 92 * should be programmed for new OPP. 93 */ 94 95/* Elpida 2x2Gbit */ 96#define SDRAM_CONFIG_INIT 0x80800EB1 97#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 98#define READ_IDLE_CTRL 0x000501FF 99#define PWR_MGMT_CTRL 0x4000000f 100#define PWR_MGMT_CTRL_OPP100 0x4000000f 101#define ZQ_CONFIG 0x500b3215 102 103#define CS1_MR(mr) ((mr) | 0x80000000) 104 105void reset_phy(unsigned int base) 106{ 107 writel(readl(base + IODFT_TLGC) | (1 << 10), 108 base + IODFT_TLGC); 109} 110 111/* TODO: FREQ update method is not working so shadow registers programming 112 * is just for same of completeness. This would be safer if auto 113 * trasnitions are working 114 */ 115static void emif_config(unsigned int base, const struct ddr_regs *ddr_regs) 116{ 117 unsigned int reg_value; 118 119 /* 120 * set SDRAM CONFIG register 121 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4 122 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0 123 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3 124 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks 125 * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0 126 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column 127 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8 128 */ 129 writel(readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xBFFFFFFF, 130 base + EMIF_LPDDR2_NVM_CONFIG); 131 writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG); 132 133 /* PHY control values */ 134 writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1); 135 writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW); 136 137 /* 138 * EMIF_READ_IDLE_CTRL 139 */ 140 writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL); 141 writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL_SHDW); 142 143 /* 144 * EMIF_SDRAM_TIM_1 145 */ 146 writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1); 147 writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW); 148 149 /* 150 * EMIF_SDRAM_TIM_2 151 */ 152 writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2); 153 writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW); 154 155 /* 156 * EMIF_SDRAM_TIM_3 157 */ 158 writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3); 159 writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW); 160 161 writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG); 162 /* 163 * EMIF_PWR_MGMT_CTRL 164 */ 165 /* 166 * poll MR0 register (DAI bit) 167 * REG_CS[31] = 0 -- Mode register command to CS0 168 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW 169 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW 170 */ 171 172 writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); 173 do { 174 reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA); 175 } while ((reg_value & 0x1) != 0); 176 177 writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); 178 do { 179 reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA); 180 } while ((reg_value & 0x1) != 0); 181 182 183 /* set MR10 register */ 184 writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); 185 writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA); 186 writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); 187 writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA); 188 189 /* wait for tZQINIT=1us */ 190 sdelay(10); 191 192 /* set MR1 register */ 193 writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); 194 writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA); 195 writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); 196 writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA); 197 198 199 /* set MR2 register RL=6 for OPP100 */ 200 writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); 201 writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA); 202 writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); 203 writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA); 204 205 /* Set SDRAM CONFIG register again here with final RL-WL value */ 206 writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG); 207 writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1); 208 209 /* 210 * EMIF_SDRAM_REF_CTRL 211 * refresh rate = DDR_CLK / reg_refresh_rate 212 * 3.9 uS = (400MHz) / reg_refresh_rate 213 */ 214 writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL); 215 writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW); 216 217 /* set MR16 register */ 218 writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG); 219 writel(0, base + EMIF_LPDDR2_MODE_REG_DATA); 220 writel(CS1_MR(MR16_ADDR | REF_EN), 221 base + EMIF_LPDDR2_MODE_REG_CFG); 222 writel(0, base + EMIF_LPDDR2_MODE_REG_DATA); 223 /* LPDDR2 init complete */ 224 225} 226/***************************************** 227 * Routine: ddr_init 228 * Description: Configure DDR 229 * EMIF1 -- CS0 -- DDR1 (256 MB) 230 * EMIF2 -- CS0 -- DDR2 (256 MB) 231 *****************************************/ 232void omap4_ddr_init(const struct ddr_regs *emif1_ddr_regs, 233 const struct ddr_regs *emif2_ddr_regs) 234{ 235 /* DDR needs to be initialised @ 19.2 MHz 236 * So put core DPLL in bypass mode 237 * Configure the Core DPLL but don't lock it 238 */ 239 configure_core_dpll_no_lock(); 240 241 /* No IDLE: BUG in SDC */ 242 writel(0x0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL); 243 writel(0x0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL); 244 245 /* Configure EMIF1 */ 246 emif_config(EMIF1_BASE, emif1_ddr_regs); 247 248 /* Configure EMIF2 */ 249 emif_config(EMIF2_BASE, emif2_ddr_regs); 250 /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ 251 lock_core_dpll_shadow(); 252 /* TODO: SDC needs few hacks to get DDR freq update working */ 253 254 /* Set DLL_OVERRIDE = 0 */ 255 writel(0x0, CM_DLL_CTRL); 256 257 sdelay(200); 258 259 /* Check for DDR PHY ready for EMIF1 & EMIF2 */ 260 while(((readl(EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) 261 || ((readl(EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04)); 262 263 /* Reprogram the DDR PYHY Control register */ 264 /* PHY control values */ 265 266 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); 267 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); 268 269 /* Put the Core Subsystem PD to ON State */ 270 271 /* No IDLE: BUG in SDC */ 272 writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL); 273 writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL); 274 275 writel(0x0A300000, EMIF1_BASE + EMIF_L3_CONFIG); 276 writel(0x0A300000, EMIF2_BASE + EMIF_L3_CONFIG); 277 278 /* 279 * DMM : DMM_LISA_MAP_0(Section_0) 280 * [31:24] SYS_ADDR 0x80 281 * [22:20] SYS_SIZE 0x7 - 2Gb 282 * [19:18] SDRC_INTLDMM 0x1 - 128 byte 283 * [17:16] SDRC_ADDRSPC 0x0 284 * [9:8] SDRC_MAP 0x3 285 * [7:0] SDRC_ADDR 0X0 286 */ 287 288 reset_phy(EMIF1_BASE); 289 reset_phy(EMIF2_BASE); 290} 291