1/* 2 * ARM Ltd. 3 * 4 * FVP Foundation Platform (model) 5 * 6 * A reduced platform inspired by Versatile Express 7 * 8 */ 9 10/dts-v1/; 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <1>; 15 model = "V2P-AARCH64"; 16 compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 19 aliases { 20 serial0 = &v2m_serial0; 21 serial1 = &v2m_serial1; 22 serial2 = &v2m_serial2; 23 serial3 = &v2m_serial3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,armv8"; 33 reg = <0>; 34 enable-method = "spin-table"; 35 cpu-release-addr = <0x0 0x8000fff8>; 36 }; 37 cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,armv8"; 40 reg = <1>; 41 enable-method = "spin-table"; 42 cpu-release-addr = <0x0 0x8000fff8>; 43 }; 44 cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,armv8"; 47 reg = <2>; 48 enable-method = "spin-table"; 49 cpu-release-addr = <0x0 0x8000fff8>; 50 }; 51 cpu@3 { 52 device_type = "cpu"; 53 compatible = "arm,armv8"; 54 reg = <3>; 55 enable-method = "spin-table"; 56 cpu-release-addr = <0x0 0x8000fff8>; 57 }; 58 }; 59 60 memory@80000000 { 61 device_type = "memory"; 62 reg = < 0x00000000 0x80000000 0x80000000 63 0x00000008 0x80000000 0x80000000 >; 64 }; 65 66 gic: interrupt-controller@2c001000 { 67 compatible = "arm,cortex-a15-gic"; 68 #interrupt-cells = <3>; 69 #address-cells = <0>; 70 interrupt-controller; 71 reg = <0 0x2c001000 0x1000>, 72 <0 0x2c002000 0x1000>, 73 <0 0x2c004000 0x2000>, 74 <0 0x2c006000 0x2000>; 75 interrupts = <1 9 0xf04>; 76 }; 77 78 pmu { 79 compatible = "arm,armv8-pmuv3"; 80 interrupts = <0 60 4 0 61 4 0 62 4 0 63 4>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <1 13 0xff01>, 86 <1 14 0xff01>, 87 <1 11 0xff01>, 88 <1 10 0xff01>; 89 clock-frequency = <100000000>; 90 }; 91 92 motherboard { 93 compatible = "simple-bus"; 94 arm,v2m-memory-map = "rs1"; 95 #address-cells = <2>; /* SMB chipselect number and offset */ 96 #size-cells = <1>; 97 #interrupt-cells = <1>; 98 99 interrupt-map-mask = <0 0 63>; 100 interrupt-map = <0 0 0 &gic 0 0 4>, 101 <0 0 1 &gic 0 1 4>, 102 <0 0 2 &gic 0 2 4>, 103 <0 0 3 &gic 0 3 4>, 104 <0 0 4 &gic 0 4 4>, 105 <0 0 5 &gic 0 5 4>, 106 <0 0 6 &gic 0 6 4>, 107 <0 0 7 &gic 0 7 4>, 108 <0 0 8 &gic 0 8 4>, 109 <0 0 9 &gic 0 9 4>, 110 <0 0 10 &gic 0 10 4>, 111 <0 0 11 &gic 0 11 4>, 112 <0 0 12 &gic 0 12 4>, 113 <0 0 13 &gic 0 13 4>, 114 <0 0 14 &gic 0 14 4>, 115 <0 0 15 &gic 0 15 4>, 116 <0 0 16 &gic 0 16 4>, 117 <0 0 17 &gic 0 17 4>, 118 <0 0 18 &gic 0 18 4>, 119 <0 0 19 &gic 0 19 4>, 120 <0 0 20 &gic 0 20 4>, 121 <0 0 21 &gic 0 21 4>, 122 <0 0 22 &gic 0 22 4>, 123 <0 0 23 &gic 0 23 4>, 124 <0 0 24 &gic 0 24 4>, 125 <0 0 25 &gic 0 25 4>, 126 <0 0 26 &gic 0 26 4>, 127 <0 0 27 &gic 0 27 4>, 128 <0 0 28 &gic 0 28 4>, 129 <0 0 29 &gic 0 29 4>, 130 <0 0 30 &gic 0 30 4>, 131 <0 0 31 &gic 0 31 4>, 132 <0 0 32 &gic 0 32 4>, 133 <0 0 33 &gic 0 33 4>, 134 <0 0 34 &gic 0 34 4>, 135 <0 0 35 &gic 0 35 4>, 136 <0 0 36 &gic 0 36 4>, 137 <0 0 37 &gic 0 37 4>, 138 <0 0 38 &gic 0 38 4>, 139 <0 0 39 &gic 0 39 4>, 140 <0 0 40 &gic 0 40 4>, 141 <0 0 41 &gic 0 41 4>, 142 <0 0 42 &gic 0 42 4>; 143 144 ranges = <2 0 0x0 0x18000000 0x04000000>, 145 <3 0 0x0 0x1c000000 0x04000000>; 146 147 v2m_clk24mhz: clk24mhz { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <24000000>; 151 clock-output-names = "v2m:clk24mhz"; 152 }; 153 154 ethernet@2,02000000 { 155 compatible = "smsc,lan91c111"; 156 reg = <2 0x02000000 0x10000>; 157 interrupts = <15>; 158 }; 159 160 iofpga@3,00000000 { 161 compatible = "arm,amba-bus", "simple-bus"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0 3 0 0x200000>; 165 166 sysreg@010000 { 167 compatible = "arm,vexpress-sysreg"; 168 reg = <0x010000 0x1000>; 169 }; 170 171 v2m_serial0: uart@090000 { 172 compatible = "arm,pl011", "arm,primecell"; 173 reg = <0x090000 0x1000>; 174 interrupts = <5>; 175 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 176 clock-names = "uartclk", "apb_pclk"; 177 }; 178 179 v2m_serial1: uart@0a0000 { 180 compatible = "arm,pl011", "arm,primecell"; 181 reg = <0x0a0000 0x1000>; 182 interrupts = <6>; 183 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 184 clock-names = "uartclk", "apb_pclk"; 185 }; 186 187 v2m_serial2: uart@0b0000 { 188 compatible = "arm,pl011", "arm,primecell"; 189 reg = <0x0b0000 0x1000>; 190 interrupts = <7>; 191 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 192 clock-names = "uartclk", "apb_pclk"; 193 }; 194 195 v2m_serial3: uart@0c0000 { 196 compatible = "arm,pl011", "arm,primecell"; 197 reg = <0x0c0000 0x1000>; 198 interrupts = <8>; 199 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 200 clock-names = "uartclk", "apb_pclk"; 201 }; 202 203 virtio_block@0130000 { 204 compatible = "virtio,mmio"; 205 reg = <0x130000 0x1000>; 206 interrupts = <42>; 207 }; 208 }; 209 }; 210 211 /* chosen */ 212}; 213 214