1/* 2 3 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 33 */ 34#ifndef MLX4_DEVICE_H 35#define MLX4_DEVICE_H 36/* 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 */ 40#include <barrelfish/barrelfish.h> 41 42#include <linux/radix-tree.h> 43#include <linux/list.h> 44#include <linux/types.h> 45#include <linux/bitops.h> 46#include <linux/mm.h> 47 48/*#include <mlx4_ib.h>*/ 49 50#include <pci/mem.h> 51/* 52 #include <linux/bitops.h> 53 #include <linux/workqueue.h> 54 #include <asm/atomic.h> 55 56 #include <linux/clocksource.h> 57 */ 58#define MAX_MSIX_P_PORT 17 59#define MAX_MSIX 64 60#define MSIX_LEGACY_SZ 4 61#define MIN_MSIX_P_PORT 5 62 63#define MLX4_ROCE_MAX_GIDS 128 64#define MLX4_ROCE_PF_GIDS 16 65 66#define MLX4_NUM_UP 8 67#define MLX4_NUM_TC 8 68#define MLX4_MAX_100M_UNITS_VAL 255 /* 69 * work around: can't set values 70 * greater then this value when 71 * using 100 Mbps units. 72 */ 73#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 74#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 75#define MLX4_RATELIMIT_DEFAULT 0x00ff 76 77#define CORE_CLOCK_MASK 0xffffffffffffULL 78 79extern bool got_port_irq; 80extern bool got_up_irq; 81 82enum { 83 MLX4_FLAG_MSI_X = 1 << 0, 84 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 85 MLX4_FLAG_MASTER = 1 << 2, 86 MLX4_FLAG_SLAVE = 1 << 3, 87 MLX4_FLAG_SRIOV = 1 << 4, 88 MLX4_FLAG_DEV_NUM_STR = 1 << 5, 89 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 90}; 91/* 92 enum { 93 MLX4_PORT_CAP_IS_SM = 1 << 1, 94 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 95 }; 96 */ 97enum { 98 MLX4_MAX_PORTS = 2, MLX4_MAX_PORT_PKEYS = 128 99}; 100/* 101 base qkey for use in sriov tunnel-qp/proxy-qp communication. 102 * These qkeys must not be allowed for general use. This is a 64k range, 103 * and to test for violation, we use the mask (protect against future chg). 104 */ 105#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 106#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 107 108enum { 109 MLX4_BOARD_ID_LEN = 64, MLX4_VSD_LEN = 208 110}; 111 112enum { 113 MLX4_MAX_NUM_PF = 16, 114 MLX4_MAX_NUM_VF = 64, 115 MLX4_MFUNC_MAX = 80, 116 MLX4_MAX_EQ_NUM = 1024, 117 MLX4_MFUNC_EQ_NUM = 4, 118 MLX4_MFUNC_MAX_EQES = 8, 119 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 120}; 121/* 122 Driver supports 3 diffrent device methods to manage traffic steering: 123 * -device managed - High level API for ib and eth flow steering. FW is 124 * managing flow steering tables. 125 * - B0 steering mode - Common low level API for ib and (if supported) eth. 126 * - A0 steering mode - Limited low level API for eth. In case of IB, 127 * B0 mode is in use. 128 */ 129enum { 130 MLX4_STEERING_MODE_A0, 131 MLX4_STEERING_MODE_B0, 132 MLX4_STEERING_MODE_DEVICE_MANAGED 133}; 134 135static inline const char *mlx4_steering_mode_str(int steering_mode) { 136 switch (steering_mode) { 137 case MLX4_STEERING_MODE_A0: 138 return "A0 steering"; 139 140 case MLX4_STEERING_MODE_B0: 141 return "B0 steering"; 142 143 case MLX4_STEERING_MODE_DEVICE_MANAGED: 144 return "Device managed flow steering"; 145 146 default: 147 return "Unrecognize steering mode"; 148 } 149} 150 151enum { 152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 176 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44, 177 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 178 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49, 179 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53, 180 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 181 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57, 182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 185}; 186 187enum { 188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 192 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4, 193 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5, 194 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6, 195 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7, 196 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8, 197 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9, 198 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10, 199 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11, 200 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12, 201 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13, 202 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14, 203 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15, 204 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16, 205 MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17, 206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 207 MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19, 208 MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20, 209 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21, 210 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22, 211 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23, 212 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24, 213 MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25, 214}; 215/* 216 bit enums for an 8-bit flags field indicating special use 217 * QPs which require special handling in qp_reserve_range. 218 * Currently, this only includes QPs used by the ETH interface, 219 * where we expect to use blueflame. These QPs must not have 220 * bits 6 and 7 set in their qp number. 221 * 222 * This enum may use only bits 0..7. 223 */ 224 225enum { 226 MLX4_RESERVE_BF_QP = 1 << 7, 227}; 228 229enum { 230 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0 231}; 232 233enum { 234 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL 235 << 1 236}; 237 238enum { 239 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 240}; 241 242enum { 243 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 244}; 245 246#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 247 248enum { 249 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 250 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 251 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 252 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 253 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 254 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 255}; 256 257enum mlx4_event { 258 MLX4_EVENT_TYPE_COMP = 0x00, 259 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 260 MLX4_EVENT_TYPE_COMM_EST = 0x02, 261 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 262 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 263 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 264 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 265 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 266 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 267 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 268 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 269 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 270 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 271 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 272 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 273 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 274 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 275 MLX4_EVENT_TYPE_CMD = 0x0a, 276 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 277 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 278 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 279 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 280 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 281 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 282 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 283 MLX4_EVENT_TYPE_NONE = 0xff, 284}; 285 286enum { 287 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 288}; 289 290enum { 291 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 292 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 293}; 294 295enum { 296 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 297}; 298 299enum slave_port_state { 300 SLAVE_PORT_DOWN = 0, SLAVE_PENDING_UP, SLAVE_PORT_UP, 301}; 302 303enum slave_port_gen_event { 304 SLAVE_PORT_GEN_EVENT_DOWN = 0, 305 SLAVE_PORT_GEN_EVENT_UP, 306 SLAVE_PORT_GEN_EVENT_NONE, 307}; 308 309enum slave_port_state_event { 310 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 311 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 312 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 313 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 314}; 315 316enum { 317 MLX4_PERM_LOCAL_READ = 1 << 10, 318 MLX4_PERM_LOCAL_WRITE = 1 << 11, 319 MLX4_PERM_REMOTE_READ = 1 << 12, 320 MLX4_PERM_REMOTE_WRITE = 1 << 13, 321 MLX4_PERM_ATOMIC = 1 << 14, 322 MLX4_PERM_BIND_MW = 1 << 15, 323}; 324 325enum { 326 MLX4_OPCODE_NOP = 0x00, 327 MLX4_OPCODE_SEND_INVAL = 0x01, 328 MLX4_OPCODE_RDMA_WRITE = 0x08, 329 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 330 MLX4_OPCODE_SEND = 0x0a, 331 MLX4_OPCODE_SEND_IMM = 0x0b, 332 MLX4_OPCODE_LSO = 0x0e, 333 MLX4_OPCODE_RDMA_READ = 0x10, 334 MLX4_OPCODE_ATOMIC_CS = 0x11, 335 MLX4_OPCODE_ATOMIC_FA = 0x12, 336 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 337 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 338 MLX4_OPCODE_BIND_MW = 0x18, 339 MLX4_OPCODE_FMR = 0x19, 340 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 341 MLX4_OPCODE_CONFIG_CMD = 0x1f, 342 343 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 344 MLX4_RECV_OPCODE_SEND = 0x01, 345 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 346 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 347 348 MLX4_CQE_OPCODE_ERROR = 0x1e, 349 MLX4_CQE_OPCODE_RESIZE = 0x16, 350}; 351 352enum { 353 MLX4_STAT_RATE_OFFSET = 5 354}; 355 356enum mlx4_protocol { 357 MLX4_PROT_IB_IPV6 = 0, MLX4_PROT_ETH, MLX4_PROT_IB_IPV4, MLX4_PROT_FCOE 358}; 359 360enum { 361 MLX4_MTT_FLAG_PRESENT = 1 362}; 363 364enum { 365 MLX4_MAX_MTT_SHIFT = 31 366}; 367 368enum mlx4_qp_region { 369 MLX4_QP_REGION_FW = 0, 370 MLX4_QP_REGION_ETH_ADDR, 371 MLX4_QP_REGION_FC_ADDR, 372 MLX4_QP_REGION_FC_EXCH, 373 MLX4_NUM_QP_REGION 374}; 375 376enum mlx4_port_type { 377 MLX4_PORT_TYPE_NONE = 0, 378 MLX4_PORT_TYPE_IB = 1, 379 MLX4_PORT_TYPE_ETH = 2, 380 MLX4_PORT_TYPE_AUTO = 3, 381 MLX4_PORT_TYPE_NA = 4 382}; 383 384enum mlx4_special_vlan_idx { 385 MLX4_NO_VLAN_IDX = 0, MLX4_VLAN_MISS_IDX, MLX4_VLAN_REGULAR 386}; 387 388enum mlx4_steer_type { 389 MLX4_MC_STEER = 0, MLX4_UC_STEER, MLX4_NUM_STEERS 390}; 391 392enum { 393 MLX4_NUM_FEXCH = 64 * 1024, 394}; 395 396enum { 397 MLX4_MAX_FAST_REG_PAGES = 511, 398}; 399 400enum { 401 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 402 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 403 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 404}; 405 406/*Port mgmt change event handling*/ 407enum { 408 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 409 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 410 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 411 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 412 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 413}; 414 415#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 416 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 417 418enum mlx4_module_id { 419 MLX4_MODULE_ID_SFP = 0x3, 420 MLX4_MODULE_ID_QSFP = 0xC, 421 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 422 MLX4_MODULE_ID_QSFP28 = 0x11, 423}; 424 425static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) { 426 return (major << 32) | (minor << 16) | subminor; 427} 428 429struct mlx4_phys_caps { 430 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 431 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 432 u32 num_phys_eqs; 433 u32 base_sqpn; 434 u32 base_proxy_sqpn; 435 u32 base_tunnel_sqpn; 436}; 437 438struct mlx4_caps { 439 u64 fw_ver; 440 u32 function; 441 int num_ports; 442 int vl_cap[MLX4_MAX_PORTS + 1]; 443 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 444 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 445 u64 def_mac[MLX4_MAX_PORTS + 1]; 446 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 447 int gid_table_len[MLX4_MAX_PORTS + 1]; 448 int pkey_table_len[MLX4_MAX_PORTS + 1]; 449 int trans_type[MLX4_MAX_PORTS + 1]; 450 int vendor_oui[MLX4_MAX_PORTS + 1]; 451 int wavelength[MLX4_MAX_PORTS + 1]; 452 u64 trans_code[MLX4_MAX_PORTS + 1]; 453 int local_ca_ack_delay; 454 int num_uars; 455 u32 uar_page_size; 456 int bf_reg_size; 457 int bf_regs_per_page; 458 int max_sq_sg; 459 int max_rq_sg; 460 int num_qps; 461 int max_wqes; 462 int max_sq_desc_sz; 463 int max_rq_desc_sz; 464 int max_qp_init_rdma; 465 int max_qp_dest_rdma; 466 u32 *qp0_proxy; 467 u32 *qp1_proxy; 468 u32 *qp0_tunnel; 469 u32 *qp1_tunnel; 470 int num_srqs; 471 int max_srq_wqes; 472 int max_srq_sge; 473 int reserved_srqs; 474 int num_cqs; 475 int max_cqes; 476 int reserved_cqs; 477 int num_eqs; 478 int reserved_eqs; 479 int num_comp_vectors; 480 int comp_pool; 481 int num_mpts; 482 int max_fmr_maps; 483 u64 num_mtts; 484 int fmr_reserved_mtts; 485 int reserved_mtts; 486 int reserved_mrws; 487 int reserved_uars; 488 int num_mgms; 489 int num_amgms; 490 int reserved_mcgs; 491 int num_qp_per_mgm; 492 int steering_mode; 493 int num_pds; 494 int reserved_pds; 495 int max_xrcds; 496 int reserved_xrcds; 497 int mtt_entry_sz; 498 u32 max_msg_sz; 499 u32 page_size_cap; 500 u64 flags; 501 u64 flags2; 502 u32 bmme_flags; 503 u32 reserved_lkey; 504 u16 stat_rate_support; 505 u8 cq_timestamp; 506 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 507 int max_gso_sz; 508 int max_rss_tbl_sz; 509 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 510 int reserved_qps; 511 int reserved_qps_base[MLX4_NUM_QP_REGION]; 512 int log_num_macs; 513 int log_num_vlans; 514 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 515 u8 supported_type[MLX4_MAX_PORTS + 1]; 516 u8 suggested_type[MLX4_MAX_PORTS + 1]; 517 u8 default_sense[MLX4_MAX_PORTS + 1]; 518 u32 port_mask[MLX4_MAX_PORTS + 1]; 519 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 520 u32 max_counters; 521 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 522 u16 sqp_demux; 523 u32 sync_qp; 524 u32 cq_flags; 525 u32 eqe_size; 526 u32 cqe_size; 527 u8 eqe_factor; 528 u32 userspace_caps; /*userspace must be aware to*/ 529 u32 function_caps; /*functions must be aware to*/ 530 u8 fast_drop; 531 u16 hca_core_clock; 532 u32 max_basic_counters; 533 u32 max_extended_counters; 534 u8 def_counter_index[MLX4_MAX_PORTS + 1]; 535}; 536 537struct mlx4_buf_list { 538 void *buf; 539 genpaddr_t map; 540}; 541 542struct mlx4_buf { 543 struct mlx4_buf_list direct; 544 struct mlx4_buf_list *page_list; 545 int nbufs; 546 int npages; 547 int page_shift; 548}; 549 550struct mlx4_mtt { 551 u32 offset; 552 int order; 553 int page_shift; 554}; 555 556enum { 557 MLX4_DB_PER_PAGE = BASE_PAGE_SIZE / 4 558}; 559 560struct mlx4_db_pgdir { 561 struct list_head list; 562 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 563 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 564 unsigned long *bits[2]; 565 __be32 *db_page; 566 genpaddr_t db_dma; 567}; 568/* 569 struct mlx4_ib_user_db_page; 570 */ 571struct mlx4_db { 572 __be32 *db; 573 union { 574 struct mlx4_db_pgdir *pgdir; 575 struct mlx4_ib_user_db_page *user_page; 576 } u; 577 genpaddr_t dma; 578 int index; 579 int order; 580}; 581 582struct mlx4_hwq_resources { 583 struct mlx4_db db; 584 struct mlx4_mtt mtt; 585 struct mlx4_buf buf; 586}; 587 588struct mlx4_mr { 589 struct mlx4_mtt mtt; 590 u64 iova; 591 u64 size; 592 u32 key; 593 u32 pd; 594 u32 access; 595 int enabled; 596}; 597/* 598 enum mlx4_mw_type { 599 MLX4_MW_TYPE_1 = 1, 600 MLX4_MW_TYPE_2 = 2, 601 }; 602 603 struct mlx4_mw { 604 u32 key; 605 u32 pd; 606 enum mlx4_mw_type type; 607 int enabled; 608 }; 609 610 struct mlx4_fmr { 611 struct mlx4_mr mr; 612 struct mlx4_mpt_entry *mpt; 613 __be64 *mtts; 614 dma_addr_t dma_handle; 615 int max_pages; 616 int max_maps; 617 int maps; 618 u8 page_shift; 619 }; 620 */ 621struct mlx4_uar { 622 unsigned long pfn; 623 int index; 624 struct list_head bf_list; 625 unsigned free_bf_bmap; 626 void *map; /*__iomem*/ 627 void *bf_map; /*__iomem*/ 628}; 629 630struct mlx4_bf { 631 unsigned long offset; 632 int buf_size; 633 struct mlx4_uar *uar; 634 void /*__iomem*/*reg; 635}; 636 637struct mlx4_cq { 638 void (*comp)(/*struct mlx4_en_priv *priv,*/struct mlx4_cq *); 639 void (*event)(struct mlx4_cq *, enum mlx4_event); 640 641 struct mlx4_uar *uar; 642 643 u32 cons_index; 644 645 __be32 *set_ci_db; 646 __be32 *arm_db; 647 int arm_sn; 648 649 int cqn; 650 unsigned vector; 651 652 /*atomic_t refcount; 653 struct completion free;*/ 654 int eqn; 655 u16 irq; 656}; 657 658struct mlx4_qp { 659 void (*event)(struct mlx4_qp *, enum mlx4_event); 660 661 int qpn; 662 663/*atomic_t refcount; 664 struct completion free;*/ 665}; 666 667struct mlx4_srq { 668 void (*event)(struct mlx4_srq *, enum mlx4_event); 669 670 int srqn; 671 int max; 672 int max_gs; 673 int wqe_shift; 674 675/*atomic_t refcount; 676 struct completion free;*/ 677}; 678 679struct mlx4_av { 680 __be32 port_pd; 681 u8 reserved1; 682 u8 g_slid; 683 __be16 dlid; 684 u8 reserved2; 685 u8 gid_index; 686 u8 stat_rate; 687 u8 hop_limit; 688 __be32 sl_tclass_flowlabel; 689 u8 dgid[16]; 690}; 691 692struct mlx4_eth_av { 693 __be32 port_pd; 694 u8 reserved1; 695 u8 smac_idx; 696 u16 reserved2; 697 u8 reserved3; 698 u8 gid_index; 699 u8 stat_rate; 700 u8 hop_limit; 701 __be32 sl_tclass_flowlabel; 702 u8 dgid[16]; 703 u8 s_mac[6]; 704 u8 reserved4[2]; 705 __be16 vlan; 706 u8 mac[6]; 707}; 708 709union mlx4_ext_av { 710 struct mlx4_av ib; 711 struct mlx4_eth_av eth; 712 }; 713/* 714 struct mlx4_if_stat_control { 715 u8 reserved1[3]; 716 Extended counters enabled 717 u8 cnt_mode; 718 Number of interfaces 719 __be32 num_of_if; 720 __be32 reserved[2]; 721 }; 722 723 struct mlx4_if_stat_basic { 724 struct mlx4_if_stat_control control; 725 struct { 726 __be64 IfRxFrames; 727 __be64 IfRxOctets; 728 __be64 IfTxFrames; 729 __be64 IfTxOctets; 730 } counters[]; 731 }; 732 #define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\ 733 sizeof(((struct mlx4_if_stat_extended *)0)->\ 734 counters[0]) * ports) 735 736 struct mlx4_if_stat_extended { 737 struct mlx4_if_stat_control control; 738 struct { 739 __be64 IfRxUnicastFrames; 740 __be64 IfRxUnicastOctets; 741 __be64 IfRxMulticastFrames; 742 __be64 IfRxMulticastOctets; 743 __be64 IfRxBroadcastFrames; 744 __be64 IfRxBroadcastOctets; 745 __be64 IfRxNoBufferFrames; 746 __be64 IfRxNoBufferOctets; 747 __be64 IfRxErrorFrames; 748 __be64 IfRxErrorOctets; 749 __be32 reserved[39]; 750 __be64 IfTxUnicastFrames; 751 __be64 IfTxUnicastOctets; 752 __be64 IfTxMulticastFrames; 753 __be64 IfTxMulticastOctets; 754 __be64 IfTxBroadcastFrames; 755 __be64 IfTxBroadcastOctets; 756 __be64 IfTxDroppedFrames; 757 __be64 IfTxDroppedOctets; 758 __be64 IfTxRequestedFramesSent; 759 __be64 IfTxGeneratedFramesSent; 760 __be64 IfTxTsoOctets; 761 } __packed counters[]; 762 }; 763 #define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\ 764 sizeof(((struct mlx4_if_stat_extended *)\ 765 0)->counters[0]) * ports) 766 767 union mlx4_counter { 768 struct mlx4_if_stat_control control; 769 struct mlx4_if_stat_basic basic; 770 struct mlx4_if_stat_extended ext; 771 }; 772 #define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports) 773 */ 774struct mlx4_quotas { 775 int qp; 776 int cq; 777 int srq; 778 int mpt; 779 int mtt; 780 int counter; 781 int xrcd; 782}; 783 784struct mlx4_dev { 785 struct device_mem *bar_info; 786 struct pci_dev *pdev; 787 unsigned long flags; 788 /* unsigned long num_slaves;*/ 789 struct mlx4_caps caps; 790 struct mlx4_phys_caps phys_caps; 791 struct mlx4_quotas quotas; 792 struct radix_tree_root qp_table_tree; 793 u8 rev_id; 794 char board_id[MLX4_BOARD_ID_LEN]; 795 u16 vsd_vendor_id; 796 char vsd[MLX4_VSD_LEN]; 797 int num_vfs; 798 int numa_node; 799 int oper_log_mgm_entry_size; 800 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 801 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 802 803 /*DEBUGGING reasons: should be cleared*/ 804 int offset; 805 void *mtt_vaddr1; 806 void *mtt_vaddr2; 807 void *mtt_vaddr3; 808 void *mtt_vaddr4; 809 void *mtt_vaddr5; 810 void *mtt_vaddr6; 811 void *mtt_vaddr7; 812 void *mtt_vaddr8; 813 void *mtt_vaddr9; 814 void *mtt_vaddr10; 815 void *mtt_vaddr11; 816 void *mtt_vaddr12; 817 void *mtt_vaddr13; 818 void *mtt_vaddr14; 819 void *mtt_vaddr15; 820 void *mtt_vaddr16; 821 void *mtt_vaddr17; 822 void *mtt_vaddr18; 823 void *mtt_vaddr19; 824 void *mtt_vaddr20; 825 void *mtt_vaddr21; 826 void *mtt_vaddr22; 827 void *mtt_vaddr23; 828 void *mtt_vaddr24; 829 void *mtt_vaddr25; 830 void *mtt_vaddr26; 831 void *mtt_vaddr27; 832 void *mtt_vaddr28; 833 void *mtt_vaddr29; 834 void *mtt_vaddr30; 835 void *mtt_vaddr31; 836 void *mtt_vaddr32; 837 void *mtt_vaddr33; 838 void *mtt_vaddr34; 839 void *mtt_vaddr35; 840 void *mtt_vaddr36; 841 void *mtt_vaddr37; 842 void *mtt_vaddr38; 843 void *mtt_vaddr39; 844 void *mtt_vaddr40; 845 void *mtt_vaddr41; 846 void *mtt_vaddr42; 847 void *mtt_vaddr43; 848 void *mtt_vaddr44; 849 850}; 851 852struct mlx4_clock_params { 853 u64 offset; 854 u8 bar; 855 u8 size; 856}; 857 858struct mlx4_eqe { 859 u8 reserved1; 860 u8 type; 861 u8 reserved2; 862 u8 subtype; 863 union { 864 u32 raw[6]; 865 struct { 866 __be32 cqn; 867 }__packed comp; 868 struct { 869 u16 reserved1; 870 __be16 token; 871 u32 reserved2; 872 u8 reserved3[3]; 873 u8 status; 874 __be64 out_param; 875 }__packed cmd; 876 struct { 877 __be32 qpn; 878 }__packed qp; 879 struct { 880 __be32 srqn; 881 }__packed srq; 882 struct { 883 __be32 cqn; 884 u32 reserved1; 885 u8 reserved2[3]; 886 u8 syndrome; 887 }__packed cq_err; 888 struct { 889 u32 reserved1[2]; 890 __be32 port; 891 }__packed port_change; 892 struct { 893#define COMM_CHANNEL_BIT_ARRAY_SIZE 4 894 u32 reserved; 895 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 896 }__packed comm_channel_arm; 897 struct { 898 u8 port; 899 u8 reserved[3]; 900 __be64 mac; 901 }__packed mac_update; 902 struct { 903 __be32 slave_id; 904 }__packed flr_event; 905 struct { 906 __be16 current_temperature; 907 __be16 warning_threshold; 908 }__packed warming; 909 struct { 910 u8 reserved[3]; 911 u8 port; 912 union { 913 struct { 914 __be16 mstr_sm_lid; 915 __be16 port_lid; 916 __be32 changed_attr; 917 u8 reserved[3]; 918 u8 mstr_sm_sl; 919 __be64 gid_prefix; 920 }__packed port_info; 921 struct { 922 __be32 block_ptr; 923 __be32 tbl_entries_mask; 924 }__packed tbl_change_info; 925 }params; 926 }__packed port_mgmt_change; 927 struct { 928 u8 reserved[3]; 929 u8 port; 930 u32 reserved1[5]; 931 }__packed bad_cable; 932} event; 933u8 slave_id; 934u8 reserved3[2]; 935u8 owner; 936} __packed; 937 938struct mlx4_init_port_param { 939int set_guid0; 940int set_node_guid; 941int set_si_guid; 942u16 mtu; 943int port_width_cap; 944u16 vl_cap; 945u16 max_gid; 946u16 max_pkey; 947u64 guid0; 948u64 node_guid; 949u64 si_guid; 950}; 951 952#define MAD_IFC_DATA_SZ 192 953/*MAD IFC Mailbox*/ 954struct mlx4_mad_ifc { 955u8 base_version; 956u8 mgmt_class; 957u8 class_version; 958u8 method; 959__be16 status; 960__be16 class_specific; 961__be64 tid; 962__be16 attr_id; 963__be16 resv; 964__be32 attr_mod; 965__be64 mkey; 966__be16 dr_slid; 967__be16 dr_dlid; 968u8 reserved[28]; 969u8 data[MAD_IFC_DATA_SZ]; 970} __packed; 971 972#define mlx4_foreach_port(port, dev, type) \ 973 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 974 if ((type) == (dev)->caps.port_mask[(port)]) 975 976#define mlx4_foreach_non_ib_transport_port(port, dev) \ 977 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 978 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 979 980#define mlx4_foreach_ib_transport_port(port, dev) \ 981 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 982 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 983 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 984 985#define MLX4_INVALID_SLAVE_ID 0xFF 986 987#define MLX4_SINK_COUNTER_INDEX 0xff 988 989/*void handle_port_mgmt_change_event(struct work_struct *work);*/ 990 991static inline int mlx4_master_func_num(struct mlx4_dev *dev) { 992return dev->caps.function; 993} 994 995/*Always return false because SR-IOV is not yet enabled*/ 996static inline int mlx4_is_master(struct mlx4_dev *dev) { 997return dev->flags & MLX4_FLAG_MASTER; 998} 999 1000static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) { 1001return dev->phys_caps.base_sqpn + 8 1002 + 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1003} 1004 1005static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) { 1006return (qpn 1007 < dev->phys_caps.base_sqpn + 8 1008 + 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 1009} 1010 1011static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) { 1012int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1013 1014if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1015 return 1; 1016 1017return 0; 1018} 1019 1020/*Always return false because SR-IOV is not yet enabled*/ 1021static inline int mlx4_is_mfunc(struct mlx4_dev *dev) { 1022return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1023} 1024 1025/*Always return false because SR-IOV is not yet enabled*/ 1026static inline int mlx4_is_slave(struct mlx4_dev *dev) { 1027return dev->flags & MLX4_FLAG_SLAVE; 1028} 1029 1030struct mlx4_priv; 1031int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1032 struct mlx4_buf *buf); 1033/* 1034 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1035 */ 1036static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) { 1037if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1038 return (u8 *) buf->direct.buf + offset; 1039else 1040 return (u8 *) buf->page_list[offset >> PAGE_SHIFT].buf 1041 + (offset & (BASE_PAGE_SIZE - 1)); 1042} 1043 1044int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1045/* 1046 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1047 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1048 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1049 */ 1050int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1051/* 1052 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1053 */ 1054int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1055/* 1056 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1057 */ 1058int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1059 struct mlx4_mtt *mtt); 1060/* 1061 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1062 */ 1063u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1064int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1065 int npages, int page_shift, struct mlx4_mr *mr); 1066/* 1067 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1068 */ 1069int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1070/* 1071 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1072 struct mlx4_mw *mw); 1073 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1074 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1075 */ 1076int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, int start_index, 1077 int npages, u64 *page_list); 1078int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1079 struct mlx4_buf *buf); 1080int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1081/* 1082 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1083 */ 1084int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1085 int size, int max_direct); 1086/*int mlx4_alloc_hwq_res_qp(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1087 int size, int max_direct);*/ 1088/* 1089 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1090 int size); 1091 */ 1092int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1093 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, unsigned vector, 1094 int collapsed, int timestamp_en); 1095/* 1096 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1097 */ 1098int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base, 1099 u8 flags); 1100/* 1101 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1102 */ 1103int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1104/* 1105 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1106 1107 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1108 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1109 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1110 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1111 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1112 */ 1113int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1114int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1115 1116int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1117 int block_mcast_loopback, enum mlx4_protocol prot); 1118/* 1119 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1120 enum mlx4_protocol prot); 1121 */ 1122int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1123 u8 port, int block_mcast_loopback, enum mlx4_protocol protocol, u64 *reg_id); 1124/* 1125 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1126 enum mlx4_protocol protocol, u64 reg_id); 1127 */ 1128enum { 1129MLX4_DOMAIN_UVERBS = 0x1000, 1130MLX4_DOMAIN_ETHTOOL = 0x2000, 1131MLX4_DOMAIN_RFS = 0x3000, 1132MLX4_DOMAIN_NIC = 0x5000, 1133}; 1134 1135enum mlx4_net_trans_rule_id {MLX4_NET_TRANS_RULE_ID_ETH = 0, 1136MLX4_NET_TRANS_RULE_ID_IB, 1137MLX4_NET_TRANS_RULE_ID_IPV6, 1138MLX4_NET_TRANS_RULE_ID_IPV4, 1139MLX4_NET_TRANS_RULE_ID_TCP, 1140MLX4_NET_TRANS_RULE_ID_UDP, 1141MLX4_NET_TRANS_RULE_NUM, /*should be last*/ 1142MLX4_NET_TRANS_RULE_DUMMY = -1, /*force enum to be signed*/ 1143}; 1144/* 1145 extern const u16 __sw_id_hw[]; 1146 1147 static inline int map_hw_to_sw_id(u16 header_id) 1148 { 1149 1150 int i; 1151 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1152 if (header_id == __sw_id_hw[i]) 1153 return i; 1154 } 1155 return -EINVAL; 1156 } 1157 */ 1158enum mlx4_net_trans_promisc_mode { 1159MLX4_FS_REGULAR = 1, 1160MLX4_FS_ALL_DEFAULT, 1161MLX4_FS_MC_DEFAULT, 1162MLX4_FS_UC_SNIFFER, 1163MLX4_FS_MC_SNIFFER, 1164MLX4_FS_MODE_NUM, /*should be last*/ 1165MLX4_FS_MODE_DUMMY = -1, /*force enum to be signed*/ 1166}; 1167 1168struct mlx4_spec_eth { 1169u8 dst_mac[6]; 1170u8 dst_mac_msk[6]; 1171u8 src_mac[6]; 1172u8 src_mac_msk[6]; 1173u8 ether_type_enable; 1174__be16 ether_type; 1175__be16 vlan_id_msk; 1176__be16 vlan_id; 1177}; 1178 1179struct mlx4_spec_tcp_udp { 1180__be16 dst_port; 1181__be16 dst_port_msk; 1182__be16 src_port; 1183__be16 src_port_msk; 1184}; 1185 1186struct mlx4_spec_ipv4 { 1187__be32 dst_ip; 1188__be32 dst_ip_msk; 1189__be32 src_ip; 1190__be32 src_ip_msk; 1191}; 1192 1193struct mlx4_spec_ib { 1194__be32 l3_qpn; 1195__be32 qpn_msk; 1196u8 dst_gid[16]; 1197u8 dst_gid_msk[16]; 1198}; 1199 1200struct mlx4_spec_list { 1201struct list_head list; 1202enum mlx4_net_trans_rule_id id; 1203union { 1204 struct mlx4_spec_eth eth; 1205 struct mlx4_spec_ib ib; 1206 struct mlx4_spec_ipv4 ipv4; 1207 struct mlx4_spec_tcp_udp tcp_udp; 1208}; 1209}; 1210 1211enum mlx4_net_trans_hw_rule_queue { 1212MLX4_NET_TRANS_Q_FIFO, MLX4_NET_TRANS_Q_LIFO, 1213}; 1214 1215struct mlx4_net_trans_rule { 1216struct list_head list; 1217enum mlx4_net_trans_hw_rule_queue queue_mode; 1218bool exclusive; 1219bool allow_loopback; 1220enum mlx4_net_trans_promisc_mode promisc_mode; 1221u8 port; 1222u16 priority; 1223u32 qpn; 1224}; 1225 1226struct mlx4_net_trans_rule_hw_ctrl { 1227__be16 prio; 1228u8 type; 1229u8 flags; 1230u8 rsvd1; 1231u8 funcid; 1232u8 vep; 1233u8 port; 1234__be32 qpn; 1235__be32 rsvd2; 1236}; 1237 1238struct mlx4_net_trans_rule_hw_ib { 1239u8 size; 1240u8 rsvd1; 1241__be16 id; 1242u32 rsvd2; 1243__be32 l3_qpn; 1244__be32 qpn_mask; 1245u8 dst_gid[16]; 1246u8 dst_gid_msk[16]; 1247} __packed; 1248 1249struct mlx4_net_trans_rule_hw_eth { 1250u8 size; 1251u8 rsvd; 1252__be16 id; 1253u8 rsvd1[6]; 1254u8 dst_mac[6]; 1255u16 rsvd2; 1256u8 dst_mac_msk[6]; 1257u16 rsvd3; 1258u8 src_mac[6]; 1259u16 rsvd4; 1260u8 src_mac_msk[6]; 1261u8 rsvd5; 1262u8 ether_type_enable; 1263__be16 ether_type; 1264__be16 vlan_tag_msk; 1265__be16 vlan_tag; 1266} __packed; 1267 1268struct mlx4_net_trans_rule_hw_tcp_udp { 1269u8 size; 1270u8 rsvd; 1271__be16 id; 1272__be16 rsvd1[3]; 1273__be16 dst_port; 1274__be16 rsvd2; 1275__be16 dst_port_msk; 1276__be16 rsvd3; 1277__be16 src_port; 1278__be16 rsvd4; 1279__be16 src_port_msk; 1280} __packed; 1281 1282struct mlx4_net_trans_rule_hw_ipv4 { 1283u8 size; 1284u8 rsvd; 1285__be16 id; 1286__be32 rsvd1; 1287__be32 dst_ip; 1288__be32 dst_ip_msk; 1289__be32 src_ip; 1290__be32 src_ip_msk; 1291} __packed; 1292 1293struct _rule_hw { 1294union { 1295 struct { 1296 u8 size; 1297 u8 rsvd; 1298 __be16 id; 1299 }; 1300 struct mlx4_net_trans_rule_hw_eth eth; 1301 struct mlx4_net_trans_rule_hw_ib ib; 1302 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1303 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1304}; 1305}; 1306/* 1307 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1308 enum mlx4_net_trans_promisc_mode mode); 1309 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1310 enum mlx4_net_trans_promisc_mode mode); 1311 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1312 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1313 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1314 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1315 */ 1316int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1317/* 1318 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1319 */ 1320int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1321/* 1322 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1323 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, unsigned long *stats_bitmap); 1324 */ 1325int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, u8 pptx, 1326 u8 pfctx, u8 pprx, u8 pfcrx); 1327int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1328 u8 promisc); 1329/* 1330 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1331 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1332 u8 *pg, u16 *ratelimit); 1333 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1334 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1335 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1336 1337 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1338 int npages, u64 iova, u32 *lkey, u32 *rkey); 1339 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1340 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1341 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1342 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1343 u32 *lkey, u32 *rkey); 1344 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1345 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1346 int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 1347 u8 op_modifier, u32 in_offset[], 1348 u32 counter_out[]); 1349 1350 int mlx4_test_interrupts(struct mlx4_dev *dev); 1351 int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector); 1352 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1353 1354 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1355 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1356 */ 1357int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, int *idx); 1358/* 1359 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx); 1360 */ 1361int mlx4_flow_attach(struct mlx4_dev *dev, struct mlx4_net_trans_rule *rule, 1362 u64 *reg_id); 1363int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1364/* 1365 int map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1366 enum mlx4_net_trans_promisc_mode flow_type); 1367 int map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1368 enum mlx4_net_trans_rule_id id); 1369 */ 1370int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1371/* 1372 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1373 int i, int val); 1374 1375 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1376 1377 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1378 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1379 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1380 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl); 1381 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1382 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1383 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1384 1385 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1386 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1387 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id); 1388 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid); 1389 */ 1390int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1391 u32 max_range_qpn); 1392/* 1393 int mlx4_read_clock(struct mlx4_dev *dev); 1394 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1395 struct mlx4_clock_params *params); 1396 1397 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1398 u16 offset, u16 size, u8 *data); 1399 1400 */ 1401 1402#endif /*MLX4_DEVICE_H*/ 1403