1/** 2 * \file 3 * \brief Arch specific definition of the registers, can be included by anyone. 4 * Definitions only seen in the user. 5 */ 6 7/* 8 * Copyright (c) 2010, 2012, ETH Zurich. 9 * All rights reserved. 10 * 11 * This file is distributed under the terms in the attached LICENSE file. 12 * If you do not find this file, copies can be found by writing to: 13 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 14 */ 15 16#ifndef TARGET_X86_64_BARRELFISH_REGISTERS_H 17#define TARGET_X86_64_BARRELFISH_REGISTERS_H 18 19#include <target/x86_64/barrelfish_kpi/registers_target.h> 20#include <target/x86_64/barrelfish_kpi/cpu_target.h> 21#include "threads_priv.h" 22 23static inline void 24registers_x86_64_set_initial(struct registers_x86_64 *regs, struct thread *thread, 25 lvaddr_t entry, lvaddr_t stack, uint64_t arg1, 26 uint64_t arg2, uint64_t arg3, uint64_t arg4) 27{ 28 // XXX: the x86-64 ELF ABI requires that (RSP - 8) be 16-byte aligned. why?! 29 assert((stack % 16) == 0); 30 stack -= sizeof(uintptr_t); 31 32 regs->rip = entry; 33 regs->rsp = stack; 34 regs->eflags = USER_EFLAGS; 35 regs->fs = thread->thread_seg_selector; 36 regs->gs = 0; 37 38 regs->rdi = arg1; 39 regs->rsi = arg2; 40 regs->rdx = arg3; 41 regs->rcx = arg4; 42 43 memset(®s->fxsave_area, 0, sizeof(regs->fxsave_area)); 44 regs->fxsave_area.fcw = 0x037f; // fcw 45#if __k1om__ 46 regs->fxsave_area.mxcsr = 0x00200000; // mxcsr 47#else 48 regs->fxsave_area.mxcsr = 0x00001f80; // mxcsr 49#endif 50} 51 52#endif // TARGET_X86_64_BARRELFISH_REGISTERS_H 53