1/**
2 * \file
3 * \brief Platform code for the Xilinx Zynq7000-series SoCs
4 */
5
6/*
7 * Copyright (c) 2016 ETH Zurich.
8 * All rights reserved.
9 *
10 * This file is distributed under the terms in the attached LICENSE file.
11 * If you do not find this file, copies can be found by writing to:
12 * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group.
13 */
14
15#include <kernel.h>
16
17#include <maps/zynq7_map.h>
18
19/* RAM starts at 0 on the Zynq */
20/* XXX - MMAP */
21lpaddr_t phys_memory_start= 0;
22
23#define NUM_UARTS 2
24unsigned int serial_console_port = 1;
25unsigned int serial_debug_port = 1;
26unsigned int serial_num_physical_ports = NUM_UARTS;
27
28const lpaddr_t
29uart_base[NUM_UARTS]= {
30    ZINQ7_UART0_BASEADDR,
31    ZINQ7_UART1_BASEADDR
32};
33
34const size_t
35uart_size[NUM_UARTS]= {
36    (1<<12),
37    (1<<12)
38};
39