1/* 2 * Copyright (c) 2014 ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10#ifndef XEON_PHI_XEON_PHI_H_ 11#define XEON_PHI_XEON_PHI_H_ 12 13/// The maximum number of coprocessor cards in a system 14#define XEON_PHI_NUM_MAX 8 15 16#define XEON_PHI_CBOX_BASE 0x0ULL /* P54C Core */ 17#define XEON_PHI_TXS0_BASE 0x0800780000ULL /* Texture Sampler */ 18#define XEON_PHI_TXS1_BASE 0x0800770000ULL /* Texture Sampler */ 19#define XEON_PHI_TXS2_BASE 0x0800760000ULL /* Texture Sampler */ 20#define XEON_PHI_TXS3_BASE 0x0800750000ULL /* Texture Sampler */ 21#define XEON_PHI_TXS4_BASE 0x0800740000ULL /* Texture Sampler */ 22#define XEON_PHI_TXS5_BASE 0x0800730000ULL /* Texture Sampler */ 23#define XEON_PHI_TXS6_BASE 0x0800720000ULL /* Texture Sampler */ 24#define XEON_PHI_TXS7_BASE 0x0800710000ULL /* Texture Sampler */ 25#define XEON_PHI_DBOX0_BASE 0x08007C0000ULL /* Display Box Registers */ 26#define XEON_PHI_DBOX1_BASE 0x0800620000ULL /* Display Box Registers */ 27#define XEON_PHI_TD0_BASE 0x08007C0000ULL /* Dbox Tag Directory TD */ 28#define XEON_PHI_TD1_BASE 0x0800620000ULL /* Dbox Tag Directory TD */ 29#define XEON_PHI_VBOX_BASE 0x08007B0000ULL /* Video Box Registers */ 30#define XEON_PHI_SBOX_BASE 0x08007D0000ULL /* PCIE Box Registers */ 31#define XEON_PHI_GBOX0_BASE 0x08007A0000ULL /* Gbox Front Box Registers */ 32#define XEON_PHI_GBOX1_BASE 0x0800790000ULL /* Gbox Front Box Registers */ 33#define XEON_PHI_GBOX2_BASE 0x0800700000ULL /* Gbox Front Box Registers */ 34#define XEON_PHI_GBOX3_BASE 0x08006F0000ULL /* Gbox Front Box Registers */ 35#define XEON_PHI_GBOX4_BASE 0x08006D0000ULL /* Gbox Front Box Registers */ 36#define XEON_PHI_GBOX5_BASE 0x08006C0000ULL /* Gbox Front Box Registers */ 37#define XEON_PHI_GBOX6_BASE 0x08006B0000ULL /* Gbox Front Box Registers */ 38#define XEON_PHI_GBOX7_BASE 0x08006A0000ULL /* Gbox Front Box Registers */ 39#define XEON_PHI_REUT0_BASE 0x08007A0000ULL /* Gbox REUT interface Registers */ 40#define XEON_PHI_REUT1_BASE 0x0800790000ULL /* Gbox REUT interface Registers */ 41#define XEON_PHI_REUT2_BASE 0x0800700000ULL /* Gbox REUT interface Registers */ 42#define XEON_PHI_REUT3_BASE 0x08006F0000ULL /* Gbox REUT interface Registers */ 43#define XEON_PHI_REUT4_BASE 0x08006D0000ULL /* Gbox REUT interface Registers */ 44#define XEON_PHI_REUT5_BASE 0x08006C0000ULL /* Gbox REUT interface Registers */ 45#define XEON_PHI_REUT6_BASE 0x08006B0000ULL /* Gbox REUT interface Registers */ 46#define XEON_PHI_REUT7_BASE 0x08006A0000ULL /* Gbox REUT interface Registers */ 47 48#define XEON_PHI_GBOX_CHANNEL0_BASE 0x0 49#define XEON_PHI_GBOX_CHANNEL1_BASE 0x800 50#define XEON_PHI_GBOX_CHANNEL2_BASE 0x800 51#define XEON_PHI_GBOX_CHANNEL3_BASE 0x1000 52 53#define XEON_PHI_SBOX_SIZE (64*1024) 54#define XEON_PHI_SBOX_SIZE_BITS (16) 55 56// TODO: Verify these... 57#define XEON_PHI_GBOX_SIZE (64*1024) 58#define XEON_PHI_DBOX_SIZE (64*1024) 59#define XEON_PHI_CBOX_SIZE (64*1024) 60 61#define XEON_PHI_SYSMEM_BASE 0x8000000000ULL 62#define XEON_PHI_SYSMEM_SIZE_BITS 39 63#define XEON_PHI_SYSMEM_SIZE (1ULL << XEON_PHI_SYSMEM_SIZE_BITS) 64#define XEON_PHI_SYSMEM_PAGE_SIZE (16UL*1024*1024*1024) 65#define XEON_PHI_SYSMEM_PAGE_BITS 34 66 67#define XEON_PHI_SYSMEM_KNC_BASE (XEON_PHI_SYSMEM_BASE + 25 * XEON_PHI_SYSMEM_PAGE_SIZE) 68 69#define XEON_PHI_MEM_MASK 0xFFFFFFFFFFULL 70 71/** 72 * layout of the boot parameter data structure 73 * 74 * XXX: some fields will be overwritten by the Xeon Phi firmware! 75 */ 76struct xeon_phi_boot_params 77{ 78 uint8_t reserved[0x54]; 79 uint64_t tboot_addr; /* 0x058 */ 80 uint8_t _pad3[128]; /* 0x070 */ 81 uint8_t dummy[256]; 82 uint8_t _pad1[4]; 83 uint32_t scratch; /* Scratch field! *//* 0x1e4 */ 84 uint8_t _pad6[13]; /* 0x1eb */ 85 uint8_t setup_sects; /// must be at this very location !!! 86 uint16_t root_flags; 87 uint32_t syssize; /// must be at this very location !!! 88 uint16_t _pad2[5]; 89 uint32_t header; /// must be at this very location !!! 90 uint16_t version; 91 uint32_t realmode_swtch; 92 uint16_t start_sys; 93 uint16_t kernel_version; 94 uint8_t type_of_loader; 95 uint8_t loadflags; 96 uint16_t setup_move_size; 97 uint32_t code32_start; 98 uint32_t ramdisk_image; /// pointer to the multiboot image 99 uint32_t ramdisk_size; /// multiboot image size 100 uint32_t bootsect_kludge; 101 uint16_t loader_name; 102 uint8_t ext_loader_ver; 103 uint8_t ext_loader_type; 104 uint32_t payload_offset; 105 uint32_t initrd_addr_max; 106 uint32_t kernel_alignment; 107 uint8_t _pad4[4]; 108 uint32_t cmdline_size; /// size of the command line 109 uint32_t hardware_subarch; 110 uint64_t hardware_subarch_data; 111 uint32_t cmdline_ptr; /// pointer to the command line 112 uint32_t xeon_phi_id; 113 uint64_t msg_base; /// pointer to the host message base address 114 uint8_t msg_size_bits; /// size of the messaging channel 115 //uint64_t multiboot; /// pointer to the multiboot information 116 uint32_t mbi; 117}__attribute__((packed)); 118 119 120typedef uint8_t xphi_chan_type_t; 121 122typedef uint8_t xphi_id_t; 123 124typedef uint64_t xphi_dom_id_t; 125 126static inline xphi_dom_id_t xeon_phi_domain_build_id(xphi_id_t xid, 127 uint8_t core, 128 uint8_t is_host, 129 domainid_t domid) 130{ 131 xphi_dom_id_t did = xid; 132 did <<= 8; 133 did |= core; 134 did <<= 32; 135 did |=domid; 136 if (is_host) { 137 did |= (1UL << 63); 138 } 139 return did; 140} 141 142static inline xphi_id_t xeon_phi_domain_get_xid(xphi_dom_id_t domid) 143{ 144 return (0xFF & (domid >> 40)); 145} 146 147static inline xphi_id_t xeon_phi_domain_get_core(xphi_dom_id_t domid) 148{ 149 return (0xFF & (domid >> 32)); 150} 151 152static inline uint8_t xeon_phi_domain_is_on_host(xphi_dom_id_t domid) 153{ 154 return !!((1UL << 63) & domid); 155} 156 157 158#endif // XEON_PHI_XEON_PHI_H_ 159