1/** 2 * \file 3 * \brief Arch specific definitions, can be included by others. 4 */ 5 6/* 7 * Copyright (c) 2010-2013 ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef TARGET_X86_32_BARRELFISH_KPI_PAGING_H 16#define TARGET_X86_32_BARRELFISH_KPI_PAGING_H 17 18#ifndef __ASSEMBLER__ 19#ifdef CONFIG_PAE 20typedef uint64_t paging_x86_32_flags_t; 21#else 22typedef uint32_t paging_x86_32_flags_t; 23#endif 24#endif 25 26/** The system's base page size is 4kB */ 27#define X86_32_BASE_PAGE_BITS 12 28#define X86_32_BASE_PAGE_SIZE 0x1000 29#define X86_32_BASE_PAGE_MASK (X86_32_BASE_PAGE_SIZE - 1) 30#define X86_32_BASE_PAGE_OFFSET(a) ((a) & X86_32_BASE_PAGE_MASK) 31 32/** The system's large page size is 2MB or 4MB */ 33#ifdef CONFIG_PAE 34#define X86_32_LARGE_PAGE_BITS 21 35#define X86_32_LARGE_PAGE_SIZE 0x200000 36 37#else 38#define X86_32_LARGE_PAGE_BITS 22 39#define X86_32_LARGE_PAGE_SIZE 0x400000 40 41#endif 42 43#define X86_32_LARGE_PAGE_MASK (X86_32_LARGE_PAGE_SIZE - 1) 44#define X86_32_LARGE_PAGE_OFFSET(a) ((a) & X86_32_LARGE_PAGE_MASK) 45 46/** 47 * Bits within the various page directories and tables. 48 */ 49#ifdef CONFIG_NXE 50# define X86_32_PTABLE_EXECUTE_DISABLE (((paging_x86_32_flags_t)1) << 63) 51#else 52# define X86_32_PTABLE_EXECUTE_DISABLE ((paging_x86_32_flags_t)0) 53#endif 54#define X86_32_PTABLE_GLOBAL_PAGE (((paging_x86_32_flags_t)1) << 8) 55#define X86_32_PTABLE_ATTR_INDEX (((paging_x86_32_flags_t)1) << 7) 56#define X86_32_PTABLE_DIRTY (((paging_x86_32_flags_t)1) << 6) 57#define X86_32_PTABLE_ACCESSED (((paging_x86_32_flags_t)1) << 5) 58#define X86_32_PTABLE_CACHE_DISABLED (((paging_x86_32_flags_t)1) << 4) 59#define X86_32_PTABLE_WRITE_THROUGH (((paging_x86_32_flags_t)1) << 3) 60#define X86_32_PTABLE_USER_SUPERVISOR (((paging_x86_32_flags_t)1) << 2) 61#define X86_32_PTABLE_READ_WRITE (((paging_x86_32_flags_t)1) << 1) 62#define X86_32_PTABLE_PRESENT (((paging_x86_32_flags_t)1) << 0) 63 64#ifdef CONFIG_PAE 65#define X86_32_PDPTE_BITS 2 66#define X86_32_PDPTE_SIZE (1U<<X86_32_PDPTE_BITS) 67#define X86_32_PDPTE_MASK (X86_32_PDPTE_SIZE - 1) 68#define X86_32_PDPTE_CLEAR 0 69 70#define X86_32_PDIR_BITS 9 71#define X86_32_PDIR_SIZE (1U<<X86_32_PDIR_BITS) 72#define X86_32_PDIR_MASK (X86_32_PDIR_SIZE - 1) 73#define X86_32_PDIR_CLEAR 0 74 75#define X86_32_PTABLE_BITS 9 76#define X86_32_PTABLE_SIZE (1U<<X86_32_PTABLE_BITS) /**< Page directory/table size */ 77#define X86_32_PTABLE_MASK (X86_32_PTABLE_SIZE-1) /**< Page dir/table address mask */ 78#define X86_32_PTABLE_CLEAR 0 /**< Bitmap of a clear table entry */ 79 80#else 81#define X86_32_PDIR_BITS 10 82#define X86_32_PDIR_SIZE (1U << X86_32_PDIR_BITS) 83#define X86_32_PDIR_MASK (X86_32_PDIR_SIZE - 1) 84#define X86_32_PDIR_CLEAR 0 85 86#define X86_32_PTABLE_BITS 10 87#define X86_32_PTABLE_SIZE (1U<<X86_32_PTABLE_BITS) /**< Page directory/table size */ 88#define X86_32_PTABLE_MASK (X86_32_PTABLE_SIZE - 1) /**< Page dir/table address mask */ 89#define X86_32_PTABLE_CLEAR 0 /**< Bitmap of a clear table entry */ 90 91#endif 92 93#define X86_32_PTABLE_ENTRY_SIZE sizeof(union x86_32_pdir_entry) 94 95#ifdef CONFIG_PAE 96#define X86_32_PDPTE_BASE(base) (((uint32_t)(base) >> 30) & X86_32_PDPTE_MASK) 97#define X86_32_PDIR_BASE(base) (((uint32_t)(base) >> 21) & X86_32_PTABLE_MASK) 98#define X86_32_PTABLE_BASE(base) (((uint32_t)(base) >> 12) & X86_32_PTABLE_MASK) 99#else 100#define X86_32_PDIR_BASE(base) (((uint32_t)(base) >> 22) & X86_32_PTABLE_MASK) 101#define X86_32_PTABLE_BASE(base) (((uint32_t)(base) >> 12) & X86_32_PTABLE_MASK) 102#endif 103 104/// Default access is read/write, but not execute 105#define X86_32_PTABLE_ACCESS_DEFAULT \ 106 (X86_32_PTABLE_EXECUTE_DISABLE | X86_32_PTABLE_USER_SUPERVISOR | \ 107 X86_32_PTABLE_READ_WRITE) 108#define X86_32_PTABLE_ACCESS_READONLY \ 109 (X86_32_PTABLE_EXECUTE_DISABLE | X86_32_PTABLE_USER_SUPERVISOR) 110 111#endif // TARGET_X86_32_BARRELFISH_KPI_PAGING_H 112