1/** 2 * \file 3 * \brief Paging definitions for arm_v7. 4 */ 5 6/* 7 * Copyright (c) 2012, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V7_H 16#define TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V7_H 17 18/* Default page size is 4K */ 19#define BASE_PAGE_BITS 12 20#define BASE_PAGE_SIZE (1u << BASE_PAGE_BITS) 21#define BASE_PAGE_MASK (BASE_PAGE_SIZE - 1) 22#define BASE_PAGE_OFFSET(a) ((a) & BASE_PAGE_MASK) 23 24/* 1MB large pages */ 25#define LARGE_PAGE_BITS 20 26#define LARGE_PAGE_SIZE (1u << LARGE_PAGE_BITS) 27#define LARGE_PAGE_MASK (LARGE_PAGE_SIZE - 1) 28#define LARGE_PAGE_OFFSET(a) ((a) & LARGE_PAGE_MASK) 29 30#define ARM_L1_OFFSET(addr) ((((uintptr_t)addr) >> 20) & 0xfff) 31#define ARM_L2_OFFSET(addr) ((((uintptr_t)addr) >> 12) & 0xff) 32#define ARM_PAGE_OFFSET(addr) ((uintptr_t)addr & 0xfff) 33 34 35#define ARM_L1_MAX_ENTRIES 4096u 36#define ARM_L1_BYTES_PER_ENTRY 4u 37#define ARM_L1_ALIGN 16384u 38#define ARM_L1_SECTION_BITS 20u 39#define ARM_L1_SECTION_BYTES (1u << ARM_L1_SECTION_BITS) 40#define ARM_L1_SECTION_MASK (ARM_L1_SECTION_BYTES - 1u) 41#define ARM_L1_SECTION_OFFSET(a) ((a) & ARM_L1_SECTION_MASK) 42#define ARM_L1_SECTION_NUMBER(a) ((a) >> ARM_L1_SECTION_BITS) 43 44 45#define ARM_L2_MAX_ENTRIES 256u 46#define ARM_L2_BYTES_PER_ENTRY 4u 47#define ARM_L2_ALIGN 1024u 48#define ARM_L2_TABLE_BITS 10u 49#define ARM_L2_TABLE_BYTES (1 << ARM_L2_TABLE_BITS) 50#define ARM_L2_TABLE_MASK (ARM_L2_TABLE_BYTES - 1u) 51#define ARM_L2_TABLE_OFFSET(a) ((a) & ARM_L2_TABLE_MASK) 52#define ARM_L2_TABLE_PPN(a) ((a) >> ARM_L2_TABLE_BITS) 53 54#define ARM_L2_SMALL_CACHEABLE 0x008 55#define ARM_L2_SMALL_BUFFERABLE 0x004 56#define ARM_L2_SMALL_USR_RO 0x20 57#define ARM_L2_SMALL_USR_RW 0x30 58#define ARM_L2_SMALL_USR_NONE 0x10 59 60/* Page type independent page options */ 61#define KPI_PAGING_FLAGS_READ 0x01 62#define KPI_PAGING_FLAGS_WRITE 0x02 63#define KPI_PAGING_FLAGS_EXECUTE 0x04 64#define KPI_PAGING_FLAGS_NOCACHE 0x08 65#define KPI_PAGING_FLAGS_MASK 0x0f 66 67union arm_l1_entry { 68 uint32_t raw; 69 70 /// Invalid L1 entry 71 struct { 72 uint32_t type :2; // == 0 73 } invalid; 74 75 /// L1 entry for 256 4K L2 entries 76 struct { 77 uint32_t type :2; // == 1 78 uint32_t pxn :1; // PXN 79 uint32_t ns :1; 80 uint32_t sbz0 :1; // Should-be-zero 81 uint32_t domain :4; 82 uint32_t sbz1 :1; // Should-be-zero 83 uint32_t base_address :22; 84 } page_table; 85 86 /// L1 entry for 1MB mapped section 87 struct { 88 uint32_t type :2; // == 2 89 uint32_t bufferable :1; 90 uint32_t cacheable :1; 91 uint32_t execute_never :1; 92 uint32_t domain :4; 93 uint32_t sbz0 :1; 94 uint32_t ap10 :2; // AP[1:0] 95 uint32_t tex :3; // type extension 96 uint32_t ap2 :1; // AP[2] 97 uint32_t shareable :1; 98 uint32_t not_global :1; 99 uint32_t mbz0 :1; //must be zero 100 uint32_t ns :1; 101 uint32_t base_address :12; 102 } section; 103 104 /// L1 entry for 16MB mapped super section 105 struct { 106 uint32_t type :2; // == 3 107 uint32_t bufferable :1; 108 uint32_t cacheable :1; 109 uint32_t execute_never :1; 110 uint32_t domain :4; 111 uint32_t sbz0 :1; 112 uint32_t ap10 :2; // AP[1:0] 113 uint32_t tex :3; // type extension 114 uint32_t ap2 :1; // AP[2] 115 uint32_t shareable :1; 116 uint32_t not_global :1; 117 uint32_t mbz0 :1; //must be one 118 uint32_t ns :1; 119 uint32_t base_address :12; 120 } super_section; 121 122}; 123 124#define L1_TYPE_INVALID_ENTRY 0 125#define L1_TYPE_PAGE_TABLE_ENTRY 1 126#define L1_TYPE_SECTION_ENTRY 2 127/* XXX - this is wrong. Supersections are marked by bit 18. */ 128#define L1_TYPE_SUPER_SECTION_ENTRY 3 129#define L1_TYPE(x) ((x) & 3) 130 131union arm_l2_entry { 132 uint32_t raw; 133 134 /// Invalid L2 entry 135 struct { 136 uint32_t type :2; // == 0 137 } invalid; 138 139 /// Descriptior for a 64K page 140 struct { 141 uint32_t type :2; // == 1 142 uint32_t bufferable :1; 143 uint32_t cacheable :1; 144 uint32_t ap10 :2; // AP[1:0] 145 uint32_t sbz0 :3; // should be zero 146 uint32_t ap2 :1; // AP[2] 147 uint32_t shareable :1; 148 uint32_t not_global :1; 149 uint32_t tex :3; // type extension TEX[2:0] 150 uint32_t execute_never :1; 151 uint32_t base_address :16; 152 } large_page; 153 154 /// Descriptor for a 4K page 155 struct { 156 uint32_t type :2; // == 2 or 3 157 uint32_t bufferable :1; 158 uint32_t cacheable :1; 159 uint32_t ap10 :2; // AP[1:0] 160 uint32_t tex :3; // type extension TEX[2:0] 161 uint32_t ap2 :1; // AP[2] 162 uint32_t shareable :1; 163 uint32_t not_global :1; 164 uint32_t base_address :20; 165 } small_page; 166 167}; 168 169 170#define L2_TYPE_INVALID_PAGE 0 171#define L2_TYPE_LARGE_PAGE 1 172#define L2_TYPE_SMALL_PAGE 2 173#define L2_TYPE_SMALL_PAGE_XN 3 174#define L2_TYPE(x) ((x) & 3) 175 176#define BYTES_PER_SECTION ARM_L1_SECTION_BYTES 177#define BYTES_PER_LARGE_PAGE 0x10000 178#define BYTES_PER_PAGE 0x1000 179#define BYTES_PER_SMALL_PAGE ARM_L2_TABLE_BYTES 180 181#endif // TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V7_H 182