1/** 2 * \file 3 * \brief AMD performance monitoring infrastructure. 4 */ 5 6/* 7 * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef BARRELFISH_KPI_PERFMON_H 16#define BARRELFISH_KPI_PERFMON_H 17 18#define EVENT_L2_LINES_IN 0x24 19 20/* 21 * The following are derived from the AMD "BIOS and Kernel Developer's 22 * Guide (family 10h)", Section 3.14. 23 */ 24 25// 3.14.3 Data Cache Events 26 27// Instructions retired 28#define EVENT_AMD_INSTRUCTIONS_RETIRED 0xC0 29 30// DRAM Access 31#define EVENT_AMD_DRAM_ACCESS 0xE0 32 33// L1 DTLB MISS AND L2 DTLB HIT 34#define EVENT_AMD_L1DTLB_MISS_L2_DTLB_HIT 0x45 35 36// L1 DTLB MISS AND L2 DTLB MISS 37#define EVENT_AMD_L1DTLB_MISS_L2_DTLB_MISS 0x46 38 39// Data Cache Misses 40#define EVENT_AMD_DATA_CACHE_MISSES 0x41 41 42// Interrupts taken 43#define EVENT_AMD_INTERRUPTS_TAKEN 0xCF 44 45// Dispatch Stalls 46#define EVENT_AMD_DISPATCH_STALLS 0xD1 47 48// Dispatch Stall Reorder buffer full 49#define EVENT_AMD_DISPATCH_STALL_REORDER_BUF_FULL 0xD5 50 51// Check if SMM came up 52#define EVENT_AMD_SMM_INTERRUPTS 0x2B 53 54// Data Cache Refills from L2 or Northbridge 55#define EVENT_AMD_DATA_CACHE_REFILLS_L2_NB 0x42 56 57#define UMASK_AMD_DATA_CACHE_REFILLS_NB 0x1 58#define UMASK_AMD_DATA_CACHE_REFILLS_L2_SHARED 0x2 59#define UMASK_AMD_DATA_CACHE_REFILLS_L2_EXCLUSIVE 0x4 60#define UMASK_AMD_DATA_CACHE_REFILLS_L2_OWNED 0x8 61#define UMASK_AMD_DATA_CACHE_REFILLS_L2_MODIFIED 0x10 62 63// Data Cache Refills from Northbridge 64#define EVENT_AMD_DATA_CACHE_REFILLS_NB 0x43 65 66// UMASK: See MOESI generic count UMASK_COUNT_* 67 68// Data Cache Lines Evicted 69#define EVENT_AMD_DATA_CACHE_LINES_EVICTED 0x44 70 71// MOESI generic UMASK_COUNT_*, and 72#define UMASK_AMD_DATA_CACHE_EVICTED_PREFETCHNTA 0x20 73#define UMASK_AMD_DATA_CACHE_EVICTED_NO_PREFETCHNTA 0x40 74 75// Misaligned accesses 76#define EVENT_AMD_MISALIGNED_ACCESSES 0x47 77 78// DCACHE misses by locked instructions 79#define EVENT_AMD_DCACHE_MISS_LOCKED 0x4c 80 81#define UMASK_AMD_DCACHE_MISS_LOCKED 0x2 82 83// 3.14.4 L2 Cache and System Interface Events 84 85// Memory requests by type 86#define EVENT_AMD_MEM_REQ_TYPES 0x65 87 88#define UMASK_AMD_MEM_REQ_TYPE_UC 0x1 89#define UMASK_AMD_MEM_REQ_TYPE_WC 0x2 90#define UMASK_AMD_MEM_REQ_TYPE_SS 0x80 91 92// Northbridge read responses by coherency state 93#define EVENT_AMD_NB_RESPONSE_STATE 0x6c 94 95#define UMASK_AMD_NB_RESPONSE_STATE_EXCLUSIVE 0x1 96#define UMASK_AMD_NB_RESPONSE_STATE_MODIFIED 0x2 97#define UMASK_AMD_NB_RESPONSE_STATE_SHARED 0x4 98#define UMASK_AMD_NB_RESPONSE_STATE_DATA_ERROR 0x10 99 100// Octwords written to system 101#define EVENT_AMD_OCTWORDS_TO_SYSTEM 0x6d 102 103#define UMASK_AMD_OCTWORDS_WRITE_TRANSFER 0x1 104 105// Requests to L2 Cache 106#define EVENT_AMD_L2_REQUESTS 0x7d 107 108#define UMASK_AMD_L2_REQUEST_IC_FILL 0x1 109#define UMASK_AMD_L2_REQUEST_DC_FILL 0x2 110#define UMASK_AMD_L2_REQUEST_TLB_FILL 0x4 111#define UMASK_AMD_L2_REQUEST_TAG_SNOOP 0x8 112#define UMASK_AMD_L2_REQUEST_CANCELLED 0x10 113#define UMASK_AMD_L2_REQUEST_HW_PREFETCH_DC 0x20 114 115// L2 Cache Misses 116#define EVENT_AMD_L2_CACHE_MISSES 0x7e 117 118#define UMASK_AMD_L2_CACHE_MISS_IC_FILL 0x1 119#define UMASK_AMD_L2_CACHE_MISS_DC_FILL 0x2 120#define UMASK_AMD_L2_CACHE_MISS_TLB_PAGE_TABLE_WALK 0x4 121#define UMASK_AMD_L2_CACHE_MISS_HW_PREFETCH_DC 0x8 122 123// L2 Fill/Writeback 124#define EVENT_AMD_L2_FILL_WRITEBACK 0x7f 125 126#define UMASK_AMD_L2_FILL_WRITEBACK_FILLS 0x1 127#define UMASK_AMD_L2_FILL_WRITEBACK_WRITEBACKS 0x2 128 129// Instruction Cache Events 130#define EVENT_AMD_INSTRUCTION_CACHE_MISSES 0x81 131 132// 3.14.7 Memory Controller Events 133 134// CPU/IO Requests to Memory/IO 135// Cache Block Commands 136// Probe Responses and Upstream Requests 137// Memory Controller Requests 138 139// 3.14.8 Crossbar Events 140 141// CPU to DRAM Requests to Target Node 142// CPU Read Command Latency to Target Node 0-3 143// CPU Read Command Requests to Target Node 0-3 144// CPU Read Command Latency to Target Node 4-7 145// CPU Read Command Requests to Target Node 4-7 146// CPU Command Latency to Target Node 0-3/4-7 147// CPU Requests to Target Node 0-3/4-7 148 149// 3.14.9 Link Events 150 151#define EVENT_AMD_HYPERTRANSPORT_LINK0_BANDWIDTH 0xf6 152#define EVENT_AMD_HYPERTRANSPORT_LINK1_BANDWIDTH 0xf7 153#define EVENT_AMD_HYPERTRANSPORT_LINK2_BANDWIDTH 0xf8 154#define EVENT_AMD_HYPERTRANSPORT_LINK3_BANDWIDTH 0x1f9 155 156// HyperTransport Link 0 Transmit Bandwidth 157// HyperTransport Link 1 Transmit Bandwidth 158// HyperTransport Link 2 Transmit Bandwidth 159// HyperTransport Link 3 Transmit Bandwidth 160 161// 3.14.10 L3 Cache Events 162 163// Read Request to L3 Cache 164 165// L3 Cache Misses 166#define EVENT_AMD_L3_CACHE_MISSES 0x4e1 167 168#define UMASK_AMD_L3_MISSES_READ_BLOCK_EXCLUSIVE 0x1 169#define UMASK_AMD_L3_MISSES_READ_BLOCK_SHARED 0x2 170#define UMASK_AMD_L3_MISSES_READ_BLOCK_MODIFY 0x4 171#define UMASK_AMD_L3_MISSES_ALL 0x7 172// See UMASK_AMD_CORE_*_SELECT for core select 173 174// L3 Fills caused by L2 evictions 175#define EVENT_AMD_L3_FILLS_L2_EVICT 0x4e2 176 177#define UMASK_AMD_L3_FILLS_L2_EVICT_SHARED 0x1 178#define UMASK_AMD_L3_FILLS_L2_EVICT_EXCLUSIVE 0x2 179#define UMASK_AMD_L3_FILLS_L2_EVICT_OWNED 0x4 180#define UMASK_AMD_L3_FILLS_L2_EVICT_MODIFIED 0x8 181// See UMASK_AMD_CORE_*_SELECT for core select 182 183// L3 Evictions 184#define EVENT_AMD_L3_EVICTIONS 0x4e3 185 186#define UMASK_AMD_L3_EVICTIONS_SHARED 0x1 187#define UMASK_AMD_L3_EVICTIONS_EXCLUSIVE 0x2 188#define UMASK_AMD_L3_EVICTIONS_OWNED 0x4 189#define UMASK_AMD_L3_EVICTIONS_MODIFIED 0x8 190 191// HyperTransport 192 193#define EVENT_AMD_HYPERTRANSPORT_LINK0_BANDWIDTH 0xf6 194#define EVENT_AMD_HYPERTRANSPORT_LINK1_BANDWIDTH 0xf7 195#define EVENT_AMD_HYPERTRANSPORT_LINK2_BANDWIDTH 0xf8 196 197/////////////////////////////////////////////////////////////// 198 199// Generic UMASKs 200#define UMASK_ALL_CORES (3 << 6) 201#define UMASK_THIS_CORE (1 << 6) 202 203#define UMASK_ALL_AGENTS (1 << 5) 204 205#define UMASK_ALL_INCLUSIVE (3 << 4) 206#define UMASK_PREFETCH_ONLY (1 << 4) 207#define UMASK_NO_PREFETCH (0 << 4) 208 209// Generic UMASK for MOESI counts 210#define UMASK_COUNT_MODIFIED 0x10 211#define UMASK_COUNT_OWNED 0x8 212#define UMASK_COUNT_EXCLUSIVE 0x4 213#define UMASK_COUNT_SHARED 0x2 214#define UMASK_COUNT_INVALID 0x1 215#define UMASK_COUNT_ALL (UMASK_COUNT_INVALID | UMASK_COUNT_SHARED | \ 216 UMASK_COUNT_EXCLUSIVE | UMASK_COUNT_OWNED | \ 217 UMASK_COUNT_MODIFIED) 218 219// Generic UMASK for core select 220#define UMASK_AMD_CORE_0_SELECT 0x10 221#define UMASK_AMD_CORE_1_SELECT 0x20 222#define UMASK_AMD_CORE_2_SELECT 0x40 223#define UMASK_AMD_CORE_3_SELECT 0x80 224 225#define UMASK_AMD_L2_MISSES 0x1 226 227#endif 228