1/**
2 * \file
3 * \brief
4 */
5
6/*
7 * Copyright (c) 2010, ETH Zurich.
8 * Copyright (c) 2015, Hewlett Packard Enterprise Development LP.
9 * All rights reserved.
10 *
11 * This file is distributed under the terms in the attached LICENSE file.
12 * If you do not find this file, copies can be found by writing to:
13 * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group.
14 */
15
16#ifndef ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
17#define ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
18
19#include <barrelfish_kpi/asm_inlines_arch.h>
20
21typedef volatile uint32_t spinlock_t;
22
23// Refer to ARM Manual - Load-Acquire Exclusive, Store-Release Exclusive and barriers
24static inline void acquire_spinlock(spinlock_t *spinlock)
25{
26    unsigned long tmp;
27
28	__asm volatile(
29			"	sevl\n"
30			"   prfm pstl1keep, %1\n"
31			"1:	wfe\n"
32			"	ldaxr	%w0, %1\n"
33			"	cbnz	%w0, 1b\n"
34			"	stxr	%w0, %w2, %1\n"
35			"	cbnz	%w0, 1b\n"
36			: "=&r" (tmp), "+Q" (*spinlock)
37			: "r" (1)
38			: "memory");
39
40    dmb();
41}
42
43static inline void release_spinlock(spinlock_t *spinlock)
44{
45    dmb();
46
47	__asm volatile(
48			"	stlr	%w1, %0\n"
49			: "=Q" (*spinlock) : "r" (0) : "memory");
50}
51
52#endif // ARCH_AARCH64_BARRELFISH_KPI_SPINLOCKS_H
53