1/* 2 * Copyright (c) 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * e1000.dev 11 * 12 * DESCRIPTION: Intel e1000 family Gigabit Ethernet NICs 13 * 14 * Numbers in comments refer to the Intel PCIe GbE Controllers Open 15 * Source Software Development Manual, 631xESB / 632xESB, 82563EB / 16 * 82564EB, 82571EB / 82572EI & 82573E / 82573V / 82573L. 17 * 316080-003, Revison 1.2, September 2007 18 */ 19 20device e1000 lsbfirst ( addr base ) "Intel e1000 Gigabit Ethernet" { 21 22 /************************************ 23 * General registers 24 ***********************************/ 25 26 // 13.3.1 27 constants linkspeed "Link speed" { 28 mb10 = 0b00 "10Mb/s"; 29 mb100 = 0b01 "100Mb/s"; 30 mb1000 = 0b10 "1Gb/s"; 31 mb_notused = 0b11 "1Gb/s"; 32 }; 33 34 register ctrl rw addr(base, 0x0000) "Device control" { 35 fd 1 "full-duplex"; 36 _ 1 mbz; 37 gio_md 1 "GIO master disable"; 38 lrst 1 "Link reset"; 39 _ 1 mbz; 40 asde 1 "Auto-Speed Detection Enable"; 41 slu 1 "Set link up"; 42 ilos 1 "Invert Loss-of-Signal (LOS)"; 43 speed 2 type(linkspeed) "Speed selection"; 44 _ 1 mbz; 45 frcspd 1 "Force speed"; 46 frcdplx 1 "Force duplex"; 47 _ 5 mbz; 48 sdp0_data 1 "SDP0 data value, or dock/undock status"; 49 sdp1_data 1 "SDP1 data value"; 50 advd3wuc 1 "D3cold wakeup capability"; 51 en_phy_pwr_mgmt 1 "PHY Power-Management Enable"; 52 sdp0_iodir 1 "SDP0 pin I/O directionality"; 53 sdp1_iodir 1 "SDP1 pin I/O directionality"; 54 _ 2 mbz; 55 rst 1 "Device reset"; 56 rfce 1 "Receive flow control enable"; 57 tfce 1 "Transmit flow control enable"; 58 _ 1 mbz; 59 vme 1 "VLAN mode enable"; 60 phy_rst 1 "PHY reset"; 61 }; 62 63 // 82546 rev 3 64 register ctrldup rw addr(base, 0x0004) "Device Control Duplicate (Shadow)" { 65 fd 1 "full-duplex"; 66 _ 1 mbz; 67 gio_md 1 "GIO master disable"; 68 lrst 1 "Link reset"; 69 _ 1 mbz; 70 asde 1 "Auto-Speed Detection Enable"; 71 slu 1 "Set link up"; 72 ilos 1 "Invert Loss-of-Signal (LOS)"; 73 speed 2 type(linkspeed) "Speed selection"; 74 _ 1 mbz; 75 frcspd 1 "Force speed"; 76 frcdplx 1 "Force duplex"; 77 _ 5 mbz; 78 sdp0_data 1 "SDP0 data value, or dock/undock status"; 79 sdp1_data 1 "SDP1 data value"; 80 advd3wuc 1 "D3cold wakeup capability"; 81 en_phy_pwr_mgmt 1 "PHY Power-Management Enable"; 82 sdp0_iodir 1 "SDP0 pin I/O directionality"; 83 sdp1_iodir 1 "SDP1 pin I/O directionality"; 84 _ 2 mbz; 85 rst 1 "Device reset"; 86 rfce 1 "Receive flow control enable"; 87 tfce 1 "Transmit flow control enable"; 88 _ 1 mbz; 89 vme 1 "VLAN mode enable"; 90 phy_rst 1 "PHY reset"; 91 }; 92 93 constants lanid "LAN ID" { 94 lan_a = 0b00 "LAN A"; 95 lan_b = 0b01 "LAN B"; 96 lan_not_u1 = 0b10 "LAN ID not used"; 97 lan_not_u2 = 0b11 "LAN ID not used"; 98 }; 99 constants mac_mask "LAN MAC MASK" { 100 lan_b_mask = 0x0100 "LAN B mask"; 101 }; 102 103 // 13.3.2 104 register status ro addr(base, 0x0008) "Device status" { 105 fd 1 "Link full duplex configuration"; 106 lu 1 "Link up"; 107 func_id 2 "Function ID"; 108 txoff 1 "Transmission paused"; 109 tbimode 1 "TBI mode"; 110 speed 2 type(linkspeed) "Link speed setting"; 111 asdv 2 type(linkspeed) "Auto speed detection value"; 112 phyra 1 "PHY reset asserted"; 113 pci66 1 "PCI Bus speed indication"; 114 bus64 1 "PCI Bus Width indication"; 115 pcix_mode 1 "PCI-X Mode indication"; 116 pcixspd 2 "PCI-X Bus Speed Indication"; 117 _ 3 mbz; 118 gio_mes 1 "GIO master enable status"; 119 _ 12 mbz; 120 }; 121 122 // 13.3.3 123 constants flashenable "Flash write enable control" { 124 flash_erase = 0b00 "Flash erase"; 125 flash_wr_disable = 0b01 "Flash writes discarded"; 126 flash_wr_enable = 0b10 "Flash writed enabled"; 127 }; 128 129 constants eeaddrsize "EEPROM address size" { 130 bits8or9 = 0 "8- and 9-bit"; 131 bits16 = 1 "16-bit"; 132 }; 133 134 constants nvmtype "Non-volatile memory type" { 135 eeprom = 0b00 "EEPROM"; 136 saflash = 0b01 "Stand-alone Flash"; 137 spiflash = 0b10 "Shared SPI Flash"; 138 sio = 0b11 "SIO"; 139 }; 140 141 register eecd rw addr(base, 0x0010) "EEPROM/Flash control" { 142 ee_sk 1 "Clock input to EEPROM"; 143 ee_cs 1 "Chip select to EEPROM"; 144 ee_di 1 "Data input to EEPROM"; 145 ee_do 1 "Data output bit from EEPROM"; 146 fwe 2 type(flashenable) "Flash write enable control"; 147 ee_req 1 "Request EEPROM access"; 148 ee_gnt 1 "Grant EEPROM access"; 149 ee_pres 1 "EEPROM present"; 150 ee_size_n 1 "EEPROM size for NM93C46 compatible EEPROM" ; 151 ee_size_m 1 "EEPROM size for Microwire EEPROMs"; 152 _ 2 mbz; 153 ee_type 1 "EEPROM Type. (82541xx and 82547GI/EI)"; 154 _ 18 mbz; 155 }; 156 157 // 13.3.4 158 // NM93C46 compatible EEPROMs 159 register eerd_nm rw addr(base, 0x0014) "EEPROM read" { 160 start 1 "Start read"; 161 _ 3 mbz; 162 done 1 ro "Read done"; 163 _ 3 mbz; 164 addr 8 "Read address"; 165 data 16 "Read data"; 166 }; 167 168 register eerd_ms rw also addr(base, 0x0014) "EEPROM read 82541xx and 82547GI/EI" { 169 start 1 "Start read"; 170 done 1 ro "Read done"; 171 addr 14 "Read address"; 172 data 16 "Read data"; 173 }; 174 175 176 // 13.3.5 177 constants linkmode "Link mode" { 178 glci = 0b00 "Direct coper or GLCI"; 179 l82573 = 0b10 "Must be set for 82573E/V/L"; 180 serdes = 0b11 "Internal SerDes (TBI) or SerDes mode"; 181 }; 182 register ctrlext rw addr(base, 0x0018) "Extended device control" { 183 _ 2 mbz; 184 sdp2_gpien 1 "General-purpose interrupt detection for SDP2"; 185 sdp3_gpien 1 "General-purpose interrupt detection for SDP3"; 186 _ 2; 187 sdp2_data 1 "SDP2 data value"; 188 sdp3_data 1 "SDP3 data value"; 189 _ 2 mbz; 190 sdp2_iodir 1 "SDP2 pin directionality"; 191 sdp3_iodir 1 "SDP3 pin directionality"; 192 asdchk 1 "Auto-speed-detection check"; 193 ee_rst 1 "EEPROM reset"; 194 _ 1 mbz; 195 spd_byps 1 "Speed select bypass"; 196 _ 1; 197 rodis 1 "Relaxed ordering disabled"; 198 serdeslpe 1 "SERDES low power enable"; 199 dmadge 1 "DMA dynamic gating enable"; 200 phypde 1 "PHY power down enable"; 201 _ 1; 202 link_mode 2 type(linkmode) "Link mode"; 203 pb_paren 1 "Packet buffer parity error detection enable"; 204 df_paren 1 "Descriptor FIFO parity error detection enable"; 205 _ 1 mbz; 206 iame 1 "Interrupt acknowledge auto-mask enable"; 207 drv_load 1 "Driver loaded"; 208 int_tca 1 "Timers clear enable"; 209 host_paren 1 "Host data FIFO parity enable"; 210 _ 1; 211 }; 212 213 // 13.3.6 214 register fla rw addr(base, 0x001c) "Flash access" { 215 fl_sk 1 "Clock input to Flash"; 216 fl_ce 1 "Chip select to Flash"; 217 fl_si 1 "Data input to Flash"; 218 fl_so 1 "Data output bit from Flash"; 219 fl_req 1 "Request Flash access"; 220 fl_gnt 1 "Grant Flash access"; 221 fl_addr_sz 1 "Flash address size"; 222 _ 2; 223 sw_wr_done 1 "Last write done"; 224 rd_status 1 "Flash status"; 225 _ 5; 226 ide_bo 14 "Base address of IDE Boot expansion ROM"; 227 fl_busy 1 "Flash busy"; 228 fl_er 1 "Flash erase command"; 229 }; 230 231 // 13.3.7 232 constants phyop "PHY register opcode" { 233 mdi_write = 0b01 "MDI Write"; 234 mdi_read = 0b10 "MDI Read"; 235 }; 236 register mdic rw addr(base, 0x0020) "MDI control" { 237 data 16 "Data"; 238 regadd 5 "PHY register address"; 239 phyadd 5 "PHY address"; 240 op 2 type(phyop) "Opcode"; 241 r 1 "Ready bit"; 242 i 1 "Interript enable"; 243 e 1 "Error"; 244 _ 1 mbz; 245 }; 246 247 // 13.3.8 248 // There are a lot of PHY registers, all accessed through the MDIC. 249 // We don't yet list them here. 250 251 // 13.3.10 252 register serdesctl rw addr(base, 0x0024) "SERDES ANA" { 253 data 8 "Data to SerDes"; 254 addr 8 "Address to SerDes"; 255 _ 15; 256 done 1 "Done"; 257 }; 258 259 // 13.3.11-12 260 constants fca "Flow control address" { 261 fca_lo = 0x0c28001; 262 fca_hi = 0x0000100; 263 }; 264 register fcal rw addr(base, 0x0028) "Flow control address low" type(uint32); 265 register fcah rw addr(base, 0x002C) "Flow control address low" type(uint32); 266 267 // 13.3.13 268 constants fctval "Flow control type" { 269 fct_val = 0x0008808; 270 }; 271 register fct rw addr(base, 0x0030) "Flow control type" type(uint32); 272 273 // 13.3.14 274 register kumctrlsta rw addr(base, 0x0034) "GLCI control and status" { 275 data 16 "Data"; 276 offset 5 "Offset of internal register"; 277 ren 1 "Read enable (1=read)"; 278 _ 10; 279 }; 280 281 // 13.3.15 282 constants vet_val "VLAN ether type value" { 283 vlan_type = 0x0008100; 284 }; 285 register vet rw addr(base, 0x0038) "VLAN Ether type" type(uint32); 286 287 // 13.3.16 288 register mdphya rw addr(base, 0x003c) "MDC/MDIO PHY address" { 289 phya 5 "PHY address"; 290 _ 27; 291 }; 292 293 // 13.3.17 294 register ufuse3 ro addr(base, 0x00f0) "ULT Fuse register 3" { 295 drred 15 "Data RAM redundancy fuses"; 296 crred 13 "Code RAM redundancy fuses"; 297 enad 1 "Enable Data RAM redundancy fuses"; 298 enac 1 "Enable Code RAM redundancy fuses"; 299 _ 2; 300 }; 301 302 // 13.3.18 303 register fcttv rw addr(base, 0x0170) "Flow control transmit timer value" { 304 ttv 16 "Transmit timer value"; 305 _ 16 mbz; 306 }; 307 308 // 13.3.19 309 register txcw rw addr(base, 0x0178) "Transmit config word" { 310 _ 5 mbz; 311 txcw_fd 1 "TXCW full-duplex"; 312 txcw_hd 1 "TXCW half-duplex"; 313 txcw_pause 2 "TXCW pause"; 314 _ 3 mbz; 315 txcw_rfi 2 "TXCW remote fault indication"; 316 _ 1 mbz; 317 txcw_npr 1 "TXCW next page request"; 318 _ 14 mbz; 319 txconfig 1 "Transmit config control bit"; 320 ane 1 "Auto-negotiation enable"; 321 }; 322 323 // 13.3.20 324 register rxcw ro addr(base, 0x0180) "Receive config word" { 325 _ 5 mbz; 326 rxcw_fd 1 "RXCW full-duplex"; 327 rxcw_hd 1 "RXCW half-duplex"; 328 rxcw_pause 2 "RXCW pause"; 329 _ 3 mbz; 330 rxcw_rfi 2 "RXCW remote fault indication"; 331 _ 1 mbz; 332 rxcw_npr 1 "RXCW next page request"; 333 _ 10 mbz; 334 nc 1 "Carrier sense indicator"; 335 inv 1 "Invalid symbol during config process"; 336 chg 1 "Change to RXCW indication"; 337 rxconfig 1 "Reception indication"; 338 sync 1 "Lost bit sync indication"; 339 anc 1 "Auto-negotiation complete"; 340 }; 341 342 // 13.3.21 343 constants ledmode "LED output mode" { 344 link_10_100 = 0b0000 "Either 10 or 100 Mbs link established"; 345 link_100_1000 = 0b0001 "Either 100 or 1000 Mbs link established"; 346 link_up = 0b0010 "Any speed link established"; 347 filter_activity = 0b0011 "Packets passing MAC filtering"; 348 link_activity = 0b0100 "No transmit or receive activity"; 349 link_10 = 0b0101 "10 Mbs link established"; 350 link_100 = 0b0110 "100 Mbs link established"; 351 link_1000 = 0b0111 "1000 Mbs link established"; 352 full_duplex = 0b1001 "Link configured for full-duplex"; 353 collision = 0b1010 "Collision is observed"; 354 activity = 0b1011 "Link established and packets sent or revd"; 355 bus_size = 0b1100 "Controller detects 1 PCIe lane conn."; 356 paused = 0b1101 "Transmitter is flow controlled"; 357 led_on = 0b1110 "Always on"; 358 led_off = 0b1111 "Always off"; 359 }; 360 constants blmode "LED blink mode" { 361 ms200 = 0 "200ms on, 200ms off"; 362 ms83 = 1 "83ms on, 83 ms off"; 363 }; 364 register ledctl rw addr(base, 0x0e00) "LED control" { 365 led0_mode 4 type(ledmode) "LED0/LINK# mode"; 366 _ 1 mbz; 367 global_blink_mode 1 type(blmode) "Global blink mode"; 368 led0_ivrt 1 "LED0 invert"; 369 led0_blink 1 "LED0 blink"; 370 371 led1_mode 4 type(ledmode) "LED1/LINK# mode"; 372 _ 1 mbz; 373 led1_blink_mode 1 type(blmode) "Global blink mode"; 374 led1_ivrt 1 "LED1 invert"; 375 led1_blink 1 "LED1 blink"; 376 377 led2_mode 4 type(ledmode) "LED2/LINK# mode"; 378 _ 1 mbz; 379 led2_blink_mode 1 type(blmode) "Global blink mode"; 380 led2_ivrt 1 "LED2 invert"; 381 led2_blink 1 "LED2 blink"; 382 383 led3_mode 4 type(ledmode) "LED3/LINK# mode"; 384 _ 1 mbz; 385 led3_blink_mode 1 type(blmode) "Global blink mode"; 386 led3_ivrt 1 "LED3 invert"; 387 led3_blink 1 "LED3 blink"; 388 }; 389 390 // 13.3.22 391 register extcnf_ctrl rw addr(base, 0x0f00) "Extended config control" { 392 _ 1 mbz; 393 phy_we 1 "PHY write enable"; 394 dud_en 1 "Extended dock/undock configuration enable"; 395 _ 1; 396 dock_own 1 "Dock config owner"; 397 mdio_swown 1 "MDIO software ownership"; 398 mdio_hwown 1 "MDIO hoftware ownership"; 399 _ 9; 400 ecp 12 "Extended configuration pointer"; 401 _ 4; 402 }; 403 404 // 13.3.23 405 register extcnf_size rw addr(base, 0x0f08) "Extended config size" { 406 phy_len 8 "Extended PHY configuration area length"; 407 dock_len 8 "Extended dock configuration area length"; 408 _ 8 mbz; 409 _ 8; 410 }; 411 412 // 13.3.24 413 register pba rw addr(base, 0x1000) "Packet buffer allocation" { 414 rxa 16 "Rx packet buffer allocation in KB"; 415 txa 16 "Tx packet buffer allocation in KB"; 416 }; 417 418 // 13.3.25 419 register eemngctl rw addr(base, 0x1010) "MNG EEPROM control" { 420 _ 18; 421 crg_done 1 "MNG configuration cycle done"; 422 _ 13; 423 }; 424 425 // 13.3.26 426 register sw_fw_sync rw addr(base, 0x5b5c) "Software/firmware sync" { 427 sw_eep_sm 1 "EEPROM access owned by software"; 428 sw_phy_sm0 1 "PHY 0 access owned by software"; 429 sw_phy_sm1 1 "PHY 1 access owned by software"; 430 sw_mac_csr_sm 1 "Shared CSR access owned by software"; 431 _ 12; 432 fw_eep_sm 1 "EEPROM access owned by firmware"; 433 fw_phy_sm0 1 "PHY 0 access owned by firmware"; 434 fw_phy_sm1 1 "PHY 1 access owned by firmware"; 435 fw_mac_csr_sm 1 "Shared CSR access owned by firmware"; 436 _ 12; 437 }; 438 439 /************************************ 440 * Interrupt registers 441 ***********************************/ 442 443 // 13.3.27 444 regtype intreg "Interrupt register format" { 445 txdw 1 "Transmit descriptor written back"; 446 txqe 1 "Transmit queue empty"; 447 lsc 1 "Link status change"; 448 rxseq 1 "Receive sequence error"; 449 rxdmt0 1 "Receive descriptor minimum threshold reached"; 450 _ 1; 451 rxo 1 "Receiver overrun"; 452 rxt0 1 "Receiver timer interrupt"; 453 _ 1; 454 mdac 1 "MDI/O access complete"; 455 rxcfg 1 "Received configuration symbols"; 456 _ 2; 457 gpi_sdp2 1 "General-purpose interrupt on SPD2"; 458 gpi_sdp3 1 "General-purpose interrupt on SPD3"; 459 txd_low 1 "Transmit descriptor low threshold"; 460 srpd 1 "Small receive packet detected"; 461 ack 1 "Receive ack frame detected"; 462 _ 2; 463 rx_desc_fifo_par0 1 "Rx descriptor FIFO parity error 0"; 464 tx_desc_fifo_par0 1 "Tx descriptor FIFO parity error 0"; 465 pcie_master_par 1 "PCIe master data FIFO parity error"; 466 pbpar 1 "Packet buffer parity error"; 467 rx_desc_fifo_par1 1 "Rx descriptor FIFO parity error 1"; 468 tx_desc_fifo_par1 1 "Tx descriptor FIFO parity error 1"; 469 _ 5; 470 int_asserted 1 "Interrupt asserted"; 471 }; 472 473 // 13.3.27 474 register icr ro addr(base, 0x00c0) "Interrupt cause read" type(intreg); 475 476 // 13.3.28 477 register itr rw addr(base, 0x00c4) "Interrupt throttling rate" { 478 interval 16 "Minimum inter-interrupt interval (x256ns)"; 479 _ 16 mbz; 480 }; 481 482 // 13.3.29 483 register ics wo addr(base, 0x00c8) "Interrupt cause write" type(intreg); 484 485 // 13.3.30 486 register ims rw addr(base, 0x00d0) "Interrupt mask set/read" type(intreg); 487 488 // 13.3.31 489 register imc wo addr(base, 0x00d8) "Interrupt mask clear" type(intreg); 490 491 // 13.3.32 492 register iam rw addr(base, 0x00e0) "Interrupt ack auto mask" type(intreg); 493 494 regarray eitr addr(base, 0x1680)[9;0x4] "Extended Interrupt Throttle" { 495 _ 2 mbz; 496 interval 13 "Interval"; 497 _ 1 mbz; 498 counter 16 "Down counter"; 499 }; 500 501 /************************************ 502 * Receive registers 503 ***********************************/ 504 505 // 13.3.33 506 constants lbmode "Loopback mode" { 507 lb_normal = 0b00 "Normal operation"; 508 lb_mac = 0b01 "MAC loopback"; 509 }; 510 constants rxthresh "Received desc. threshold size" { 511 rdlen_2 = 0b00 "1/2 RDLEN"; 512 rdlen_4 = 0b01 "1/4 RDLEN"; 513 rdlen_8 = 0b10 "1/8 RDLEN"; 514 }; 515 constants dtype "Descriptor type" { 516 dt_legacy = 0b00 "Legacy descriptor type"; 517 dt_split = 0b01 "Packet split descriptor type"; 518 }; 519 constants rxbsize "Receive buffer size" { 520 rxb2048 = 0b00 "2048 bytes"; 521 rxb1024 = 0b01 "1024 or 16384 bytes"; 522 rxb512 = 0b10 "512 or 8192 bytes"; 523 rxb256 = 0b11 "256 or 4096 bytes"; 524 }; 525 register rctl rw addr(base, 0x0100) "Receive control" { 526 _ 1 mbz; 527 en 1 "Receiver enable"; 528 sbp 1 "Store bad packets"; 529 upe 1 "Unicast promiscuous enabled"; 530 mpe 1 "Multicast promiscuous enabled"; 531 lpe 1 "Long packet reception enable"; 532 lbm 2 type(lbmode) "Loopback mode"; 533 rdmts 2 type(rxthresh) "Receive descriptor minimum threshold size"; 534 dtyp 2 type(dtype) "Descriptor type"; 535 mo 2 "Multicast offset (12 bits starting at 36-val)"; 536 _ 1 mbz; 537 bam 1 "Broadcast accept mode"; 538 bsize 2 type(rxbsize) "Receive buffer size (see BSEX)"; 539 vfe 1 "VLAN filter enable"; 540 cfien 1 "Canonical form indicator enable"; 541 cfi 1 "Canonical form indicator value"; 542 _ 1 mbz; 543 dpf 1 "Discard pause frames"; 544 pmcf 1 "Pass MAC control frames"; 545 _ 1 mbz; 546 bsex 1 "Buffer size extension"; 547 secrc 1 "Strip Ethernet CRC from packet"; 548 flxbuf 4 "Flexible buffer size (in KB)"; 549 _ 1 mbz; 550 }; 551 552 // 13.3.34 553 register ert rw addr(base, 0x2008) "Early receive threshold" { 554 rxthresh 13 "Receive threshold value (x 8 bytes)"; 555 _ 1; 556 _ 18 mbz; 557 }; 558 559 // 13.3.35 560 register fcrtl rw addr(base, 0x2160) "Flow control rx threshold low" { 561 _ 3 mbz; 562 rtl 13 "Recieve threshold low"; 563 _ 15 mbz; 564 xone 1 "XON enable"; 565 }; 566 567 // 13.3.36 568 register fcrth rw addr(base, 0x2168) "Flow control rx threshold high" { 569 _ 3 mbz; 570 rth 13 "Recieve threshold high"; 571 _ 15 mbz; 572 flowcntdis 1 "Flow control disable"; 573 }; 574 575 // 13.3.37 576 register psrctl rw addr(base, 0x2170) "Packet split rx control" { 577 bsize0 7 "Receive buffer 0 size (x 128 bytes)"; 578 _ 1 mbz; 579 bsize1 7 "Receive buffer 1 size (x 1 kbytes)"; 580 _ 1 mbz; 581 bsize2 7 "Receive buffer 2 size (x 1 kbytes)"; 582 _ 1 mbz; 583 bsize3 7 "Receive buffer 3 size (x 1 kbytes)"; 584 _ 1 mbz; 585 }; 586 587 // 13.3.38/46/39/47 588 regarray rdbal rw addr(base, 0x2800)[2;0x100] 589 "Rx descr. base addr low" type(uint32); 590 regarray rdbah rw addr(base, 0x2804)[2;0x100] 591 "Rx descr. base addr high" type(uint32); 592 593 // 13.3.40/48 and 13.3.62/71 594 // Note that the description of the transmit length (13.3.62/71) refers to 595 // the size of the descriptor buffer in bytes. This is misleading; the whole 596 // register (raw value) refers to that, but the bottom 7 bits must be zero. 597 regtype dqlen "Descriptor length value" { 598 _ 7 mbz; 599 len 13 "Num. descriptors (x8)"; 600 _ 12 mbz; 601 }; 602 regarray rdlen rw addr(base, 0x2808)[2;0x100] 603 "Rx descriptor length" type(dqlen); 604 605 // 13.3.41/49/42/50 606 regtype dqval "Descriptor head/tail value" { 607 val 16 "value"; 608 _ 16 mbz; 609 }; 610 regarray rdh rw addr(base, 0x2810)[2;0x100] "Rx descr. head" type(dqval); 611 regarray rdt rw addr(base, 0x2818)[2;0x100] "Rx descr. tail" type(dqval); 612 613 // 13.3.43 614 register rdtr rw addr(base, 0x2820) "Rx. interrupt delay timer" { 615 delay 16 "delay timer (x 1.024us)"; 616 _ 15 mbz; 617 fpd 1 "Flush partial descriptor block"; 618 }; 619 620 // 13.3.44/51 621 constants threshgran "Threshold granularity" { 622 gran_cache = 0 "Cache line granularity"; 623 gran_desc = 1 "Descriptor granularity"; 624 }; 625 626 regarray rxdctl rw addr(base, 0x2828)[2;0x100] "Rx descriptor control" { 627 pthresh 6 "Prefetch threshold"; 628 _ 2 mbz; 629 hthresh 6 "Host threshold"; 630 _ 2 mbz; 631 wthresh 6 "Write back threshold"; 632 _ 2 mbz; 633 gran 1 type(threshgran) "Granularity"; 634 _ 7 mbz; 635 }; 636 637 regarray rxdctl_82575 rw also addr(base, 0x2828)[2;0x100] "Rx descriptor control" { 638 pthresh 6 "Prefetch threshold"; 639 _ 2 mbz; 640 hthresh 6 "Host threshold"; 641 _ 2 mbz; 642 wthresh 6 "Write back threshold"; 643 _ 3 mbz; 644 enable 1 "Granularity"; 645 swflush 1 "Receive Software Flush"; 646 _ 5 mbz; 647 }; 648 649 // 13.3.45 650 register radv rw addr(base, 0x282c) "Rx absolute intr. delay" { 651 idv 16 "Interrupt delay value"; 652 _ 16 mbz; 653 }; 654 655 // 13.3.52 656 register rsrpd rw addr(base, 0x2c00) "Rx small packet detect interrupt" { 657 size 12 "Max size of small packet"; 658 _ 20 mbz; 659 }; 660 661 // 13.3.53 662 register raid rw addr(base, 0x2c08) "Rx ACK interrupt delay" { 663 idv 16 "Interrupt delay value (x 1.024us)"; 664 _ 16 mbz; 665 }; 666 667 // 13.3.54 668 register cpuvec rw addr(base, 0x2c10) "CPU vector" type(uint32); 669 670 // 13.3.55 671 register rxcsum rw addr(base, 0x5000) "Receive checksum control" { 672 pcss 8 "Packet checksum start"; 673 ipofld 1 "IP checksum offload enable"; 674 tuofld 1 "TCP/UDP checksum offload enable"; 675 _ 22 mbz; 676 }; 677 678 // 13.3.56 679 register rfctl rw addr(base, 0x5008) "Receive filter control" { 680 iscsi_dis 1 "iSCSI filtering disable"; 681 iscsi_dwc 5 "iSCSI dword count"; 682 nfsw_dis 1 "NFS write filtering disable"; 683 nfsr_dis 1 "NFS read filtering disable"; 684 nfs_ver 2 "NFS version (+2)"; 685 ipv6_dis 1 "IPv6 filtering disable"; 686 ipv6xsum_dis 1 "IPv6 xsum disable"; 687 ackdis 1 "ACK accelerator disable"; 688 ackd_dis 1 "ACK data disable"; 689 ipfrsp_dis 1 "IP fragment split disable"; 690 exsten 1 "Extended status enable"; 691 _ 16 mbz; 692 }; 693 694 /************************************ 695 * Transmit registers 696 ***********************************/ 697 698 // 13.3.57 699 constants coldist "Recommended collision distances" { 700 cd_half = 0x200 "512 byte-times"; 701 cd_full = 0x3f "64 byte-times"; 702 cd_esb = 0x40 "64 byte-times (for 631xESB/632xESB)"; 703 }; 704 register tctl rw addr(base, 0x400) "Transmit control" { 705 _ 1 mbz; 706 en 1 "Transmit enable"; 707 _ 1 mbz; 708 psp 1 "Pad short packets"; 709 ct 8 "Collision threshold"; 710 bst 10 "Back-Off Slot time"; 711 swxoff 1 "Software XOFF transmission"; 712 _ 1 mbz; 713 rtlc 1 "Retransmit on late collision"; 714 unortx 1 "Underrun no re-transmit"; 715 txcscmt 2 "Tx descriptor minimum threshold"; 716 mulr 1 "Multiple request support"; 717 _ 3; 718 }; 719 720 // 13.3.58 721 register tctl_ext rw addr(base, 0x0404) "Transmit control extended" { 722 _ 10 mbz; 723 cold 10 type(coldist) "Collision distance"; 724 _ 12; 725 }; 726 727 // 13.3.59 728 register tipg rw addr(base, 0x0410) "Transmit IPQ" { 729 ipgt 10 "IPG back to back (x MAC clock, +4)"; 730 ipgr1 10 "IPG Part 1"; 731 ipgr2 10 "IPG after deferral"; 732 _ 2 mbz; 733 }; 734 735 // 736 // The e1000 has two transmit queues, hence two sets of the 737 // remaining registers 738 // 739 740 // 13.3.60/61/69/70 741 regarray tdbal rw addr(base, 0x3800)[2;0x100] "Tx descr. base addr. low" 742 type(uint32); 743 regarray tdbah rw addr(base, 0x3804)[2;0x100] "Tx descr. base addr. hi" 744 type(uint32); 745 746 // 13.3.62/71 747 regarray tdlen rw addr(base, 0x3808)[2;0x100] "Tx descr. length" type(dqlen); 748 749 // 13.3.63/64/73 750 regarray tdh rw addr(base, 0x3810)[2;0x100] "Tx descr. head" type(dqval); 751 regarray tdt rw addr(base, 0x3818)[2;0x100] "Tx descr. tail" type(dqval); 752 753 // 13.3.65 754 register tidv rw addr(base, 0x3820) "Transmit interrupt delay value" { 755 idv 16 "Interupt delay value"; 756 _ 15 mbz; 757 fdp 1 wo "Flush partial description block"; 758 }; 759 760 // 13.3.66/74 761 regarray txdctl rw addr(base, 0x3828)[2;0x100] "Transmit descr. control queue" { 762 pthresh 6 "Prefetch threshold"; 763 _ 2 mbz; 764 hthresh 8 "Host threshold"; 765 wthresh 6 "Write back threshold"; 766 _ 1 mb1; 767 _ 1; 768 gran 1 type(threshgran) "Granularity"; 769 lwthresh 7 "Transmit descriptor low threshold"; 770 }; 771 772 regarray txdctl_82575 rw also addr(base, 0x3828)[4;0x100] "Transmit descr. control queue for 82575 cards" { 773 pthresh 6 "Prefetch threshold"; 774 _ 2 mbz; 775 hthresh 6 "Host threshold"; 776 _ 2; 777 wthresh 6 "Write back threshold"; 778 _ 3 mb1; 779 enable 1 "Enable the queue"; 780 swflsh 1 "Transmit Software Flush"; 781 priority 1 "Priority"; 782 _ 4; 783 }; 784 785 // 13.3.67 786 register tadv rw addr(base, 0x382c) "Tx absolute intr. delay" { 787 idv 16 "Interrupt delay value"; 788 _ 16 mbz; 789 }; 790 791 // 13.3.68/75 792 regarray tarc rw addr(base, 0x3840)[2;0x100] "Tx arbitration counter" { 793 count 7 "Transmit arbitration count"; 794 _ 1; 795 ratio 2 "Compensation ratio (1 / 2^val)"; 796 enable 1 mb1; 797 _ 10 mbz; 798 _ 1 mb1; 799 _ 1 mbz; 800 _ 4 mb1; 801 _ 5 mbz; 802 }; 803 804 /************************************ 805 * Filter registers 806 ***********************************/ 807 808 // 13.4.1 809 regarray mta rw addr(base, 0x5200)[128] "Multicast table array" type(uint32); 810 811 // 13.4.2 812 regarray ral rw addr(base, 0x5400)[16;8] "Receive address low" type(uint32); 813 814 // 13.4.3 815 constants addrsel "Address select" { 816 as_dest = 0b00 "Destination"; 817 as_src = 0b01 "Source"; 818 }; 819 regarray rah rw addr(base, 0x5404)[16;8] "Receive address high" { 820 rah 16 "Receive address high"; 821 asel 2 type(addrsel) "Address select"; 822 _ 13 mbz; 823 av 1 "Address valid"; 824 }; 825 826 // 13.4.4 827 regarray vfta rw addr(base, 0x5600)[128] 828 "VLAN filter table array" type(uint32); 829 830 // 13.4.5 831 constants mrqen "Multiple rx queue enable" { 832 mrq_dis = 0b00 "Multiple queues disabled"; 833 mrq_rss = 0b01 "Multiple queues enabled by MSFT RSS"; 834 }; 835 register mrq rw addr(base, 0x5818) "Multiple queues receive command" { 836 mrqe 2 type(mrqen) "Multiple rx queues enable"; 837 rssie 1 "RSS interrupt enable"; 838 _ 13 mbz; 839 tcp4 1 "Enable TCP IPv4 hash"; 840 ipv4 1 "Enable IPv4 hash"; 841 tcp6ex 1 "Enable TCP IPv6 Ex hash"; 842 ipv6ex 1 "Enable IPv6 Ex hash"; 843 ipv6 1 "Enable IPv6 hash"; 844 _ 11; 845 }; 846 847 // 13.4.6 848 register rssim rw addr(base, 0x5864) "RSS interrupt mask" type(uint32); 849 850 // 13.4.7 851 register rssir rw addr(base, 0x5868) "RSS interrupt request" type(uint32); 852 853 // 13.4.8 854 regarray reta rw addr(base, 0x5c00)[128] "Redirection table" type(uint8); 855 856 // 13.4.9 857 regarray rssrk rw addr(base, 0x5c80)[40] "RSS Random key" type(uint8); 858 859 /************************************ 860 * Wakeup registers 861 ***********************************/ 862 863 // 13.5.1 864 register wuc rw addr(base, 0x5800) "Wakeup control" { 865 apme 1 "Advanced power mgmt enable"; 866 pme_en 1 "PME enable"; 867 pme_stat 1 "PME status"; 868 apmpme 1 "Assert PME on APM wakeup"; 869 _ 28; 870 }; 871 872 // 13.5.2 873 regtype wakeup "Wakeup register" { 874 lnkc 1 "Link status change"; 875 mag 1 "Magic packet"; 876 ex 1 "Directed exact"; 877 mc 1 "Directed multicast"; 878 bc 1 "Broadcast"; 879 arp 1 "ARP request packet"; 880 ipv4 1 "Directed IPv4"; 881 ipv6 1 "Directed IPv6"; 882 _ 7 mbz; 883 notco 1 "Ignore TCO/management packets"; 884 flx0 1 "Flexible filter 0 enable"; 885 flx1 1 "Flexible filter 1 enable"; 886 flx2 1 "Flexible filter 2 enable"; 887 flx3 1 "Flexible filter 3 enable"; 888 _ 12 mbz; 889 }; 890 register wufc rw addr(base, 0x5808) "Wakeup filter control" type(wakeup); 891 892 // 13.5.3 893 register wus ro addr(base, 0x5810) "Wakeup status" type(wakeup); 894 895 // 13.5.4 896 register ipav rw addr(base, 0x5838) "IP address valid" { 897 v40 1 "IPv4 address 0 valid"; 898 v41 1 "IPv4 address 1 valid"; 899 v42 1 "IPv4 address 2 valid"; 900 v43 1 "IPv4 address 3 valid"; 901 _ 12 mbz; 902 v60 1 "IPv6 address 0 valid"; 903 _ 15 mbz; 904 }; 905 906 // 13.5.5 907 regarray ip4at rw addr(base, 0x5840)[4;8] 908 "IPv4 address table" type(uint32); 909 910 // 13.5.6 911 regarray ip6at rw addr(base, 0x5880)[4] "IPv6 address table" type(uint32); 912 913 // 13.5.7 914 register wupl rw addr(base, 0x5900) "Wakeup packet length" { 915 len 12 "Length"; 916 _ 20 mbz; 917 }; 918 919 // 13.5.8 920 regarray wupm rw addr(base, 0x5a00)[32] "Wakeup packet memory" type(uint32); 921 922 // 13.5.9 923 regarray fflt rw addr(base, 0x5f00)[4;8] "Flexible filter length table" { 924 len 11 "Length"; 925 _ 21 mbz; 926 }; 927 regarray ffltco rw addr(base, 0x5f20)[2;8] "Flexible filter length table" { 928 tcolen 11 "Length"; 929 _ 21 mbz; 930 }; 931 932 // 13.5.10 933 regarray ffmt rw addr(base, 0x9000)[128;8] "Flexible filter mask table" { 934 mask 4 "mask"; 935 _ 28 mbz; 936 }; 937 938 // 13.5.11 939 regarray ffvt rw addr(base, 0x9800)[128;8] "Flexible filter value table" { 940 val0 8 "Value 0"; 941 val1 8 "Value 1"; 942 val2 8 "Value 2"; 943 val3 8 "Value 3"; 944 }; 945 946 /************************************ 947 * Management control registers 948 ***********************************/ 949 950 // 13.6.1 951 register manc rw addr(base, 0x5820) "Management control" { 952 _ 3 mbz; 953 en_flexport0 1 "Enable flex UDP/TCP port 0 filtering"; 954 en_flexport1 1 "Enable flex UDP/TCP port 1 filtering"; 955 en_flexport2 1 "Enable flex UDP/TCP port 2 filtering"; 956 flex_tco1_filter 1 "Enable TCO filter 1"; 957 flex_tco0_filter 1 "Enable TCO filter 0"; 958 rmcp_en 1 "Enable RMCP 0x026f filtering"; 959 o298_en 1 "Enable RMCP 0x0298 filtering"; 960 _ 3 mbz; 961 arp_req_en 1 "Enable ARP request filtering"; 962 neighbor_en 1 "Enable neighbor discovery filtering"; 963 arp_res_en 1 "Enable ARP response filtering"; 964 tco_reset 1 "TCO reset occurred"; 965 rcv_tco_en 1 "Receive TCO packets enable"; 966 blk_phyrst_on_ide 1 "Block PHY reset and power on state changes"; 967 rcv_all 1 "Receive all enable"; 968 en_mac16_filter 1 "Enable MAC address 16 filtering"; 969 en_mng2host 1 "Enable firmware packets to host memory"; 970 en_ip_addrfilter 1 "Enable IP address filtering"; 971 en_xsum_filter 1 "Enable Xsum filtering to firmware"; 972 br_en 1 "Enable broadcast filtering"; 973 _ 7 mbz; 974 }; 975 976 /************************************ 977 * PCIe registers 978 ***********************************/ 979 980 // NOTE: Intel in their infinite wisdom have chosen to list these 981 // registers MSBfirst in the documentation, as opposed to all the 982 // others which are LSBfirst... 983 984 // 13.7.1 985 register gcr rw addr(base, 0x5b00) "PCIe control" { 986 rxd_nosnoop 1 "Receive data write"; 987 rxdscw_nosnoop 1 "Receive descriptor write"; 988 rxdscr_nosnoop 1 "Receive descriptor read"; 989 txd_nosnoop 1 "Transmit data write"; 990 txdscw_nosnoop 1 "Transmit descriptor write"; 991 txdscr_nosnoop 1 "Transmit descriptor read"; 992 elec_idle_in0 1 ro "SerDes0 internal electrical idle indicator"; 993 elec_idle_in1 1 ro "SerDes1 internal electrical idle indicator"; 994 self_test_enable 1 "Perform self test"; 995 _ 12 mbz; 996 logheader 1 "Log header into PCI config space"; 997 _ 1 mbz; 998 l1el_msb 1 ro "L1 Entry latency msb"; 999 l0s_el 1 "L0s entry latency"; 1000 l1el_lsb 2 ro "L1 Entry latency lsbs"; 1001 l1_aw_l0s 1 "L1 act without L0s_rx correlation"; 1002 gio_dis_rderr 1 "Disable running disparity err"; 1003 gio_good_10s 1 "Force good PCIe l0s training"; 1004 self_test_result 1 "Result of self test"; 1005 dis_tmout 1 "Disable PCIe timeout mechanism"; 1006 }; 1007 1008 // 13.7.2 1009 register gscl1 rw addr(base, 0x5b10) "PCIe statistics control 1" { 1010 count_en0 1 "Enable PCIe stats counter 0"; 1011 count_en1 1 "Enable PCIe stats counter 1"; 1012 count_en2 1 "Enable PCIe stats counter 2"; 1013 count_en3 1 "Enable PCIe stats counter 3"; 1014 _ 23; 1015 count_test 1 "Test bit"; 1016 en_64bit 1 "Enable two 64-bit counters instead of 4 32-bit"; 1017 count_reset 1 "Reset indication of PCIe stats"; 1018 count_stop 1 "Stop indication"; 1019 count_start 1 "Start indication"; 1020 }; 1021 1022 // 13.7.3 1023 register gscl2 rw addr(base, 0x5b14) "PCIe statistics control 2" { 1024 event0 8 "Event number that counter 0 counts"; 1025 event1 8 "Event number that counter 1 counts"; 1026 event2 8 "Event number that counter 2 counts"; 1027 event3 8 "Event number that counter 3 counts"; 1028 }; 1029 1030 // 13.7.4 1031 register gscl3 rw addr(base, 0x5b18) "PCIe statistics control 3" { 1032 fc_th0 12 "Threshold of flow control credits 0"; 1033 _ 4; 1034 fc_th1 12 "Threshold of flow control credits 1"; 1035 _ 4; 1036 }; 1037 1038 // 13.7.5 1039 register gscl4 rw addr(base, 0x5b1c) "PCIe statistics control 4" { 1040 coml_th 10 "Completions latency threshold"; 1041 rb_th 6 "Retry buffer threshold"; 1042 _ 16; 1043 }; 1044 1045 // 13.7.6-9 1046 regarray gscn rw addr(base, 0x5b20)[4] "PCIe counter" type(uint32); 1047 1048 // 13.7.10 1049 constants fps "Function power state" { 1050 fps_dr = 0b00 "DR"; 1051 fps_d0u = 0b01 "D0u"; 1052 fps_d0a = 0b10 "Doa"; 1053 fps_d3 = 0b11 "D3"; 1054 }; 1055 register factps ro addr(base, 0x5b30) "Fn. active & power state to MNG" { 1056 f0ps 2 type(fps) "Power state of fn. 0"; 1057 lan0v 1 "LAN 0 valid enable"; 1058 f0aux 1 "Fn. 0 aux power enable shadow"; 1059 lan0en 1 "LAN 0 enabled"; 1060 _ 1; 1061 f1ps 2 type(fps) "Power state of fn. 1"; 1062 lan1v 1 "LAN 1 valid enable"; 1063 f1aux 1 "Fn. 1 aux power enable shadow"; 1064 lan1en 1 "LAN 1 enabled"; 1065 _ 1; 1066 f2ps 2 type(fps) "Power state of fn. 2"; 1067 ide_en 1 "IDE (function 2) enable"; 1068 f2aux 1 "Fn. 2 aux power enable shadow"; 1069 _ 2; 1070 f3ps 2 type(fps) "Power state of fn. 3"; 1071 sp_en 1 "SP (function 3) enable"; 1072 f3aux 1 "Fn. 3 aux power enable shadow"; 1073 _ 2; 1074 f4ps 2 type(fps) "Power state of fn. 4"; 1075 ipmi_en 1 "IPMI (function 4) enable"; 1076 f4aux 1 "Fn. 4 aux power enable shadow"; 1077 _ 1; 1078 mngcg 1 "MNG clock gated"; 1079 lanfs 1 "LAN function select"; 1080 pmchg 1 "PM state changed"; 1081 }; 1082 1083 // 13.7.11-12 1084 regtype anal_ctl "Analog circuit configuration" { 1085 data 8 "Data to SerDes"; 1086 address 8 "Address to SerDes"; 1087 _ 15; 1088 done 1 "Done indicator"; 1089 }; 1090 regarray gioanactl rw addr(base,0x5b34)[4] "Analog control" type(anal_ctl); 1091 1092 // 13.7.13 1093 register gioanactlall rw addr(base,0x5b44) "Analog control" type(anal_ctl); 1094 1095 // 13.7.14 1096 register ccmctl rw addr(base,0x5b48) "CCM analog control" type(anal_ctl); 1097 1098 // 13.7.15 1099 register anactl rw also addr(base,0x5b48) "Analog control" { 1100 data 8 "Data to/from analog register"; 1101 address 8 "Address of analog register"; 1102 _ 14; 1103 write 1 "Read/write command"; 1104 done 1 "Done indication"; 1105 }; 1106 1107 // 13.7.16 1108 register scctl rw addr(base, 0x5b4c) "SCC analog control" type(anal_ctl); 1109 1110 // 13.7.17 1111 register swsm rw addr(base, 0x5b50) "Software semaphore" { 1112 smbi 1 "Semaphore bit"; 1113 swesmbi 1 "Software EEPROM semaphore bit"; 1114 wmng 1 "Wake MNG clock"; 1115 _ 29; 1116 }; 1117 1118 // 13.7.18 1119 constants fwmode "Firmware mode" { 1120 nomng = 0b000 "No MNG"; 1121 ptmode = 0b010 "PT mode"; 1122 hieo = 0b100 "Host interface firmware"; 1123 }; 1124 constants pcierr "PCIe external error indication" { 1125 pe_none = 0x00 "No error"; 1126 pe_mschk = 0x01 "Bad checksum in manageability sections"; 1127 pe_prot = 0x02 "EEPROM protection disabled"; 1128 pe_clkoff = 0x03 "Clock off command executed"; 1129 pe_flchk = 0x04 "Bad checksum in flash header"; 1130 pe_pschk = 0x05 "Bad checksum in patch section"; 1131 pe_lschk = 0x06 "Bad checksum in loader section"; 1132 pe_dschk = 0x07 "Bad checksum in diagnostic section"; 1133 pe_inval = 0x08 "Invalid firmware mode"; 1134 pe_tlbe = 0x09 "TLB table exceeded"; 1135 pe_eerd = 0x0a "EEPROM read failed"; 1136 pe_hwver = 0x0b "Bad hardware version in patch load"; 1137 pe_sfrd = 0x0c "SFlash read failed"; 1138 pe_unspec = 0x0d "Unspecified error"; 1139 pe_auth = 0x0e "Flash authentication failed"; 1140 pe_pfrd = 0x0f "PFlash read failed"; 1141 pe_ifep = 0x10 "Invalid Flash entry point"; 1142 }; 1143 register fwsm rw addr(base, 0x5b54) "Firmware semaphore" { 1144 eep_fw 1 "EEPROM firmware semaphore"; 1145 fw_mode 3 type(fwmode) "Firmware mode"; 1146 ide_on 1 "IDE redirection on"; 1147 sol_on 1 "SOL on"; 1148 eep_rl 1 "EEPROM reloaded indication"; 1149 _ 8; 1150 fwval 1 "Firmware valid bit"; 1151 rstcnt 3 "Reset counter"; 1152 error 6 type(pcierr) "External error indication"; 1153 _ 7; 1154 }; 1155 1156 /************************************ 1157 * Statistics registers 1158 ***********************************/ 1159 1160 // 13.8 ff 1161 register crcerrs rc addr(base, 0x4000) 1162 "CRC error count" type(uint32); 1163 register algnerrc rc addr(base, 0x4004) 1164 "Alignment error count" type(uint32); 1165 register symerrs rc addr(base, 0x4008) 1166 "Symbol error count" type(uint32); 1167 register rxerrc rc addr(base, 0x400c) 1168 "Receive error count" type(uint32); 1169 register mpc rc addr(base, 0x4010) 1170 "Missed packets count" type(uint32); 1171 register scc rc addr(base, 0x4014) 1172 "Single collision count" type(uint32); 1173 register ecol rc addr(base, 0x4018) 1174 "Excessive collisions count" type(uint32); 1175 register mcc rc addr(base, 0x401c) 1176 "Multiple collision count" type(uint32); 1177 register latecol rc addr(base, 0x4020) 1178 "Late collisions count" type(uint32); 1179 register colc rc addr(base, 0x4028) 1180 "Collision count" type(uint32); 1181 register dc rc addr(base, 0x4030) 1182 "Defer count" type(uint32); 1183 register tncrs rc addr(base, 0x4034) 1184 "Transmit with no CRS" type(uint32); 1185 register sec rc addr(base, 0x4038) 1186 "Sequence error count" type(uint32); 1187 register cexterr rc addr(base, 0x403c) 1188 "Carrier extension error count" type(uint32); 1189 register rlec rc addr(base, 0x4040) 1190 "Receive length error count" type(uint32); 1191 register xonrxc rc addr(base, 0x4048) 1192 "XON received count" type(uint32); 1193 register xontxc rc addr(base, 0x404c) 1194 "XON transmitted count" type(uint32); 1195 register xoffrxc rc addr(base, 0x4050) 1196 "XOFF received count" type(uint32); 1197 register xofftxc rc addr(base, 0x4054) 1198 "XOFF transmitted count" type(uint32); 1199 register fcurc rc addr(base, 0x4058) 1200 "FC received unsupported count" type(uint32); 1201 register prc64 rc addr(base, 0x405c) 1202 "Packets received (64 bytes) count" type(uint32); 1203 register prc127 rc addr(base, 0x4060) 1204 "Packets received (65-127 bytes) count" type(uint32); 1205 register prc255 rc addr(base, 0x4064) 1206 "Packets received (128-255 bytes) count" type(uint32); 1207 register prc511 rc addr(base, 0x4068) 1208 "Packets received (256-511 bytes) count" type(uint32); 1209 register prc1023 rc addr(base, 0x406c) 1210 "Packets received (512-1023 bytes) count" type(uint32); 1211 register prc1522 rc addr(base, 0x4070) 1212 "Packets received (1024-max bytes) count" type(uint32); 1213 register gprc rc addr(base, 0x4074) 1214 "Good packets received count" type(uint32); 1215 register bprc rc addr(base, 0x4078) 1216 "Broadcast packets received count" type(uint32); 1217 register mcprc rc addr(base, 0x407c) 1218 "Multicast packets received count" type(uint32); 1219 register gptc rc addr(base, 0x4080) 1220 "Good packets transmitted count" type(uint32); 1221 register gorcl rc addr(base, 0x4088) 1222 "Good octets received count low" type(uint32); 1223 register gorch rc addr(base, 0x408c) 1224 "Good octets received count high" type(uint32); 1225 register gotcl rc addr(base, 0x4090) 1226 "Good octets transmitted count low" type(uint32); 1227 register gotch rc addr(base, 0x4094) 1228 "Good octets transmitted count high" type(uint32); 1229 register rnbc rc addr(base, 0x40a0) 1230 "Receive no buffers count" type(uint32); 1231 register ruc rc addr(base, 0x40a4) 1232 "Receive undersize count" type(uint32); 1233 register rfc rc addr(base, 0x40a8) 1234 "Receive fragment count" type(uint32); 1235 register roc rc addr(base, 0x40ac) 1236 "Receive oversize count" type(uint32); 1237 register rjc rc addr(base, 0x40b0) 1238 "Receive jabber count" type(uint32); 1239 register mprc rc addr(base, 0x40b4) 1240 "Management packets receive count" type(uint32); 1241 register mpdc rc addr(base, 0x40b8) 1242 "Management packets dropped count" type(uint32); 1243 register mptc rc addr(base, 0x40bc) 1244 "Management packets transmitted count" type(uint32); 1245 register torl rc addr(base, 0x40c0) 1246 "Total octets received low" type(uint32); 1247 register torh rc addr(base, 0x40c4) 1248 "Total octets received high" type(uint32); 1249 register totl rc addr(base, 0x40c8) 1250 "Total octets transmitted low" type(uint32); 1251 register toth rc addr(base, 0x40cc) 1252 "Total octets transmitted high" type(uint32); 1253 register tpr rc addr(base, 0x40d0) 1254 "Total packets received" type(uint32); 1255 register tpt rc addr(base, 0x40d4) 1256 "Total packets transmitted" type(uint32); 1257 register ptc64 rc addr(base, 0x40d8) 1258 "Packets transmitted (64 bytes) count" type(uint32); 1259 register ptc127 rc addr(base, 0x40dc) 1260 "Packets transmitted (65-127 bytes) count" type(uint32); 1261 register ptc255 rc addr(base, 0x40e0) 1262 "Packets transmitted (128-255 bytes) count" type(uint32); 1263 register ptc511 rc addr(base, 0x40e4) 1264 "Packets transmitted (256-511 bytes) count" type(uint32); 1265 register ptc1023 rc addr(base, 0x40e8) 1266 "Packets transmitted (512-1023 bytes) count" type(uint32); 1267 register ptc1522 rc addr(base, 0x40ec) 1268 "Packets transmitted (1024-max bytes) count" type(uint32); 1269 register mcptc rc addr(base, 0x40f0) 1270 "Multicast packets transmitted count" type(uint32); 1271 register bptc rc addr(base, 0x40f4) 1272 "Broadcast packets transmitted count" type(uint32); 1273 register tsctc rc addr(base, 0x40f8) 1274 "TCP segmentation context transmitted count" type(uint32); 1275 register tsctfc rc addr(base, 0x40fc) 1276 "TCP segmentation context tx fail count" type(uint32); 1277 register iac rc addr(base, 0x4100) 1278 "Interrupt assertion count" type(uint32); 1279 register icrxptc rc addr(base, 0x4104) 1280 "Interrupt cause rx packet timer expire count" type(uint32); 1281 register icrxatc rc addr(base, 0x4108) 1282 "Interrupt cause rx absolute timer expire count" type(uint32); 1283 register ictxptc rc addr(base, 0x410c) 1284 "Interrupt cause tx packet timer expire count" type(uint32); 1285 register ictxatc rc addr(base, 0x4110) 1286 "Interrupt cause tx absolute timer expire count" type(uint32); 1287 register ictxqec rc addr(base, 0x4118) 1288 "Interrupt cause transmit queue empty count" type(uint32); 1289 register ictxdltc rc addr(base, 0x411c) 1290 "Interrupt cause transmit descriptor low threshold count" type(uint32); 1291 register icrxdmtc rc addr(base, 0x4120) 1292 "Interrupt cause receive descriptor minimum threshold count" type(uint32); 1293 register icrxoc rc addr(base, 0x4124) 1294 "Interrupt cause receive overrun count" type(uint32); 1295 1296 regarray statsregs rc also addr(base, 0x4000)[74] 1297 "All stats registers" type(uint32); 1298 1299 1300 /************************************ 1301 * Descriptors 1302 ***********************************/ 1303 1304 // 3.2.4 1305 datatype legacy_rdesc lsbfirst(64) "Legacy rx descriptor" { 1306 addr 64 "Buffer address"; 1307 length 16 "Packet length"; 1308 checksum 16 "Packet checksum"; 1309 // Status 1310 dd 1 "Descriptor done"; 1311 eop 1 "End of packet"; 1312 ixsm 1 "Ignore checksum indication"; 1313 vp 1 "Packet is 802.1q (matched VET)"; 1314 udpcs 1 "UDP checksum calculated on packet"; 1315 tcpcs 1 "TCP checksum calculated on packet"; 1316 ipcs 1 "IPv4 checksum calculated on packet"; 1317 pif 1 "Passed in-exact filter"; 1318 // Errors 1319 ce 1 "CRC or alignment error"; 1320 se 1 "Symbol error"; 1321 seq 1 "Sequence error"; 1322 _ 2; 1323 tcpe 1 "TCP/UDP checksum error"; 1324 ipe 1 "IPv4 checksum error"; 1325 rxe 1 "RX data error"; 1326 // VLAN tag field 1327 vlan 12 "VLAN id"; 1328 cr 1 "Canonical form indicator"; 1329 pri 3 "802.1p priority"; 1330 }; 1331 1332 // 3.2.5 1333 datatype rdesc_read lsbfirst(64) "Extended rx descriptor (read format)" { 1334 addr 64 "Buffer address"; 1335 dd 1 "Descriptor done"; 1336 _ 63; 1337 }; 1338 datatype rdesc_write lsbfirst(64) "Extended rx descriptor (write format)" { 1339 // MRQ 1340 rss 4 type(rsstype) "RSS type"; 1341 _ 4; 1342 queue 5 "Receive queue"; 1343 _ 19; 1344 // IP id; note that the RSS hash can overlay the next two fields 1345 ipid 16 "IP header identification field"; 1346 // Checksum 1347 checksum 16 "Packet checksum"; 1348 // Extended status 1349 dd 1 "Descriptor done"; 1350 eop 1 "End of packet"; 1351 ixsm 1 "Ignore checksum indication"; 1352 vp 1 "Packet is 802.1q (matched VET)"; 1353 udpcs 1 "UDP checksum calculated on packet"; 1354 tcpcs 1 "TCP checksum calculated on packet"; 1355 ipcs 1 "IPv4 checksum calculated on packet"; 1356 pif 1 "Passed in-exact filter"; 1357 _ 1; 1358 ipidv 1 "IP identification valid"; 1359 udpv 1 "Valid UDP checksum"; 1360 _ 4; 1361 ack 1 "ACK packet identification"; 1362 _ 4; 1363 // Extended errors 1364 _ 4; 1365 ce 1 "CRC or alignment error"; 1366 se 1 "Symbol error"; 1367 seq 1 "Sequence error"; 1368 _ 2; 1369 tcpe 1 "TCP/UDP checksum error"; 1370 ipe 1 "IPv4 checksum error"; 1371 rxe 1 "RX data error"; 1372 // Length 1373 length 16 "Packet length"; 1374 // VLAN tag field 1375 vlan 12 "VLAN id"; 1376 cr 1 "Canonical form indicator"; 1377 pri 3 "802.1p priority"; 1378 }; 1379 1380 // 3.2.5.4 1381 constants rsstype "RSS computation type" { 1382 no_rss = 0x0 "No RS computation"; 1383 tcp_v4 = 0x1 "IPv4 with TCP hash"; 1384 ipv4 = 0x2 "IPv4 hash"; 1385 tcp_v6 = 0x3 "IPv6 with TCP hash"; 1386 ipv6 = 0x5 "IPv6 hash"; 1387 }; 1388 1389 1390}; 1391