1/*
2 * Copyright (c) 2014 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * xeon_phi_apic.dev
11 *
12 * description: register definitions for the Xeon Phi APIC register
13 * 
14 * Note: this is for raising interrupts to the other parts.
15 */
16
17device xeon_phi_apic lsbfirst ( addr base ) "Intel Xeon Phi APIC register" {
18
19     constants irq_vec width(32) "Interupt Vectors" {
20          vec_bsp = 229;
21     };
22     
23     constants irq_idx width(3) "Interrupt Register Index" {
24          vnet      = 0;
25          sht       = 1;
26          hvc       = 2;
27          virtio    = 3;
28          pm        = 4;
29          unused    = 5;
30          unused2   = 6;
31          bootstrap = 7;
32     };
33     
34
35    constants dst_shorthand "Destination shorthand" {
36      none    = 0b00 "No shorthand";
37      self    = 0b01 "Self";
38      all_inc = 0b10 "All including self";
39      all_exc = 0b11 "All excluding self";
40    };
41
42    constants dst_mode "Destination mode" {
43      dst_phys        = 0b00 "Physical";
44      dst_log         = 0b01 "Logical";
45    };
46
47    constants int_level "Interrupt level" {
48      lvl_clr         = 0b00 "Clear";
49      lvl_set         = 0b01 "Set";
50    };
51    
52    constants vdm "Vector delivery mode" { 
53      fixed   = 0b000 "Fixed";
54      lowest  = 0b001 "Lowest priority";
55      smi     = 0b010 "SMI";
56      nmi     = 0b100 "NMI";
57      init    = 0b101 "INIT";
58      startup = 0b110 "Start Up";
59      extint  = 0b111 "ExtINT";
60    };
61    
62    constants trigm "Trigger mode" {
63      edge  = 0 "Edge";
64      level = 1 "Level";
65    };
66
67    /*
68     * Protection Level: Ring 0
69     * Visibility: Host / Coprocessor
70     * Reset Dmain: GRPB_RESET
71     * Register Access: CRU
72     */
73    register id rw addr(base, 0xA800) "APIC Identification Register" { 
74        _   23;
75        id  9 "apic id";
76    };
77
78    /*
79     * Protection Level: Ring 0
80     * Visibility: Host / Coprocessor
81     * Reset Dmain: GRPB_RESET
82     * Register Access: CRU
83     */
84    register version rw addr(base, 0xA804) "APIC Version Register" { 
85        ver      8 "version";
86        _        8;
87        max_lvt  8 "max LVT entry";
88        _        8;
89    };
90
91    /*
92     * Protection Level: Ring 0
93     * Visibility: Host / Coprocessor
94     * Reset Dmain: GRPB_RESET
95     * Register Access: CRU
96     */
97    register pr rw addr(base, 0xA808) "APIC Priority Register" { 
98        value 32 "Value";
99    };
100
101    /*
102     * Protection Level: Ring 0
103     * Visibility: Host / Coprocessor
104     * Reset Dmain: GRPB_RESET
105     * Register Access: CRU
106     * Number: 26
107     */
108    regarray rt rw addr(base, 0xA840) [26] "APIC Redirection Table" { 
109        value 64 "Value";
110    };            
111
112    /*
113     * Protection Level: Ring 0
114     * Visibility: Host / Coprocessor
115     * Reset Dmain: GRPB_RESET
116     * Register Access: CRU
117     * Number: 8
118     */
119    regarray icr_lo rw addr(base, 0xA9D0) [8; 0x8] "APIC Interrupt Command Register 0 to 7" { 
120        vector      8 "Vector";
121        dlv_mode    3 type(vdm) "Delivery mode";
122        dst_mode    1 type(dst_mode) "Destination mode";
123        dlv_stat    1 ro "Delivery status";
124        boot_notify 1 "Boot notify bit";
125        level       1 type(int_level) "Level";
126        trig_mode   1 type(trigm) "Trigger mode";
127        _           2;
128        dst_short   2 type(dst_shorthand) "Destination shorthand";
129        _           12;
130    };            
131    
132    regarray icr_hi rw addr(base, 0xA9D4) [8; 0x8]  "APIC Interrupt Command Register 0 to 7" { 
133        dest        32 "Destination field";
134    }; 
135
136
137};