1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_venc_l4_per.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_venc_l4_per msbfirst ( addr base ) "" { 29 30 31 register venc_rev_id ro addr(base, 0x0) "Revision ID for the encoder" type(uint32); 32 33 constants fsq_status width(3) "" { 34 FSQ_0_r = 0 "ODD field"; 35 FSQ_1_r = 1 "EVEN field"; 36 }; 37 38 register venc_status addr(base, 0x4) "STATUS" { 39 _ 27 mbz; 40 cce 1 ro "Closed Caption Status for Even Field. This bit is set immediately after the data in registers LINE21_E0 and LINE21_E1 have been encoded to closed caption. This bit is reset when both of these registers are written."; 41 cco 1 ro "Closed Caption Status for Odd Field. This bit is set immediately after the data in registers LINE21_O0 and LINE21_O1 have been encoded to closed caption. This bit is reset when both of these registers are written."; 42 fsq 3 ro type(fsq_status) "Field Sequence ID. For PAL, all three FSQ[2:0] are used whereas for NTSC only FSQ[1:0] is meaningful. Furthermore, FSQ[0] represents ODD field when it is '0' and EVEN field when it is '1'."; 43 }; 44 45 constants reset_status width(1) "" { 46 RESET_0 = 0 "No effect"; 47 RESET_1 = 1 "Reset the encoder, after reset, this bit is automatically set to zero."; 48 }; 49 50 constants svds_status width(2) "" { 51 SVDS_0 = 0 "Use external video source"; 52 SVDS_1 = 1 "Use internal Color BAR"; 53 SVDS_2 = 2 "Use background color"; 54 SVDS_3 = 3 "Reserved"; 55 }; 56 57 constants rgbf_status width(1) "" { 58 RGBF_0 = 0 "The input RGB data are in binary format with coding range 0-255 The input YCrCb data are in binary format with coding range 0-255"; 59 RGBF_1 = 1 "The input RGB data are in binary format with coding range 16-235 The input YCrCb data are in binary format conforming to ITU-601 standard"; 60 }; 61 62 constants bcolor_status width(3) "" { 63 BCOLOR_0 = 0 ""; 64 BCOLOR_1 = 1 ""; 65 BCOLOR_2 = 2 ""; 66 BCOLOR_3 = 3 ""; 67 BCOLOR_4 = 4 ""; 68 BCOLOR_5 = 5 ""; 69 BCOLOR_6 = 6 ""; 70 BCOLOR_7 = 7 ""; 71 }; 72 73 constants fmt_status width(2) "" { 74 FMT_0 = 0 "24-bit 4:4:4 RGB"; 75 FMT_1 = 1 "24-bit 4:4:4"; 76 FMT_2 = 2 "16-bit 4:2:2"; 77 FMT_3 = 3 "8-bit ITU-R 656 4:2:2"; 78 }; 79 80 register venc_f_control addr(base, 0x8) "This register specifies the input video source and format" { 81 _ 23 mbz; 82 reset 1 rw type(reset_status) "RESET the encoder"; 83 svds 2 rw type(svds_status) "Select Video Data Source."; 84 rgbf 1 rw type(rgbf_status) "RGB /YCrCb input coding range"; 85 bcolor 3 rw type(bcolor_status) "Background color select"; 86 fmt 2 rw type(fmt_status) "These two bits specify the video input data stream format and timing"; 87 }; 88 89 constants mhz_27_54_status width(1) "" { 90 MHZ_27_54_0 = 0 "54 MHz, 4x oversampling"; 91 MHZ_27_54_1 = 1 "27MHz, 2x oversampling, the last 2x oversampling filter bypassed"; 92 }; 93 94 register venc_vidout_ctrl addr(base, 0x10) "Encoder output clock" { 95 _ 31 mbz; 96 mhz_27_54 1 rw type(mhz_27_54_status) "Encoder output clock"; 97 }; 98 99 constants free_status width(1) "" { 100 FREE_0 = 0 "Free running disabled"; 101 FREE_1 = 1 "Free running enabled. HSYNC and VSYNC are ignored"; 102 }; 103 104 constants esav_status width(1) "" { 105 ESAV_0 = 0 "Detection of F and V bits on both EAV and SAV"; 106 ESAV_1 = 1 "Detection of F and V bits only on EAV"; 107 }; 108 109 constants ignp_status width(1) "" { 110 IGNP_0 = 0 "Protection bits are not ignored"; 111 IGNP_1 = 1 "Protection bits are ignored"; 112 }; 113 114 constants nblnks_status width(1) "" { 115 NBLNKS_0 = 0 "Blank shaping enabled"; 116 NBLNKS_1 = 1 "Blank shaping disabled"; 117 }; 118 119 constants vblkm_status width(2) "" { 120 VBLKM_0 = 0 "Internal default blanking"; 121 VBLKM_1 = 1 "Internal default blanking AND internal programmable blanking defined by FAL and LAL"; 122 VBLKM_2 = 2 "Reserved"; 123 VBLKM_3 = 3 "Reserved"; 124 }; 125 126 constants hblkm_status width(2) "" { 127 HBLKM_0 = 0 "Internal default blanking"; 128 HBLKM_1 = 1 "Internal programmable blanking defined by SAVID and EAVID"; 129 HBLKM_2 = 2 "External blanking defined by AVID"; 130 HBLKM_3 = 3 "Reserved"; 131 }; 132 133 constants m_s_status width(1) "" { 134 M_S_0 = 0 "Sync master. Encoder outputs Vsync, Hsync, FID and AVID."; 135 M_S_1 = 1 "Sync slave. Encoder is synchronized to external Vsync, Hsync, FID and AVID."; 136 }; 137 138 constants fid_pol_status width(1) "" { 139 FID_POL_0 = 0 "ODD field = '0' EVEN field = '1'"; 140 FID_POL_1 = 1 "ODD field = '1' EVEN field = '0'"; 141 }; 142 143 constants vs_pol_status width(1) "" { 144 VS_POL_0 = 0 "VS is active high"; 145 VS_POL_1 = 1 "VS is active low"; 146 }; 147 148 constants hs_pol_status width(1) "" { 149 HS_POL_0 = 0 "HS is active high"; 150 HS_POL_1 = 1 "HS is active low"; 151 }; 152 153 constants fhvmod_status width(1) "" { 154 FHVMOD_0 = 0 "External FID"; 155 FHVMOD_1 = 1 "Extracted from HSYNC and VSYNC"; 156 }; 157 158 register venc_sync_ctrl addr(base, 0x14) "SYNC Control register" { 159 _ 16 mbz; 160 free 1 rw type(free_status) "Free running"; 161 esav 1 rw type(esav_status) "Enable to detect F and V bits only on EAV in ITU-R 656 input mode"; 162 ignp 1 rw type(ignp_status) "Ignore protection bits in ITU-R 656 input mode"; 163 nblnks 1 rw type(nblnks_status) "Blank shaping"; 164 vblkm 2 rw type(vblkm_status) "Vertical blanking mode"; 165 hblkm 2 rw type(hblkm_status) "Horizontal blanking mode"; 166 m_s 1 rw type(m_s_status) "Encoder is master or slave of external sync"; 167 fid_pol 1 rw type(fid_pol_status) "FID output polarity"; 168 _ 2 mbz; 169 vs_pol 1 rw type(vs_pol_status) "VS input polarity"; 170 hs_pol 1 rw type(hs_pol_status) "HS input polarity"; 171 _ 1 mbz; 172 fhvmod 1 rw type(fhvmod_status) "FID extracted from external FID or HSYNC and VSYNC"; 173 }; 174 175 constants llen_en_status width(1) "" { 176 LLEN_EN_0 = 0 "disable"; 177 LLEN_EN_1 = 1 "enable"; 178 }; 179 180 register venc_llen addr(base, 0x1C) "LLEN" { 181 _ 16 mbz; 182 llen_en 1 rw type(llen_en_status) "LLEN_EN"; 183 _ 4 mbz; 184 llen 11 rw "LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking. Total number of pixels in a scan line = LLEN NOTE: A write to bit 11 of this bit field is illegal."; 185 }; 186 187 register venc_flens addr(base, 0x20) "FLENS" { 188 _ 21 mbz; 189 flens 11 rw "The frame length or total number of lines in a frame including active video and blanking from the source image. Total number of lines in a frame from the source image = FLENS + 1"; 190 }; 191 192 constants cintp_status width(2) "" { 193 CINTP_0 = 0 "The chrominance interpolation filter is enabled"; 194 CINTP_1 = 1 "The first section of the chrominance interpolation filter is bypassed"; 195 CINTP_2 = 2 "The second section of the chrominance interpolation filter is bypassed"; 196 CINTP_3 = 3 "Both sections of the filter are bypassed"; 197 }; 198 199 register venc_hfltr_ctrl addr(base, 0x24) "HFLTR_CTRL" { 200 _ 29 mbz; 201 cintp 2 rw type(cintp_status) "Chrominance interpolation filter control"; 202 yintp 1 rw type(cintp_status) "Luminance interpolation filter control"; 203 }; 204 205 register venc_cc_carr_wss_carr addr(base, 0x28) "Frequencie code control" { 206 fwss 16 rw "Wide screen signaling run-in code frequency control. For 50-Hz systems, FWSS = 2 * 5 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line frequency."; 207 fcc 16 rw "Close caption run-in code frequency control. For 60-Hz system, FCC = 2 * 0.5035 * 10/(LLEN * Fh) For 50-Hz systems, FCC = 2* 0.500 * 10/(LLEN * Fh), where LLEN = total number of pixels in a scan line Fh = line frequency."; 208 }; 209 210 register venc_c_phase addr(base, 0x2C) "C_PHASE" { 211 _ 24 mbz; 212 cphs 8 rw "Phase of the encoded video color subcarrier (including the color burst) relative to H-sync. The adjustable step is 360/256 degrees."; 213 }; 214 215 register venc_gain_u addr(base, 0x30) "Gain control for Cb signal" { 216 _ 23 mbz; 217 gu 9 rw "Gain control for Cb signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GU = 0x102 NTSC with no pedestal: WHITE - BLACK = 100 IRE GU = 0x117 PAL with no pedestal: WHITE - BLACK = 100 IRE GU = 0x111"; 218 }; 219 220 register venc_gain_v addr(base, 0x34) "Gain control of Cr signal" { 221 _ 23 mbz; 222 gv 9 rw "Gain control of Cr signal. Following are typical programming examples for NTSC and PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GV = 0x16C NTSC with no pedestal: WHITE - BLACK = 100 IRE GV = 0x189 PAL with no pedestal: WHITE - BLACK = 100 IRE GV = 0x181"; 223 }; 224 225 register venc_gain_y addr(base, 0x38) "Gain control of Y signal" { 226 _ 23 mbz; 227 gy 9 rw "Gain control of Y signal. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GY = 0x12F NTSC with no pedestal: WHITE - BLACK = 100 IRE GY = 0x147 PAL with no pedestal: WHITE - BLACK = 100 IRE GY = 0x140"; 228 }; 229 230 register venc_black_level addr(base, 0x3C) "BLACK LEVEL" { 231 _ 25 mbz; 232 black 7 rw "Black level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLACK_LEVEL = 0x43 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x38 PAL with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x3B"; 233 }; 234 235 register venc_blank_level addr(base, 0x40) "BLANK LEVEL" { 236 _ 25 mbz; 237 blank 7 rw "Blank level setting. Following are typical programming examples for NTSC/PAL standards. NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLANK_LEVEL = 0x38 NTSC with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x38 PAL with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x3B"; 238 }; 239 240 constants xce_status width(1) "" { 241 XCE_0 = 0 "Cross color reduction is disabled"; 242 XCE_1 = 1 "Cross color is enabled"; 243 }; 244 245 constants lcd_status width(3) "" { 246 LCD_0 = 0 "0"; 247 LCD_1 = 1 "0.5 pixel clock period"; 248 LCD_2 = 2 "1.0 pixel clock period"; 249 LCD_3 = 3 "1.5 pixel clock period"; 250 LCD_4 = 4 "-2.0 pixel clock period"; 251 LCD_5 = 5 "-1.5 pixel clock period"; 252 LCD_6 = 6 "-1.0 pixel clock period"; 253 LCD_7 = 7 "-0.5 pixel clock period"; 254 }; 255 256 register venc_x_color addr(base, 0x44) "Cross-Colour Control register" { 257 _ 25 mbz; 258 xce 1 rw type(xce_status) "Cross color reduction enable for composite video output. Cross color does not affect S-video output"; 259 _ 1 mbz; 260 xcbw 2 rw type(cintp_status) "Cross color reduction filter selection"; 261 lcd 3 rw type(lcd_status) "These three bits can be used for chroma channel delay compensation. Delay on Luma channel."; 262 }; 263 264 constants pali_status width(1) "" { 265 PALI_0 = 0 "Normal oeration"; 266 PALI_1 = 1 "PAL I Enable"; 267 }; 268 269 constants paln_status width(1) "" { 270 PALN_0 = 0 "Normal operation"; 271 PALN_1 = 1 "PAL N enable"; 272 }; 273 274 constants palphs_status width(1) "" { 275 PALPHS_0 = 0 "PAL switch phase is nominal"; 276 PALPHS_1 = 1 "PAL switch phase is inverted compared to nominal"; 277 }; 278 279 constants cbw_status width(3) "" { 280 CBW_0 = 0 "-6db at 21.8 % of encoding pixel clock frequency"; 281 CBW_1 = 1 "-6db at 19.8 % of encoding pixel clock frequency"; 282 CBW_2 = 2 "-6db at 18.0 % of encoding pixel clock frequency"; 283 CBW_3 = 3 "Reserved"; 284 CBW_4 = 4 "Reserved"; 285 CBW_5 = 5 "-6db at 23.7 % of encoding pixel clock frequency"; 286 CBW_6 = 6 "-6db at 26.8 % of encoding pixel clock frequency"; 287 CBW_7 = 7 "Chrominance lowpass filter bypass"; 288 }; 289 290 constants pal_status width(1) "" { 291 PAL_0 = 0 "Phase alternation line encoding disabled"; 292 PAL_1 = 1 "Phase alternation line encoding enabled"; 293 }; 294 295 register venc_m_control addr(base, 0x48) "M_CONTROL" { 296 _ 24 mbz; 297 pali 1 rw type(pali_status) "PAL I enable"; 298 paln 1 rw type(paln_status) "PAL N Enable"; 299 palphs 1 rw type(palphs_status) "PAL switch phase setting"; 300 cbw 3 rw type(cbw_status) "Chrominance lowpass filter bandwidth control"; 301 pal 1 rw type(pal_status) "Phase alternation line encoding selection"; 302 ffrq 1 rw "The value of this field and the SQP bit in the BSTAMP_WSS_DATA register control the number of horizontal pixels displayed per scan line # OF MODE SQP FFRQ PIXEL PER LINE ITU-R 601 NTSC 0 1 858 Square pixel NTSC 1 1 780 ITU-R 601 PAL 0 0 864 Square pixel PAL 1 0 944"; 303 }; 304 305 constants sqp_status width(1) "" { 306 SQP_0 = 0 "ITU-R 601 sampling rate"; 307 SQP_1 = 1 "Square-pixel sampling rate"; 308 }; 309 310 register venc_bstamp_wss_data addr(base, 0x4C) "BSTAMP and WSS_DATA" { 311 _ 4 mbz; 312 wss_d 20 rw "Wide Screen Signaling data NTSC: WORD 0 D0, D1 WORD 1 D2, D3, D4, D5 WORD 2 D6, D7, D8, D9, D10, D11, D12, D13 CRC D14, D15, D16, D17, D18, D19 PAL: GROUP A D0, D1, D2, D3 GROUP B D4, D5, D6, D7 GROUP C D8, D9 ,D10 GROUP D D11, D12, D13"; 313 sqp 1 rw type(sqp_status) "Square-pixel sampling rate. See FFRQ in M_CONTROL register for programming information."; 314 bstap 7 rw "Setting of amplitude of color burst."; 315 }; 316 317 register venc_s_carr rw addr(base, 0x50) "Color Subcarrier Frequency Registers." type(uint32); 318 319 register venc_line21 addr(base, 0x54) "LINE 21" { 320 l21e 16 rw "The two bytes of the closed caption data in the even field.For the data stream content, see. . [31:24] First byte of data . [23:16] Second byte of data ."; 321 l21o 16 rw "The two bytes of the closed caption data in the odd fieldFor the data stream content, see. . [15:8] First byte of data . [7:0] Second byte of data ."; 322 }; 323 324 register venc_ln_sel addr(base, 0x58) "LN_SEL" { 325 _ 6 mbz; 326 ln21_runin 10 rw "The two Bytes of the closed caption runin code position from the HSYNC"; 327 _ 11 mbz; 328 sline 5 rw "Selects the line where closed caption or extended service data are encoded.PAL mode: Because there is a one-line offset, program the desired line number - 1. . NTSC mode: Because there is a four-line offset, program the desired line number - 4. ."; 329 }; 330 331 constants inv_status width(1) "" { 332 INV_0 = 0 "no effect"; 333 INV_1 = 1 "invert WSS data"; 334 }; 335 336 constants even_odd_en_status width(2) "" { 337 EVEN_ODD_EN_0 = 0 "WSS encoding OFF"; 338 EVEN_ODD_EN_1 = 1 "Enables encoding in 2nd field (odd field)"; 339 EVEN_ODD_EN_2 = 2 "Enables encoding in 1st field (even field)"; 340 EVEN_ODD_EN_3 = 3 "Enables encoding in both fields"; 341 }; 342 343 constants l21en_status width(2) "" { 344 L21EN_0 = 0 "Line21 encoding OFF"; 345 L21EN_1 = 1 "Enables encoding in 1st field (ODD field)"; 346 L21EN_2 = 2 "Enables encoding in 2d field (EVEN field)"; 347 L21EN_3 = 3 "Enables encoding in both fields"; 348 }; 349 350 register venc_l21_wc_ctl addr(base, 0x5C) "L21 and WC_CTL registers" { 351 _ 16 mbz; 352 inv 1 rw type(inv_status) "WSS inverter"; 353 even_odd_en 2 rw type(even_odd_en_status) "This bit controls the WSS encoding."; 354 line 5 rw "Selects the line where WSS data are encoded.PAL mode: Because there is a one-line offset, program the desired line number - 1. . NTSC mode: Because there is a four-line offset, program the desired line number - 4. ."; 355 _ 6 mbz; 356 l21en 2 rw type(l21en_status) "Those bits controls the Line21 closed caption encoding according to the mode."; 357 }; 358 359 register venc_htrigger_vtrigger addr(base, 0x60) "HTRIGGER and VTRIGGER" { 360 _ 6 mbz; 361 vtrig 10 rw "Vertical trigger reference for VSYNC. These bits specify the phase between VSYNC input and the lines in a field. The VTRIG field is expressed in units of half-line."; 362 _ 5 mbz; 363 htrig 11 rw "Horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x (27 MHz) periods"; 364 }; 365 366 register venc_savid_eavid addr(base, 0x64) "SAVID and EAVID" { 367 _ 5 mbz; 368 eavid 11 rw "End of active video. These bits define the ending pixel position on a horizontal display line where active video will be displayed."; 369 _ 5 mbz; 370 savid 11 rw "Start of active video. These bits define the starting pixel position on a horizontal line where active video will be displayed."; 371 }; 372 373 register venc_flen_fal addr(base, 0x68) "FLEN and FAL" { 374 _ 7 mbz; 375 fal 9 rw "First Active Line of Field. These bits define the first active line of a field"; 376 _ 6 mbz; 377 flen 10 rw "Field length. These bits define the number of half_lines in each field. Length of field = (FLEN + 1) half_lines"; 378 }; 379 380 constants pres_status width(2) "" { 381 PRES_0 = 0 "No reset"; 382 PRES_1 = 1 "Reset every two lines"; 383 PRES_2 = 2 "Reset every eight fields. Color subcarrier phase is reset to C_Phase (subaddress 5A) upon reset"; 384 PRES_3 = 3 "Reset every four fields. Color subcarrier phase is reset to C_Phase (subaddress 5A) upon reset"; 385 }; 386 387 constants sblank_status width(1) "" { 388 SBLANK_0 = 0 "Vertical blanking is defined by the setting of FAL and LAL registers."; 389 SBLANK_1 = 1 "Vertical blanking is forced automatically during field synchronization and equalization."; 390 }; 391 392 register venc_lal_phase_reset addr(base, 0x6C) "LAL and PHASE_RESET" { 393 _ 13 mbz; 394 pres 2 rw type(pres_status) "Phase reset mode."; 395 sblank 1 rw type(sblank_status) "Vertical blanking setting"; 396 _ 7 mbz; 397 lal 9 rw "Last Active Line of Field. These bits define the last active line of a field"; 398 }; 399 400 register venc_hs_int_start_stop_x addr(base, 0x70) "HS_INT_START_STOP_X" { 401 _ 6 mbz; 402 hs_int_stop_x 10 rw "HSYNC internal stop. These bits define HSYNC internal stop pixel value"; 403 _ 6 mbz; 404 hs_int_start_x 10 rw "HSYNC internal start. These bits define HSYNC internal start pixel value"; 405 }; 406 407 register venc_hs_ext_start_stop_x addr(base, 0x74) "HS_EXT_START_STOP_X" { 408 _ 6 mbz; 409 hs_ext_stop_x 10 rw "HSYNC external stop. These bits define HSYNC external stop pixel value"; 410 _ 6 mbz; 411 hs_ext_start_x 10 rw "HSYNC external start. These bits define HSYNC external start pixel value"; 412 }; 413 414 register venc_vs_int_start_x addr(base, 0x78) "VS_INT_START_X" { 415 _ 6 mbz; 416 vs_int_start_x 10 rw "VSYNC internal start. These bits define VSYNC internal start pixel value."; 417 _ 16 mbz; 418 }; 419 420 register venc_vs_int_stop_x_vs_int_start_y addr(base, 0x7C) "VS_INT_STOP_X and VS_INT_START_Y" { 421 _ 6 mbz; 422 vs_int_start_y 10 rw "VSYNC internal start. These bits define VSYNC internal start line value"; 423 _ 6 mbz; 424 vs_int_stop_x 10 rw "VSYNC internal stop. These bits define VSYNC internal stop pixel value"; 425 }; 426 427 register venc_vs_int_stop_y_vs_ext_start_x addr(base, 0x80) "VS_INT_STOP_Y and VS_EXT_START_X" { 428 _ 6 mbz; 429 vs_ext_start_x 10 rw "VSYNC external start. These bits define VSYNC external start pixel value."; 430 _ 6 mbz; 431 vs_int_stop_y 10 rw "VSYNC internal stop. These bits define VSYNC internal stop line value."; 432 }; 433 434 register venc_vs_ext_stop_x_vs_ext_start_y addr(base, 0x84) "VS_EXT_STOP_X and VS_EXT_START_Y" { 435 _ 6 mbz; 436 vs_ext_start_y 10 rw "VSYNC external start. These bits define VSYNC external start line value."; 437 _ 6 mbz; 438 vs_ext_stop_x 10 rw "VSYNC external stop. These bits define VSYNC external stop pixel value."; 439 }; 440 441 register venc_vs_ext_stop_y addr(base, 0x88) "VS_EXT_STOP_Y" { 442 _ 22 mbz; 443 vs_ext_stop_y 10 rw "VSYNC external stop. These bits define VSYNC external stop line value."; 444 }; 445 446 register venc_avid_start_stop_x addr(base, 0x90) "AVID_START_STOP_X" { 447 _ 6 mbz; 448 avid_stop_x 10 rw "AVID stop. These bits define AVID stop pixel value"; 449 _ 6 mbz; 450 avid_start_x 10 rw "AVID start. These bits define AVID start pixel value"; 451 }; 452 453 register venc_avid_start_stop_y addr(base, 0x94) "AVID_START_STOP_Y" { 454 _ 6 mbz; 455 avid_stop_y 10 rw "AVID stop. These bits define AVID stop line value."; 456 _ 6 mbz; 457 avid_start_y 10 rw "AVID start. These bits define AVID start line value"; 458 }; 459 460 register venc_fid_int_start_x_fid_int_start_y addr(base, 0xA0) "FID_INT_START_X and FID_INT_START_Y" { 461 _ 6 mbz; 462 fid_int_start_y 10 rw "FID internal stop. These bits define FID internal start line value"; 463 _ 6 mbz; 464 fid_int_start_x 10 rw "FID internal start. These bits define FID internal start pixel value"; 465 }; 466 467 register venc_fid_int_offset_y_fid_ext_start_x addr(base, 0xA4) "FID_INT_OFFSET_Y and FID_EXT_START_X" { 468 _ 6 mbz; 469 fid_ext_start_x 10 rw "FID external start. These bits define FID external start pixel value"; 470 _ 6 mbz; 471 fid_int_offset_y 10 rw "FID internal offset. These bits define FID internal offset linel value"; 472 }; 473 474 register venc_fid_ext_start_y_fid_ext_offset_y addr(base, 0xA8) "FID_EXT_START_Y and FID_EXT_OFFSET_Y" { 475 _ 6 mbz; 476 fid_ext_offset_y 10 rw "FID external offset. These bits define FID external offset line value"; 477 _ 6 mbz; 478 fid_ext_start_y 10 rw "FID external start. These bits define FID external start line value."; 479 }; 480 481 register venc_tvdetgp_int_start_stop_x addr(base, 0xB0) "TVDETGP_INT_START_STOP_X" { 482 _ 6 mbz; 483 tvdetgp_int_stop_x 10 rw "TVDETGP internal stop. These bits define TVDETGP internal stop pixel value."; 484 _ 6 mbz; 485 tvdetgp_int_start_x 10 rw "TVDETGP internal start. These bits define TVDETGP internal start pixel value"; 486 }; 487 488 register venc_tvdetgp_int_start_stop_y addr(base, 0xB4) "TVDETGP_INT_START_STOP_Y" { 489 _ 6 mbz; 490 tvdetgp_int_stop_y 10 rw "TVDETGP internal stop. These bits define TVDETGP internal stop line value."; 491 _ 6 mbz; 492 tvdetgp_int_start_y 10 rw "TVDETGP internal start. These bits define TVDETGP internal start line value"; 493 }; 494 495 constants ms_status width(1) "" { 496 MS_0 = 0 "CbCr"; 497 MS_1 = 1 "CrCb"; 498 }; 499 500 constants hip_status width(1) "" { 501 HIP_0 = 0 "Active Low"; 502 HIP_1 = 1 "Active High"; 503 }; 504 505 constants en_status width(1) "" { 506 EN_0 = 0 "Disabled"; 507 EN_1 = 1 "Enabled"; 508 }; 509 510 register venc_gen_ctrl addr(base, 0xB8) "TVDETGP enable and SYNC_POLARITY and UVPHASE_POL" { 511 _ 5 mbz; 512 ms 1 rw type(ms_status) "UVPHASE_POL MS mode UV phase"; 513 uvphase_pol_656 1 rw type(ms_status) "UVPHASE_POL 656 input mode UV phase"; 514 cbar 1 rw type(ms_status) "UVPHASE_POL CBAR mode UV phase"; 515 hip 1 rw type(hip_status) "HSYNC internal polarity"; 516 vip 1 rw type(hip_status) "VSYNC internal polarity"; 517 hep 1 rw type(hip_status) "HSYNC external polarity"; 518 vep 1 rw type(hip_status) "VSYNC externall polarity"; 519 avidp 1 rw type(hip_status) "AVID polarity"; 520 fip 1 rw type(hip_status) "FID internal polarity"; 521 fep 1 rw type(hip_status) "FID external polarity"; 522 tvdp 1 rw type(hip_status) "TVDETGP polarity"; 523 _ 15 mbz; 524 en 1 rw type(en_status) "TVDETGP generation enable"; 525 }; 526 527 constants composite_source_status width(1) "" { 528 COMPOSITE_SOURCE_0 = 0 "Composite test data comes from internal register OUTPUT_TEST[9:0]"; 529 COMPOSITE_SOURCE_1 = 1 "Composite test data comes from display controller video port G[1:0], B[7:0]"; 530 }; 531 532 constants test_mode_status width(1) "" { 533 TEST_MODE_0 = 0 "Video outputs are in normal operation"; 534 TEST_MODE_1 = 1 "Test mode. Video outputs are directly connected to either internal registers or the display controller video port."; 535 }; 536 537 constants video_invert_status width(1) "" { 538 VIDEO_INVERT_0 = 0 "Video outputs are inverted"; 539 VIDEO_INVERT_1 = 1 "Video outputs are normal polarity"; 540 }; 541 542 constants composite_enable_status width(1) "" { 543 COMPOSITE_ENABLE_0 = 0 "Composite output is disabled"; 544 COMPOSITE_ENABLE_1 = 1 "Composite output is enabled"; 545 }; 546 547 register venc_output_control addr(base, 0xC4) "Output channel control register Also contains some test control features" { 548 _ 25 mbz; 549 composite_source 1 rw type(composite_source_status) "Source of composite video data in test mode"; 550 _ 1 mbz; 551 test_mode 1 rw type(test_mode_status) "This enables the video DACs to be tested. The values sent to the DACs comes from a register for each output channel (Luma, Composite or Chroma) or from the display controller video port bits G[1:0], B[7:0], depending on the setting of the Source bits"; 552 video_invert 1 rw type(video_invert_status) "Controls the video output polarity. This may be used to correct for inversion in an external video amplifier."; 553 _ 1 mbz; 554 composite_enable 1 rw type(composite_enable_status) "Enable the Composite output channel"; 555 _ 1 mbz; 556 }; 557 558 register venc_output_test addr(base, 0xC8) "Test values for the Luma/Composite Video DAC" { 559 _ 22 mbz; 560 composite_test 10 rw "In test mode, DAC input value (if composite video is selected)"; 561 }; 562};