1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_usbtllhs_config.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_usbtllhs_config msbfirst ( addr base ) "" { 29 30 31 register usbtll_revision ro addr(base, 0x0) "OCP standard revision number, BCD encoded" type(uint32); 32 33 register usbtll_hwinfo addr(base, 0x4) "Information on hardware configuration of host" { 34 _ 24 mbz; 35 sar_cntx_size 8 ro "Save-and-Restore context size, in 32-bit words, i.e. number of 32-bit registers with significant context information, mapped from offset 0x400 upward."; 36 }; 37 38 constants clockactivity_status width(1) "" { 39 CLOCKACTIVITY_0 = 0 "OCP-derived internal clocks OFF during idle"; 40 CLOCKACTIVITY_1 = 1 "OCP-derived internal clocks ON during idle"; 41 }; 42 43 constants sidlemode_status width(2) "" { 44 SIDLEMODE_0 = 0 "Force-idle mode. Sidleack[1] asserted after Sidlereq assertion"; 45 SIDLEMODE_1 = 1 "No-idle mode. Sidleack[1] never asserted."; 46 SIDLEMODE_2 = 2 "Smart-idle mode. Sidleack[1] asserted after Sidlereq assertion when no more activity on the OCP."; 47 }; 48 49 constants enawakeup_status width(1) "" { 50 ENAWAKEUP_0 = 0 "Wake-up generation disabled"; 51 ENAWAKEUP_1 = 1 "Wake-up generation enabled"; 52 }; 53 54 constants softreset_status width(1) "" { 55 SOFTRESET_0_w = 0 "No effect"; 56 SOFTRESET_1_w = 1 "Starts softreset sequence."; 57 }; 58 59 constants autoidle_status width(1) "" { 60 AUTOIDLE_0 = 0 "Clock always running"; 61 AUTOIDLE_1 = 1 "When no activity on OCP, clock is cut off."; 62 }; 63 64 register usbtll_sysconfig addr(base, 0x10) "OCP standard system configuration register" { 65 _ 23 mbz; 66 clockactivity 1 rw type(clockactivity_status) "Enable autogating of OCP-derived internal clocks while module is idle."; 67 _ 3 mbz; 68 sidlemode 2 rw type(sidlemode_status) "Slave interface power management control. Idle Req/ack control"; 69 enawakeup 1 rw type(enawakeup_status) "Asynchronous wake-up generation control (Swakeup)"; 70 softreset 1 wo type(softreset_status) "Module software reset"; 71 autoidle 1 rw type(autoidle_status) "Internal autogating control"; 72 }; 73 74 constants resetdone_status width(1) "" { 75 RESETDONE_0_r = 0 "Reset is ongoing"; 76 RESETDONE_1_r = 1 "Reset is done"; 77 }; 78 79 register usbtll_sysstatus addr(base, 0x14) "OCP standard system status register" { 80 _ 31 mbz; 81 resetdone 1 ro type(resetdone_status) "Indicates when the module has entirely come out of reset"; 82 }; 83 84 constants access_error_status width(1) "" { 85 ACCESS_ERROR_0 = 0 "No event pending"; 86 ACCESS_ERROR_1 = 1 "Event pending"; 87 }; 88 89 register usbtll_irqstatus addr(base, 0x18) "OCP standard IRQ status vector. Write 1 to clear a bit." { 90 _ 29 mbz; 91 access_error 1 rw type(access_error_status) "Access error to ULPI register over OCP: USB clock must run for that type of access to succeed."; 92 fclk_end 1 rw type(access_error_status) "Functional clock is no longer requested for USB clocking"; 93 fclk_start 1 rw type(access_error_status) "Functional clock is requested for USB clocking"; 94 }; 95 96 constants access_error_en_status width(1) "" { 97 ACCESS_ERROR_EN_0 = 0 "IRQ event is masked"; 98 ACCESS_ERROR_EN_1 = 1 "IRQ event is enabled"; 99 }; 100 101 register usbtll_irqenable addr(base, 0x1C) "OCP standard IRQ enable vector" { 102 _ 29 mbz; 103 access_error_en 1 rw type(access_error_en_status) "Enable IRQ generation upon access error to ULPI register over L3 interconnect"; 104 fclk_end_en 1 rw type(access_error_en_status) "IRQ event mask for FCLK_END interrupt (seeUSBTLL_IRQSTATUS[1])"; 105 fclk_start_en 1 rw type(access_error_en_status) "IRQ event mask for FCLK_START interrupt (seeUSBTLL_IRQSTATUS[0])"; 106 }; 107 108 constants fclk_req_status width(1) "" { 109 FCLK_REQ_0 = 0 "Func clock input is not requested by TLL"; 110 FCLK_REQ_1 = 1 "Func clock input is requested by TLL"; 111 }; 112 113 constants fclk_is_on_status width(1) "" { 114 FCLK_IS_ON_0 = 0 "Functional clock input is not guaranteed ON (can actually be ON, OFF, or unstable)"; 115 FCLK_IS_ON_1 = 1 "Functional clock input is guaranteed ON and stable"; 116 }; 117 118 register tll_shared_conf addr(base, 0x30) "Common control register for all TLL channels" { 119 _ 30 mbz; 120 fclk_req 1 ro type(fclk_req_status) "Functional clock request, ORed from all channels depending on their respective USB bus state. Combined with the Fclk_is_on status to generate fclk_start/end IRQs."; 121 fclk_is_on 1 rw type(fclk_is_on_status) "Status of the functional clock input, provided by the system to the TLL module. The TLL module will only use that clock if the current status indicated that it is ready. Combined with the Fclk_request to generate fclk_start/end IRQs."; 122 }; 123 124 constants fslslinestate_status width(2) "" { 125 FSLSLINESTATE_0_r = 0 "Single-ended 0"; 126 FSLSLINESTATE_1_r = 1 "Full-Speed J = differential 1"; 127 FSLSLINESTATE_2_r = 2 "Full-Speed K = differential 0"; 128 FSLSLINESTATE_3_r = 3 "Single-ended 1 (illegal in USB)"; 129 }; 130 131 constants fslsmode_status width(4) "" { 132 FSLSMODE_0 = 0 "6-pin unidirectional PHY i/f mode. TX encoding is Dat/Se0 (default)."; 133 FSLSMODE_1 = 1 "6-pin unidirectional PHY i/f mode. TX encoding is Dp/Dm."; 134 FSLSMODE_2 = 2 "3-pin bidirectional PHY i/f mode"; 135 FSLSMODE_3 = 3 "4-pin bidirectional PHY i/f mode"; 136 FSLSMODE_4 = 4 "6-pin unidirectional TLL mode. TX encoding is Dat/Se0."; 137 FSLSMODE_5 = 5 "6-pin unidirectional TLL mode. TX encoding is Dp/Dm."; 138 FSLSMODE_6 = 6 "3-pin bidirectional TLL mode"; 139 FSLSMODE_7 = 7 "4-pin bidirectional TLL mode"; 140 FSLSMODE_10 = 10 "2-pin bidirectional TLL mode. Encoding is Dat/Se0."; 141 FSLSMODE_11 = 11 "2-pin bidirectional TLL mode. Encoding is Dp/Dm."; 142 }; 143 144 constants testtxse0_status width(1) "" { 145 TESTTXSE0_0 = 0 "drive differential value on TX according to TestTxDat"; 146 TESTTXSE0_1 = 1 "drive SE0 on TX"; 147 }; 148 149 constants testtxdat_status width(1) "" { 150 TESTTXDAT_0 = 0 "Drive full-speed K = differential 0"; 151 TESTTXDAT_1 = 1 "Drive full-speed J = differential 1"; 152 }; 153 154 constants testtxen_status width(1) "" { 155 TESTTXEN_0 = 0 "Drive Tx according to TestTxDat/Se0"; 156 TESTTXEN_1 = 1 "Drive Tx Hiz (no drive: pullups determine line state)"; 157 }; 158 159 constants testen_status width(1) "" { 160 TESTEN_0 = 0 "No override. Tx is from local link controller"; 161 TESTEN_1 = 1 "Override enabled"; 162 }; 163 164 constants drvvbus_status width(1) "" { 165 DRVVBUS_0 = 0 "VBUS not driven"; 166 DRVVBUS_1 = 1 "VBUS driven to 5 V"; 167 }; 168 169 constants chrgvbus_status width(1) "" { 170 CHRGVBUS_0 = 0 "VBUS not charged, session not valid"; 171 CHRGVBUS_1 = 1 "VBUS charged, session valid"; 172 }; 173 174 constants ulpinobitstuff_status width(1) "" { 175 ULPINOBITSTUFF_0 = 0 "Bitstuff enabled, following USB standard"; 176 ULPINOBITSTUFF_1 = 1 "No bitstuff or associated delays (nonstandard)"; 177 }; 178 179 constants ulpiautoidle_status width(1) "" { 180 ULPIAUTOIDLE_0 = 0 "ULPI output clock always-on"; 181 ULPIAUTOIDLE_1 = 1 "ULPI output clock stops during asynchronous ULPI modes"; 182 }; 183 184 constants utmiautoidle_status width(1) "" { 185 UTMIAUTOIDLE_0 = 0 "UTMI clock output always on"; 186 UTMIAUTOIDLE_1 = 1 "UTMI clock output gated upon suspend"; 187 }; 188 189 constants ulpioutclkmode_status width(1) "" { 190 ULPIOUTCLKMODE_1_r = 1 "ULPI clock provided by PHY side (i.e. TLL, from functional clock). ULPI clock is output"; 191 }; 192 193 constants tllfullspeed_status width(1) "" { 194 TLLFULLSPEED_0 = 0 "Connect is Low-speed: D- pullup"; 195 TLLFULLSPEED_1 = 1 "Connect is Full-Speed: D+ pullup"; 196 }; 197 198 constants tllconnect_status width(1) "" { 199 TLLCONNECT_0 = 0 "Unconnected"; 200 TLLCONNECT_1 = 1 "Connected"; 201 }; 202 203 constants tllattach_status width(1) "" { 204 TLLATTACH_0 = 0 "Cable detach emulated on serial TLL"; 205 TLLATTACH_1 = 1 "Cable attach emulated on serial TLL"; 206 }; 207 208 constants utmiisadev_status width(1) "" { 209 UTMIISADEV_0 = 0 "UTMI side is peripheral, ULPI side is host"; 210 UTMIISADEV_1 = 1 "UTMI side is host, ULPI side is peripheral"; 211 }; 212 213 constants chanmode_status width(2) "" { 214 CHANMODE_0 = 0 "UTMI-to-ULPI TLL mode (HS capable): to ULPI controller"; 215 CHANMODE_1 = 1 "UTMI-to-serial (FS/LS) mode: to serial controller (TLL) or serial PHY"; 216 CHANMODE_2 = 2 "Transparent UTMI mode: to UTMI PHY"; 217 CHANMODE_3 = 3 "No mode selected"; 218 }; 219 220 constants chanen_status width(1) "" { 221 CHANEN_0 = 0 "Channel i disabled"; 222 CHANEN_1 = 1 "Channel i enabled"; 223 }; 224 225 register tll_channel_conf_i_0 addr(base, 0x40) "Control and Status register for channel i." { 226 _ 2 mbz; 227 fslslinestate 2 ro type(fslslinestate_status) "Line state for Full/low speed serial modes Bit 1 = D-/ Bit0 = D+"; 228 fslsmode 4 rw type(fslsmode_status) "Multiple-mode serial interface's mode select. Only when main channel mode is serial. No effect in other main modes."; 229 _ 3 mbz; 230 testtxse0 1 rw type(testtxse0_status) "Force-Se0 transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz)"; 231 testtxdat 1 rw type(testtxdat_status) "Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) or TestSe0 = 1 (TX = se0)"; 232 testtxen 1 rw type(testtxen_status) "Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode)"; 233 testen 1 rw type(testen_status) "Enable manual test override for serial mode TX path (from local controller UTMI port)"; 234 drvvbus 1 rw type(drvvbus_status) "VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS drive * In PHY config, write 1 to report 'VBUS valid' status (of actual VBUS) to UTMI controller"; 235 chrgvbus 1 rw type(chrgvbus_status) "VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS charge/pullup (OTG) * In PHY config, write 1 to reports 'session valid' status (of actual VBUS) to UTMI controller"; 236 _ 3 mbz; 237 ulpinobitstuff 1 rw type(ulpinobitstuff_status) "Disable bitstuff emulation in ULPI TLL for ULPI ChanMode"; 238 ulpiautoidle 1 rw type(ulpiautoidle_status) "For ChanMode = ULPI TLL only. Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode (low-power, 3-pin serial, 6-pin serial). No effect in ULPI input clock mode."; 239 utmiautoidle 1 rw type(utmiautoidle_status) "For ChanMode = ULPI TLL only. Allow the UTMI clock (output) to be stopped when UTMII goes to suspended mode (suspendm = 0)"; 240 _ 1 mbz; 241 ulpioutclkmode 1 ro type(ulpioutclkmode_status) "ULPI clocking mode select for ULPI TLL ChanMode. Hardcoded, for legacy only."; 242 tllfullspeed 1 rw type(tllfullspeed_status) "Sets PHY speed emulation in TLL (full/slow), which determines the line to pull up upon connect. The two connect source controls are: input m(N)_tllpuen, register field TllConnect."; 243 tllconnect 1 rw type(tllconnect_status) "Emulation of Full/Low-Speed connect (that is, D+ resp D- pullup) for serial TLL modes. Speed is determined by field TllSpeed."; 244 tllattach 1 rw type(tllattach_status) "Emulates cable attach/detach for all serial TLL modes: * ChanMode = serial, in TLL mode (FsLsMode) * ChanMode = ULPI, in serial mode (6pin/3pin TLL)"; 245 utmiisadev 1 rw type(utmiisadev_status) "Select the cable end 'seen' by UTMI side of TLL, i.e. the emulated USB cable's orientation. The host must always be on A-side, peripheral on B-side. Reset value depends on generic DEFUTMIISHOST."; 246 chanmode 2 rw type(chanmode_status) "Main channel mode selection"; 247 chanen 1 rw type(chanen_status) "Active-high channel enable. A disabled channel is unclocked and kept under reset."; 248 }; 249 250 register tll_channel_conf_i_1 addr(base, 0x44) "Control and Status register for channel i." { 251 _ 2 mbz; 252 fslslinestate 2 ro type(fslslinestate_status) "Line state for Full/low speed serial modes Bit 1 = D-/ Bit0 = D+"; 253 fslsmode 4 rw type(fslsmode_status) "Multiple-mode serial interface's mode select. Only when main channel mode is serial. No effect in other main modes."; 254 _ 3 mbz; 255 testtxse0 1 rw type(testtxse0_status) "Force-Se0 transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz)"; 256 testtxdat 1 rw type(testtxdat_status) "Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode) or = TestTxen = 1 (TX = hiz) or TestSe0 = 1 (TX = se0)"; 257 testtxen 1 rw type(testtxen_status) "Differential data transmit override value for serial mode test Don't care if TestEn = 0 (functional mode)"; 258 testen 1 rw type(testen_status) "Enable manual test override for serial mode TX path (from local controller UTMI port)"; 259 drvvbus 1 rw type(drvvbus_status) "VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS drive * In PHY config, write 1 to report 'VBUS valid' status (of actual VBUS) to UTMI controller"; 260 chrgvbus 1 rw type(chrgvbus_status) "VBUS-drive for ChanMode = serial * In TLL config, write 1 to emulate serial-side VBUS charge/pullup (OTG) * In PHY config, write 1 to reports 'session valid' status (of actual VBUS) to UTMI controller"; 261 _ 3 mbz; 262 ulpinobitstuff 1 rw type(ulpinobitstuff_status) "Disable bitstuff emulation in ULPI TLL for ULPI ChanMode"; 263 ulpiautoidle 1 rw type(ulpiautoidle_status) "For ChanMode = ULPI TLL only. Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode (low-power, 3-pin serial, 6-pin serial). No effect in ULPI input clock mode."; 264 utmiautoidle 1 rw type(utmiautoidle_status) "For ChanMode = ULPI TLL only. Allow the UTMI clock (output) to be stopped when UTMII goes to suspended mode (suspendm = 0)"; 265 _ 1 mbz; 266 ulpioutclkmode 1 ro type(ulpioutclkmode_status) "ULPI clocking mode select for ULPI TLL ChanMode. Hardcoded, for legacy only."; 267 tllfullspeed 1 rw type(tllfullspeed_status) "Sets PHY speed emulation in TLL (full/slow), which determines the line to pull up upon connect. The two connect source controls are: input m(N)_tllpuen, register field TllConnect."; 268 tllconnect 1 rw type(tllconnect_status) "Emulation of Full/Low-Speed connect (that is, D+ resp D- pullup) for serial TLL modes. Speed is determined by field TllSpeed."; 269 tllattach 1 rw type(tllattach_status) "Emulates cable attach/detach for all serial TLL modes: * ChanMode = serial, in TLL mode (FsLsMode) * ChanMode = ULPI, in serial mode (6pin/3pin TLL)"; 270 utmiisadev 1 rw type(utmiisadev_status) "Select the cable end 'seen' by UTMI side of TLL, i.e. the emulated USB cable's orientation. The host must always be on A-side, peripheral on B-side. Reset value depends on generic DEFUTMIISHOST."; 271 chanmode 2 rw type(chanmode_status) "Main channel mode selection"; 272 chanen 1 rw type(chanen_status) "Active-high channel enable. A disabled channel is unclocked and kept under reset."; 273 }; 274 275 register usbtll_sar_cntx_j_0 rw addr(base, 0x400) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 276 277 register usbtll_sar_cntx_j_1 rw addr(base, 0x404) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 278 279 register usbtll_sar_cntx_j_2 rw addr(base, 0x408) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 280 281 register usbtll_sar_cntx_j_3 rw addr(base, 0x40C) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 282 283 register usbtll_sar_cntx_j_4 rw addr(base, 0x410) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 284 285 register usbtll_sar_cntx_j_5 rw addr(base, 0x414) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 286 287 register usbtll_sar_cntx_j_6 rw addr(base, 0x418) "Save and Restore context array. Array size is indicated in. When in SAR mode, read to save and write to restore. Do not access when not in SAR mode." type(uint32); 288};