1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_sr_mpu.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_sr_mpu msbfirst ( addr base ) "" {
29    
30    
31    register srconfig addr(base, 0x0) "Configuration bits for the Sensor Core and the Digital Processing." {
32        accumdata 10 rw "Number of Values to Accumulate";
33        srclklength 10 rw "Determines frequency of SRClk";
34        srenable 1 rw "0: Asynchronously resets MinMaxAvgAccumValid, MinMaxAvgValid, ErrorGeneratorValid, AccumData sensor, SRClk counter, and MinMaxAvg registers. Also gates the clock for power savings and disables all the digital logic. , 1: Enables the module";
35        senenable 1 rw "0: All sensors disabled, 1: Sensors enabled per SenNEnable and SenPEnable";
36        errorgeneratorenable 1 rw "0: Error Generator Module disabled, 1: Error Generator Module enabled";
37        minmaxavgenable 1 rw "0: MinMaxAvg Detector Module disabled, 1: MinMaxAvg Detector Module enabled";
38        _ 6 mbz;
39        sennenable 1 rw "0: Disable SenN sensor, 1: Enable SenN sensor";
40        senpenable 1 rw "0: Disable SenP sensor, 1: Enable SenP sensor";
41    };
42    
43    register srstatus addr(base, 0x4) "Status bits that indicate that the values in the register are valid or events have occurred." {
44        _ 28 mbz;
45        avgerrvalid 1 ro "0: AvgError registers are not valid, 1: AvgError registers are valid.";
46        minmaxavgvalid 1 ro "0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers are valid, but not necessarily fully accumulated";
47        errorgeneratorvalid 1 ro "0: SenError register do not have valid data, 1: SenError registers have valid data.";
48        minmaxavgaccumvalid 1 ro "0: SenVal, SenMin, SenMax, SenAvg registers are not valid, 1: SenVal, SenMin, SenMax, SenAvg registers have valid, final data";
49    };
50    
51    register senval addr(base, 0x8) "The current sensor values from the Sensor Core." {
52        senpval 16 ro "The latest value of the SenPVal from the sensor core.";
53        sennval 16 ro "The latest value of the SenNVal from the sensor core.";
54    };
55    
56    register senmin addr(base, 0xC) "The minimum sensor values." {
57        senpmin 16 ro "The minimum value of the SenPVal from the sensor core since the last restat operation.";
58        sennmin 16 ro "The minimum value of the SenNVal from the sensor core since the last restat operation.";
59    };
60    
61    register senmax addr(base, 0x10) "The maximum sensor values." {
62        senpmax 16 ro "The maximum value of the SenPVal from the sensor core since the last restat operation.";
63        sennmax 16 ro "The maximum value of the SenNVal from the sensor core since the last restat operation.";
64    };
65    
66    register senavg addr(base, 0x14) "The average sensor values." {
67        senpavg 16 ro "The running average of the SenPVal from the sensor core since the last restat operation.";
68        sennavg 16 ro "The running average of the SenNVal from the sensor core since the last restat operation.";
69    };
70    
71    register avgweight addr(base, 0x18) "The weighting factor in the average computation." {
72        _ 28 mbz;
73        senpavgweight 2 rw "The weighting factor for the SenP averager.";
74        sennavgweight 2 rw "The weighting factor for the SenN averager.";
75    };
76    
77    register nvaluereciprocal addr(base, 0x1C) "The reciprocal of the SenN and SenP values used in error generation." {
78        _ 8 mbz;
79        senpgain 4 rw "The gain value for the SenP reciprocal.";
80        senngain 4 rw "The gain value for the SenN reciprocal.";
81        senprn 8 rw "The scale value for the SenP reciprocal.";
82        sennrn 8 rw "The scale value for the SenN reciprocal.";
83    };
84    
85    register irqstatus_raw addr(base, 0x24) "MCU raw interrup status and set." {
86        _ 28 mbz;
87        mcuaccumintstatraw 1 rw "0: Accum interrupt status is unchanged 1: Accum interrupt status is set";
88        mcuvalidintstatraw 1 rw "0: Valid interrupt status is unchanged 1: Valid interrupt status is set";
89        mcuboundsintstatraw 1 rw "0: Bounds interrupt status is unchanged 1: Bounds interrupt status is set";
90        mcudisableackintstatraw 1 rw "0: MCUDisable acknowledge status is unchanged 1: MCUDisable acknowledge status is set";
91    };
92
93    constants mcuaccumintstatena_status width(1) "" {
94        MCUACCUMINTSTATENA_1_r = 1 "Accum interrupt status is set.";
95        MCUACCUMINTSTATENA_0_w = 0 "Accum interrupt status is unchanged.";
96    };
97
98    constants mcuvalidintstatena_status width(1) "" {
99        MCUVALIDINTSTATENA_1_r = 1 "Valid interrupt status is set.";
100        MCUVALIDINTSTATENA_0_w = 0 "Valid interrupt status is unchanged.";
101    };
102
103    constants mcuboundsintstatena_status width(1) "" {
104        MCUBOUNDSINTSTATENA_1_r = 1 "Bounds interrupt status is set.";
105        MCUBOUNDSINTSTATENA_0_w = 0 "Bounds interrupt status is unchanged.";
106    };
107
108    constants mcudisableackintstatena_status width(1) "" {
109        MCUDISABLEACKINTSTATENA_1_r = 1 "MCUDisable acknowledge status is set.";
110        MCUDISABLEACKINTSTATENA_0_w = 0 "MCUDisable interrupt status is unchanged.";
111    };
112    
113    register irqstatus addr(base, 0x28) "MCU masked interrupt status and clear." {
114        _ 28 mbz;
115        mcuaccumintstatena 1 rw type(mcuaccumintstatena_status) "Read 0: Accum interrupt status is unchanged.";
116        mcuvalidintstatena 1 rw type(mcuvalidintstatena_status) "Read 0: Valid interrupt status is unchanged.";
117        mcuboundsintstatena 1 rw type(mcuboundsintstatena_status) "Read 0: Bounds interrupt status is unchanged.";
118        mcudisableackintstatena 1 rw type(mcudisableackintstatena_status) "Read 0: MCUDisable acknowledge status is unchanged.";
119    };
120    
121    register irqenable_set addr(base, 0x2C) "MCU interrupt enable flag and set." {
122        _ 28 mbz;
123        mcuaccumintenaset 1 rw "Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation.";
124        mcuvalidintenaset 1 rw "Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation.";
125        mcuboundsintenaset 1 rw "Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation.";
126        mcudisableactintenaset 1 rw "Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation.";
127    };
128    
129    register irqenable_clr addr(base, 0x30) "MCU interrup enable flag and clear." {
130        _ 28 mbz;
131        mcuaccumintenaclr 1 rw "Read mode: 0: Accum interrupt generation is disabled/masked, 1: Accum interrupt generation is enabled; Write mode: 0: No change to Accum interrupt enable, 1: Enable Accum interrupt generation.";
132        mcuvalidintenaclr 1 rw "Read mode: 0: Valid interrupt generation is disabled/masked, 1: Valid interrupt generation is enabled; Write mode: 0: No change to Valid interrupt enable, 1: Enable Valid interrupt generation.";
133        mcuboundsintenaclr 1 rw "Read mode: 0: Bounds interrupt generation is disabled/masked, 1: Bounds interrupt generation is enabled; Write mode: 0: No change to Bounds interrupt enable, 1: Enable Bounds interrupt generation.";
134        mcudisableackintenaclr 1 rw "Read mode: 0: MCUDisableAck interrupt generation is disabled/masked, 1: MCUDisableAck interrupt generation is enabled; Write mode: 0: No change to MCUDisAck interrupt enable, 1: Enable MCUDisableAck interrupt generation.";
135    };
136    
137    register senerror addr(base, 0x34) "The sensor error from the error generator." {
138        _ 16 mbz;
139        avgerror 8 ro "The average sensor error.";
140        senerror 8 ro "The percentage of sensor error.";
141    };
142    
143    register errconfig addr(base, 0x38) "The sensor error configuration." {
144        _ 5 mbz;
145        wakeupenable 1 rw "Wakeup from MCU Interrupts enable.";
146        idlemode 2 rw "0b00: Force-Idle Mode, 0b01: No Idle Mode, 0b10: Smart-Idle Mode #2, 0b11: Smart-Idle-Wkup mode";
147        vpboundsintstatena 1 rw "0: Bounds interrupt status is unchanged, 1: Bounds interrupt status is cleared.";
148        vpboundsintenable 1 rw "0: Bounds interrupt disabled, 1: Bounds interrupt enabled.";
149        _ 3 mbz;
150        errweight 3 rw "The AvgSenError weight.";
151        errmaxlimit 8 rw "The upper limit of SenError for interrupt generation.";
152        errminlimit 8 rw "The lower limit of SenError for interrupt generation.";
153    };
154};