1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_restore_cm2.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_restore_cm2 msbfirst ( addr base ) "" { 29 30 31 constants clkactivity_l3_1_iclk_status width(1) "" { 32 CLKACTIVITY_L3_1_ICLK_0_r = 0 "Corresponding clock is definitely gated"; 33 CLKACTIVITY_L3_1_ICLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing"; 34 }; 35 36 constants clktrctrl_status width(2) "" { 37 CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 38 CLKTRCTRL_1_r = 1 "Reserved"; 39 CLKTRCTRL_2_r = 2 "Reserved"; 40 CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 41 }; 42 43 register cm_l3_1_clkstctrl_restore addr(base, 0x0) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 44 _ 23 mbz; 45 clkactivity_l3_1_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_1_GICLK clock in the domain. [warm reset insensitive]"; 46 _ 6 mbz; 47 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L3_1 clock domain."; 48 }; 49 50 register cm_l3_2_clkstctrl_restore addr(base, 0x4) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 51 _ 23 mbz; 52 clkactivity_l3_2_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_2_GICLK clock in the domain. [warm reset insensitive]"; 53 _ 6 mbz; 54 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L3_2 clock domain."; 55 }; 56 57 register cm_l4cfg_clkstctrl_restore addr(base, 0x8) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 58 _ 23 mbz; 59 clkactivity_cfg_l4_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L4_CFG_GICLK clock in the domain. [warm reset insensitive]"; 60 _ 6 mbz; 61 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the L4CFG clock domain."; 62 }; 63 64 constants clktrctrl_status1 width(2) "" { 65 CLKTRCTRL_0_3 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 66 CLKTRCTRL_1_r_3 = 1 "Reserved"; 67 CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 68 CLKTRCTRL_3_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 69 }; 70 71 register cm_memif_clkstctrl_restore addr(base, 0xC) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 72 _ 18 mbz; 73 clkactivity_async_phy2_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the ASYNC_PHY2_CLK clock in the domain. [warm reset insensitive]"; 74 clkactivity_async_phy1_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the ASYNC_PHY1_CLK clock in the domain. [warm reset insensitive]"; 75 clkactivity_async_dll_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the ASYNC_DLL_CLK clock in the domain. [warm reset insensitive]"; 76 clkactivity_phy_root_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PHY_ROOT_CLK clock in the domain. [warm reset insensitive]"; 77 clkactivity_dll_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DLL_CLK clock in the domain. [warm reset insensitive]"; 78 clkactivity_l3_emif_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_EMIF_GICLK clock in the domain. [warm reset insensitive]"; 79 _ 6 mbz; 80 clktrctrl 2 rw type(clktrctrl_status1) "Controls the clock state transition of the MEMIF clock domain."; 81 }; 82 83 constants clktrctrl_status2 width(2) "" { 84 CLKTRCTRL_0_4 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 85 CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain."; 86 CLKTRCTRL_2_1 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 87 CLKTRCTRL_3_4 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 88 }; 89 90 register cm_l4per_clkstctrl_restore addr(base, 0x10) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 91 _ 6 mbz; 92 clkactivity_per_abe_24m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_ABE_24M_FCLK clock in the domain. [warm reset insensitive]"; 93 _ 1 mbz; 94 _ 1 mbz; 95 clkactivity_per_mcbsp4_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_MCBSP4_FCLK clock in the domain. [warm reset insensitive]"; 96 _ 2 mbz; 97 clkactivity_per_96m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_96M_FCLK clock in the domain. [warm reset insensitive]"; 98 clkactivity_per_48m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_48M_FCLK clock in the domain. [warm reset insensitive]"; 99 clkactivity_per_32k_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_32K_FCLK clock in the domain. [warm reset insensitive]"; 100 clkactivity_per_24mc_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the PER_24MC_FCLK clock in the domain. [warm reset insensitive]"; 101 clkactivity_12m_fclk_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the FUNC_12M_FCLK clock in the domain. [warm reset insensitive]"; 102 clkactivity_gpt9_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT9_FCLK clock in the domain. [warm reset insensitive]"; 103 clkactivity_gpt4_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT4_FCLK clock in the domain. [warm reset insensitive]"; 104 clkactivity_gpt3_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT3_FCLK clock in the domain. [warm reset insensitive]"; 105 clkactivity_gpt2_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT2_FCLK clock in the domain. [warm reset insensitive]"; 106 clkactivity_gpt11_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT11_FCLK clock in the domain. [warm reset insensitive]"; 107 clkactivity_gpt10_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the DMT10_FCLK clock in the domain. [warm reset insensitive]"; 108 clkactivity_l4_per_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L4_PER_GICLK clock in the domain. [warm reset insensitive]"; 109 _ 6 mbz; 110 clktrctrl 2 rw type(clktrctrl_status2) "Controls the clock state transition of the L4PER clock domain."; 111 }; 112 113 register cm_l3init_clkstctrl_restore addr(base, 0x14) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 114 _ 2 mbz; 115 clkactivity_init_60m_p2_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_60M_P2_FCLK clock in the domain. [warm reset insensitive]"; 116 clkactivity_init_60m_p1_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_60M_P1_FCLK clock in the domain. [warm reset insensitive]"; 117 clkactivity_hsic_p2_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the HSIC_P2_FCLK clock in the domain. [warm reset insensitive]"; 118 clkactivity_hsic_p1_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the HSIC_P1_FCLK clock in the domain. [warm reset insensitive]"; 119 clkactivity_utmi_root_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the UTMI_ROOT_FCLK clock in the domain. [warm reset insensitive]"; 120 _ 1 mbz; 121 clkactivity_tll_ch1_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the TLL_CH1_FCLK clock in the domain. [warm reset insensitive]"; 122 clkactivity_tll_ch0_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the TLL_CH0_FCLK clock in the domain. [warm reset insensitive]"; 123 clkactivity_hsic_p2_480m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the HSIC_P2_480M_FCLK clock in the domain. [warm reset insensitive]"; 124 clkactivity_hsic_p1_480m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the HSIC_P1_480M_FCLK clock in the domain. [warm reset insensitive]"; 125 clkactivity_init_hsmmc6_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_HSMMC6_FCLK clock in the domain. [warm reset insensitive]"; 126 clkactivity_init_hsmmc2_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_HSMMC2_FCLK clock in the domain. [warm reset insensitive]"; 127 clkactivity_init_hsmmc1_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_HSMMC1_FCLK clock in the domain. [warm reset insensitive]"; 128 clkactivity_init_hsi_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_HSI_FCLK clock in the domain. [warm reset insensitive]"; 129 clkactivity_usb_dpll_hs_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the USB_DPLL_HS_CLK clock in the domain. [warm reset insensitive]"; 130 clkactivity_usb_dpll_clk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the USB_DPLL_CLK clock in the domain. [warm reset insensitive]"; 131 clkactivity_init_48mc_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_48MC_FCLK clock in the domain. [warm reset insensitive]"; 132 clkactivity_init_48m_fclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the INIT_48M_FCLK clock in the domain. [warm reset insensitive]"; 133 _ 2 mbz; 134 clkactivity_init_l4_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L4_INIT_GICLK clock in the domain. [warm reset insensitive]"; 135 clkactivity_init_l3_iclk 1 ro type(clkactivity_l3_1_iclk_status) "This field indicates the state of the L3_INIT_GICLK clock in the domain. [warm reset insensitive]"; 136 _ 6 mbz; 137 clktrctrl 2 rw type(clktrctrl_status2) "Controls the clock state transition of the L3INIT clock domain."; 138 }; 139 140 constants idlest_status width(2) "" { 141 IDLEST_0_r = 0 "Module is fully functional, including INTRCONN"; 142 IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 143 IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock"; 144 IDLEST_3_r = 3 "Module is disabled and cannot be accessed"; 145 }; 146 147 constants modulemode_status width(2) "" { 148 MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup)."; 149 MODULEMODE_1 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state."; 150 MODULEMODE_2_r = 2 "Reserved"; 151 MODULEMODE_3_r = 3 "Reserved"; 152 }; 153 154 register cm_l3instr_l3_3_clkctrl_restore addr(base, 0x18) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 155 _ 14 mbz; 156 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 157 _ 14 mbz; 158 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 159 }; 160 161 register cm_l3instr_l3_instr_clkctrl_restore addr(base, 0x1C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 162 _ 14 mbz; 163 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 164 _ 14 mbz; 165 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 166 }; 167 168 constants idlest_status1 width(2) "" { 169 IDLEST_3_r_2 = 3 "Module is disabled and cannot be accessed"; 170 IDLEST_2_r_2 = 2 "Module is in idle mode (only Interconnect part). It is functional if using separate functional clock"; 171 IDLEST_1_r_2 = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 172 IDLEST_0_r_2 = 0 "Module is fully functional, including Interconnect"; 173 }; 174 175 constants modulemode_status1 width(2) "" { 176 MODULEMODE_0_2 = 0 "Module is disable by software. Any Interconnect access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup)."; 177 MODULEMODE_1_2 = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any Interconnect access to module is always granted. Module clocks may be gated according to the clock domain state."; 178 MODULEMODE_2_r_2 = 2 "Reserved"; 179 MODULEMODE_3_r_2 = 3 "Reserved"; 180 }; 181 182 register cm_l3instr_ocp_wp1_clkctrl_restore addr(base, 0x20) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 183 _ 14 mbz; 184 idlest 2 ro type(idlest_status1) "Module idle status. [warm reset insensitive]"; 185 _ 14 mbz; 186 modulemode 2 rw type(modulemode_status1) "Control the way mandatory clocks are managed."; 187 }; 188 189 constants idlest_status2 width(2) "" { 190 IDLEST_3_r_3 = 3 "Module is disabled"; 191 IDLEST_2_r_3 = 2 "Module is in Idle"; 192 IDLEST_1_r_3 = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 193 IDLEST_0_r_3 = 0 "Module is fully functional"; 194 }; 195 196 constants modulemode_status2 width(2) "" { 197 MODULEMODE_0_3 = 0 "Module is disabled by software. OCP configuration port is not accessible."; 198 MODULEMODE_1_3 = 1 "Module is managed automatically by hardware along with L3INSTR domain."; 199 MODULEMODE_2_r_3 = 2 "Reserved"; 200 MODULEMODE_3_r_3 = 3 "Reserved"; 201 }; 202 203 register cm_cm2_profiling_clkctrl_restore addr(base, 0x24) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" { 204 _ 14 mbz; 205 idlest 2 ro type(idlest_status2) "Module idle status"; 206 _ 14 mbz; 207 modulemode 2 rw type(modulemode_status2) "Control the way mandatory clocks are managed."; 208 }; 209 210 constants l4per_statdep_status width(1) "" { 211 L4PER_STATDEP_0 = 0 "Dependency is disabled"; 212 L4PER_STATDEP_1 = 1 "Dependency is enabled"; 213 }; 214 215 register cm_c2c_staticdep_restore addr(base, 0x28) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 216 _ 18 mbz; 217 l4per_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L4PER clock domain"; 218 l4cfg_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L4CFG clock domain"; 219 _ 4 mbz; 220 l3init_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L3INIT clock domain"; 221 l3_2_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L3_2 clock domain"; 222 l3_1_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L3_1 clock domain"; 223 memif_statdep 1 rw type(l4per_statdep_status) "Static dependency towards MEMIF clock domain"; 224 abe_statdep 1 rw type(l4per_statdep_status) "Static dependency towards ABE clock domain"; 225 ivahd_statdep 1 rw type(l4per_statdep_status) "Static dependency towards IVAHD clock domain"; 226 _ 2 mbz; 227 }; 228 229 register cm_l3_1_dynamicdep_restore addr(base, 0x2C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 230 _ 4 mbz; 231 windowsize 4 rw "Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 232 _ 11 mbz; 233 l4cfg_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L4CFG clock domain"; 234 _ 5 mbz; 235 l3_2_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3_2 clock domain"; 236 _ 1 mbz; 237 memif_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards MEMIF clock domain"; 238 abe_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards ABE clock domain"; 239 _ 3 mbz; 240 }; 241 242 register cm_l3_2_dynamicdep_restore addr(base, 0x30) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 243 _ 4 mbz; 244 windowsize 4 rw "Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 245 _ 5 mbz; 246 c2c_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards D2D clock domain"; 247 _ 3 mbz; 248 l4sec_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L4SEC clock domain"; 249 l4per_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L4PER clock domain"; 250 _ 2 mbz; 251 gfx_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards GFX clock domain"; 252 iss_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards ISS clock domain"; 253 dss_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards DSS clock domain"; 254 l3init_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3INIT clock domain"; 255 _ 1 mbz; 256 l3_1_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3_1 clock domain"; 257 _ 2 mbz; 258 ivahd_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards IVAHD clock domain"; 259 _ 1 mbz; 260 mpu_m3_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards CORTEXM3 clock domain"; 261 }; 262 263 register cm_c2c_dynamicdep_restore addr(base, 0x34) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 264 _ 4 mbz; 265 windowsize 4 rw "Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 266 _ 17 mbz; 267 l3_2_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3_2 clock domain"; 268 _ 1 mbz; 269 memif_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards MEMIF clock domain"; 270 _ 4 mbz; 271 }; 272 273 register cm_l4cfg_dynamicdep_restore addr(base, 0x38) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 274 _ 4 mbz; 275 windowsize 4 rw "Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 276 _ 4 mbz; 277 mpu_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards MPU clock domain"; 278 c2c_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards D2D clock domain"; 279 _ 1 rsvd; 280 alwoncore_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards ALWONCORE clock domain"; 281 l4wkup_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L4WKUP clock domain"; 282 _ 3 mbz; 283 sdma_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards SDMA clock domain"; 284 _ 1 mbz; 285 iss_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards ISS clock domain"; 286 dss_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards DSS clock domain"; 287 l3init_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3INIT clock domain"; 288 l3_2_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3_2 clock domain"; 289 l3_1_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3_1 clock domain"; 290 memif_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards MEMIF clock domain"; 291 _ 2 mbz; 292 dsp_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards DSP clock domain"; 293 _ 1 mbz; 294 }; 295 296 register cm_l4per_dynamicdep_restore addr(base, 0x3C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 297 _ 4 mbz; 298 windowsize 4 rw "Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 299 _ 9 mbz; 300 l4sec_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L4SEC clock domain"; 301 _ 5 mbz; 302 dss_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards DSS clock domain"; 303 l3init_dyndep 1 ro type(l4per_statdep_status) "Dynamic dependency towards L3INIT clock domain"; 304 _ 7 mbz; 305 }; 306 307 constants optfclken_dbclk_status width(1) "" { 308 OPTFCLKEN_DBCLK_0 = 0 "Optional functional clock is disabled"; 309 OPTFCLKEN_DBCLK_1 = 1 "Optional functional clock is enabled"; 310 }; 311 312 register cm_l4per_gpio2_clkctrl_restore addr(base, 0x40) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 313 _ 14 mbz; 314 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 315 _ 7 mbz; 316 optfclken_dbclk 1 rw type(optfclken_dbclk_status) "Optional functional clock control."; 317 _ 6 mbz; 318 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 319 }; 320 321 register cm_l4per_gpio3_clkctrl_restore addr(base, 0x44) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 322 _ 14 mbz; 323 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 324 _ 7 mbz; 325 optfclken_dbclk 1 rw type(optfclken_dbclk_status) "Optional functional clock control."; 326 _ 6 mbz; 327 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 328 }; 329 330 register cm_l4per_gpio4_clkctrl_restore addr(base, 0x48) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 331 _ 14 mbz; 332 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 333 _ 7 mbz; 334 optfclken_dbclk 1 rw type(optfclken_dbclk_status) "Optional functional clock control."; 335 _ 6 mbz; 336 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 337 }; 338 339 register cm_l4per_gpio5_clkctrl_restore addr(base, 0x4C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 340 _ 14 mbz; 341 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 342 _ 7 mbz; 343 optfclken_dbclk 1 rw type(optfclken_dbclk_status) "Optional functional clock control."; 344 _ 6 mbz; 345 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 346 }; 347 348 register cm_l4per_gpio6_clkctrl_restore addr(base, 0x50) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 349 _ 14 mbz; 350 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 351 _ 7 mbz; 352 optfclken_dbclk 1 rw type(optfclken_dbclk_status) "Optional functional clock control."; 353 _ 6 mbz; 354 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 355 }; 356 357 constants clksel_utmi_p2_status width(1) "" { 358 CLKSEL_UTMI_P2_0 = 0 "The functional clock is provided by the internal clock source"; 359 CLKSEL_UTMI_P2_1 = 1 "The functional clock is provided by an external PHY through an I/O pad."; 360 }; 361 362 constants stbyst_status width(1) "" { 363 STBYST_0_r = 0 "Module is functional (not in standby)"; 364 STBYST_1_r = 1 "Module is in standby"; 365 }; 366 367 constants sar_mode_status width(1) "" { 368 SAR_MODE_0 = 0 "SAR mode is disabled"; 369 SAR_MODE_1 = 1 "SAR mode is enabled"; 370 }; 371 372 constants modulemode_status3 width(2) "" { 373 MODULEMODE_0_9 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup)."; 374 MODULEMODE_1_r = 1 "Reserved"; 375 MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen."; 376 MODULEMODE_3_r_9 = 3 "Reserved"; 377 }; 378 379 register cm_l3init_hsusbhost_clkctrl_restore addr(base, 0x54) "Second address map for register CM_L3INIT_USB_HOST_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode." { 380 _ 6 mbz; 381 clksel_utmi_p2 1 rw type(clksel_utmi_p2_status) "Selects the source of the functional clock for UTMI Port2 on USB Host"; 382 clksel_utmi_p1 1 rw type(clksel_utmi_p2_status) "Selects the source of the functional clock for UTMI Por1 on USB Host"; 383 _ 5 mbz; 384 stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]"; 385 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 386 optfclken_func48mclk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: FUNC48MCLK"; 387 optfclken_hsic480m_p2_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: HSIC480M_P2_CLK"; 388 optfclken_hsic480m_p1_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: HSIC480M_P1_CLK"; 389 optfclken_hsic60m_p2_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: HSIC60M_P2_CLK"; 390 optfclken_hsic60m_p1_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: HSIC60M_P1_CLK"; 391 optfclken_utmi_p3_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: UTMI_P3_CLK"; 392 optfclken_utmi_p2_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: UTMI_P2_CLK when CLKSEL_UTMI_P2 is 0"; 393 optfclken_utmi_p1_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: UTMI_P1_CLK when CLKSEL_UTMI_P1 is 0"; 394 _ 3 mbz; 395 sar_mode 1 rw type(sar_mode_status) "SAR mode control for the module. Shall not be modify except if module is disabled."; 396 _ 2 mbz; 397 modulemode 2 rw type(modulemode_status3) "Control the way mandatory clocks are managed."; 398 }; 399 400 register cm_l3init_hsusbtll_clkctrl_restore addr(base, 0x58) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 401 _ 14 mbz; 402 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 403 _ 6 mbz; 404 optfclken_usb_ch1_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: USB_CH1_CLK"; 405 optfclken_usb_ch0_clk 1 rw type(optfclken_dbclk_status) "USB-HOST optional clock control: USB_CH0_CLK"; 406 _ 3 mbz; 407 sar_mode 1 rw type(sar_mode_status) "SAR mode control for the module. Shall not be modify except if module is disabled."; 408 _ 2 mbz; 409 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 410 }; 411 412 register cm_sdma_staticdep_restore addr(base, 0x5C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 413 _ 16 mbz; 414 l4wkup_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L4WKUP clock domain"; 415 l4sec_statdep 1 rw "Static dependency towards L4SEC clock domain"; 416 l4per_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L4PER clock domain"; 417 l4cfg_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L4CFG clock domain"; 418 _ 2 mbz; 419 iss_statdep 1 ro type(l4per_statdep_status) "Static dependency towards ISS clock domain"; 420 dss_statdep 1 rw type(l4per_statdep_status) "Static dependency towards DSS clock domain"; 421 l3init_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L3INIT clock domain"; 422 l3_2_statdep 1 ro type(l4per_statdep_status) "Static dependency towards L3_2 clock domain"; 423 l3_1_statdep 1 rw type(l4per_statdep_status) "Static dependency towards L3_1 clock domain"; 424 memif_statdep 1 rw type(l4per_statdep_status) "Static dependency towards MEMIF clock domain"; 425 abe_statdep 1 rw type(l4per_statdep_status) "Static dependency towards ABE clock domain"; 426 ivahd_statdep 1 rw type(l4per_statdep_status) "Static dependency towards IVAHD clock domain"; 427 _ 1 mbz; 428 mpu_m3_statdep 1 rw type(l4per_statdep_status) "Static dependency towards MPU_A3 clock domain"; 429 }; 430};