1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_restore_cm1.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_restore_cm1 msbfirst ( addr base ) "" { 29 30 31 constants clksel_l4_status width(1) "" { 32 CLKSEL_L4_0 = 0 "L4_CLK is L3_CLK divided by 1"; 33 CLKSEL_L4_1 = 1 "L4_CLK is L3_CLK divided by 2"; 34 }; 35 36 constants clksel_l3_status width(1) "" { 37 CLKSEL_L3_0 = 0 "L3_CLK is CORE_CLK divided by 1"; 38 CLKSEL_L3_1 = 1 "L3_CLK is CORE_CLK divided by 2"; 39 }; 40 41 constants clksel_core_status width(1) "" { 42 CLKSEL_CORE_0 = 0 "CORE_CLK is CORE_X2_CLK divided by 1"; 43 CLKSEL_CORE_1 = 1 "CORE_CLK is CORE_X2_CLK divided by 2"; 44 }; 45 46 register cm_clksel_core_restore addr(base, 0x0) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 47 _ 23 mbz; 48 clksel_l4 1 rw type(clksel_l4_status) "Selects L4 interconnect clock (L4_clk)"; 49 _ 3 mbz; 50 clksel_l3 1 rw type(clksel_l3_status) "Selects L3 interconnect clock (L3_clk)"; 51 _ 3 mbz; 52 clksel_core 1 rw type(clksel_core_status) "Selects CORE_CLK configuration"; 53 }; 54 55 constants st_dpll_clkout_status width(1) "" { 56 ST_DPLL_CLKOUT_0_r = 0 "The clock output is enabled"; 57 ST_DPLL_CLKOUT_1_r = 1 "The clock output is gated"; 58 }; 59 60 constants dpll_clkout_gate_ctrl_status width(1) "" { 61 DPLL_CLKOUT_GATE_CTRL_0 = 0 "Automatically gate this clock when there is no dependency for it"; 62 DPLL_CLKOUT_GATE_CTRL_1 = 1 "Force this clock to stay enabled even if there is no request"; 63 }; 64 65 constants dpll_clkout_div_status width(5) "" { 66 DPLL_CLKOUT_DIV_0 = 0 "Reserved"; 67 }; 68 69 register cm_div_m2_dpll_core_restore addr(base, 0x4) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 70 _ 22 mbz; 71 st_dpll_clkout 1 ro type(st_dpll_clkout_status) "DPLL CLKOUT status"; 72 dpll_clkout_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUT"; 73 _ 2 mbz; 74 dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect"; 75 dpll_clkout_div 5 rw type(dpll_clkout_div_status) "DPLL post-divider factor, M2, for internal clock generation (1 to 31); Divide value from 1 to 31."; 76 }; 77 78 register cm_div_m3_dpll_core_restore addr(base, 0x8) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 79 _ 22 mbz; 80 st_dpll_clkouthif 1 ro type(st_dpll_clkout_status) "DPLL CLKOUTHIF status"; 81 dpll_clkouthif_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of DPLL CLKOUTHIF"; 82 _ 2 mbz; 83 dpll_clkouthif_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect"; 84 dpll_clkouthif_div 5 rw type(dpll_clkout_div_status) "DPLL post-divider factor, M3, for internal clock generation (1 to 31);Divide value from 1 to 31."; 85 }; 86 87 constants hsdivider_clkout1_pwdn_status width(1) "" { 88 HSDIVIDER_CLKOUT1_PWDN_0 = 0 "Divider is powered up"; 89 HSDIVIDER_CLKOUT1_PWDN_1 = 1 "Divider is powered down"; 90 }; 91 92 constants st_hsdivider_clkout1_status width(1) "" { 93 ST_HSDIVIDER_CLKOUT1_0_r = 0 "The clock output is gated"; 94 ST_HSDIVIDER_CLKOUT1_1_r = 1 "The clock output is enabled"; 95 }; 96 97 register cm_div_m4_dpll_core_restore addr(base, 0xC) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 98 _ 19 mbz; 99 hsdivider_clkout1_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M4 divider and CLKOUT1 output. Power down should be enabled only when clock is first gated."; 100 _ 2 mbz; 101 st_hsdivider_clkout1 1 ro type(st_hsdivider_clkout1_status) "HSDIVIDER CLKOUT1 status"; 102 hsdivider_clkout1_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT1"; 103 _ 2 mbz; 104 hsdivider_clkout1_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect"; 105 hsdivider_clkout1_div 5 rw type(dpll_clkout_div_status) "DPLL M4 post-divider factor (1 to 31)."; 106 }; 107 108 register cm_div_m5_dpll_core_restore addr(base, 0x10) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 109 _ 19 mbz; 110 hsdivider_clkout2_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M5 divider and CLKOUT2 output. Power down should be enabled only when clock is first gated."; 111 _ 2 mbz; 112 st_hsdivider_clkout2 1 ro type(st_hsdivider_clkout1_status) "HSDIVIDER CLKOUT2 status"; 113 hsdivider_clkout2_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT2"; 114 _ 2 mbz; 115 hsdivider_clkout2_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect"; 116 hsdivider_clkout2_div 5 rw type(dpll_clkout_div_status) "DPLL M5 post-divider factor (1 to 31)."; 117 }; 118 119 register cm_div_m6_dpll_core_restore addr(base, 0x14) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 120 _ 19 mbz; 121 hsdivider_clkout3_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M6 divider and CLKOUT3 output. Power down should be enabled only when clock is first gated."; 122 _ 2 mbz; 123 st_hsdivider_clkout3 1 ro type(st_hsdivider_clkout1_status) "HSDIVIDER CLKOUT3 status"; 124 hsdivider_clkout3_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT3"; 125 _ 2 mbz; 126 hsdivider_clkout3_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect"; 127 hsdivider_clkout3_div 5 rw type(dpll_clkout_div_status) "DPLL M6 post-divider factor (1 to 31)."; 128 }; 129 130 register cm_div_m7_dpll_core_restore addr(base, 0x18) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 131 _ 19 mbz; 132 hsdivider_clkout4_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M7 divider and CLKOUT4 output. Power down should be enabled only when clock is first gated."; 133 _ 2 mbz; 134 st_hsdivider_clkout4 1 ro type(st_hsdivider_clkout1_status) "HSDIVIDER CLKOUT4 status"; 135 hsdivider_clkout4_gate_ctrl 1 rw type(dpll_clkout_gate_ctrl_status) "Control gating of HSDIVIDER CLKOUT4"; 136 _ 2 mbz; 137 hsdivider_clkout4_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect"; 138 hsdivider_clkout4_div 5 rw type(dpll_clkout_div_status) "DPLL M7 post-divider factor (1 to 31)."; 139 }; 140 141 constants dpll_clkouthif_clksel_status width(1) "" { 142 DPLL_CLKOUTHIF_CLKSEL_0 = 0 "CLKOUTHIF is generated from the DPLL oscillator (DCO)"; 143 DPLL_CLKOUTHIF_CLKSEL_1 = 1 "CLKOUTHIF is generated from CLKINPHIF"; 144 }; 145 146 constants dpll_mult_status width(11) "" { 147 DPLL_MULT_0 = 0 "Reserved"; 148 DPLL_MULT_1 = 1 "Reserved"; 149 }; 150 151 register cm_clksel_dpll_core_restore addr(base, 0x1C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 152 _ 8 mbz; 153 dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2"; 154 _ 2 mbz; 155 dpll_clkouthif_clksel 1 rw type(dpll_clkouthif_clksel_status) "Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL"; 156 _ 1 mbz; 157 dpll_mult 11 rw type(dpll_mult_status) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M)."; 158 _ 1 mbz; 159 dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."; 160 }; 161 162 register cm_ssc_deltamstep_dpll_core_restore addr(base, 0x20) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" { 163 _ 12 mbz; 164 deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part"; 165 }; 166 167 register cm_ssc_modfreqdiv_dpll_core_restore addr(base, 0x24) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" { 168 _ 21 mbz; 169 modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor"; 170 _ 1 mbz; 171 modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor"; 172 }; 173 174 constants dpll_ssc_downspread_status width(1) "" { 175 DPLL_SSC_DOWNSPREAD_0 = 0 "When SSC is enabled, clock frequency is spread on both sides of the programmed frequency"; 176 DPLL_SSC_DOWNSPREAD_1 = 1 "When SSC is enabled, clock frequency is spread only on the lower side of the programmed frequency"; 177 }; 178 179 constants dpll_ssc_ack_status width(1) "" { 180 DPLL_SSC_ACK_0_r = 0 "SSC has been turned off on PLL o/ps"; 181 DPLL_SSC_ACK_1_r = 1 "SSC has been turned on on PLL o/ps"; 182 }; 183 184 constants dpll_ssc_en_status width(1) "" { 185 DPLL_SSC_EN_0 = 0 "SSC disabled"; 186 DPLL_SSC_EN_1 = 1 "SSC enabled"; 187 }; 188 189 constants dpll_regm4xen_status width(1) "" { 190 DPLL_REGM4XEN_0_r = 0 "REGM4XEN mode of the DPLL is disabled"; 191 }; 192 193 constants dpll_lpmode_en_status width(1) "" { 194 DPLL_LPMODE_EN_0 = 0 "Low-power mode of the DPLL is disabled"; 195 DPLL_LPMODE_EN_1 = 1 "Low-power mode of the DPLL is enabled"; 196 }; 197 198 constants dpll_driftguard_en_status width(1) "" { 199 DPLL_DRIFTGUARD_EN_0 = 0 "DRIFTGUARD feature is disabled"; 200 DPLL_DRIFTGUARD_EN_1 = 1 "DRIFTGUARD feature is enabled"; 201 }; 202 203 constants dpll_en_status width(3) "" { 204 DPLL_EN_0 = 0 "Reserved"; 205 DPLL_EN_1 = 1 "Reserved"; 206 DPLL_EN_2 = 2 "Reserved"; 207 DPLL_EN_3 = 3 "Reserved"; 208 DPLL_EN_4 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode."; 209 DPLL_EN_5 = 5 "Put the DPLL in idle bypass low-power mode."; 210 DPLL_EN_6 = 6 "Put the DPLL in idle bypass fast-relock mode."; 211 DPLL_EN_7 = 7 "Enables the DPLL in lock mode"; 212 }; 213 214 register cm_clkmode_dpll_core_restore addr(base, 0x28) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 215 _ 17 mbz; 216 dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required"; 217 dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature"; 218 dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking"; 219 dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled."; 220 dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled."; 221 _ 1 mbz; 222 dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set."; 223 _ 5 mbz; 224 dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode."; 225 }; 226 227 constants gpmc_freq_update_status width(1) "" { 228 GPMC_FREQ_UPDATE_0 = 0 "GPMC is not put automatically into idle during frequency change operation."; 229 GPMC_FREQ_UPDATE_1 = 1 "GPMC is put automatically into idle during frequency change operation."; 230 }; 231 232 register cm_shadow_freq_config2_restore addr(base, 0x2C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 233 _ 24 mbz; 234 dpll_core_m5_div 5 rw type(dpll_en_status) "Shadow register forCM_DIV_M5_DPLL_CORE.HSDIVIDER_CLKOUT2_DIV. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1. Divide value from 1 to 31."; 235 clksel_l3 1 rw type(clksel_l3_status) "Shadow register forCM_CLKSEL_CORE.CLKSEL_L3. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1."; 236 clksel_core 1 rw type(clksel_core_status) "Shadow register forCM_CLKSEL_CORE.CLKSEL_CORE. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to 1 and GPMC_FREQ_UPDATE is set to 1."; 237 gpmc_freq_update 1 rw type(gpmc_freq_update_status) "Controls whether or not GPMC has to be put automatically into idle during the frequency change operation."; 238 }; 239 240 constants dll_reset_status width(1) "" { 241 DLL_RESET_0 = 0 "DLL is not reset during the frequency change hardware sequence"; 242 DLL_RESET_1 = 1 "DLL is reset automatically during the frequency change hardware sequence"; 243 }; 244 245 constants dll_override_status width(1) "" { 246 DLL_OVERRIDE_0 = 0 "Lock and code outputs are not overriden"; 247 DLL_OVERRIDE_1 = 1 "Lock output is overriden to 1 and code output is overriden with a value coming from control module."; 248 }; 249 250 register cm_shadow_freq_config1_restore addr(base, 0x30) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 251 _ 16 rsvd; 252 dpll_core_m2_div 5 rw type(dpll_en_status) "Shadow register forCM_DIV_M2_DPLL_CORE.DPLL_CLKOUT_DIV. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1. Divide value from 1 to 31."; 253 dpll_core_dpll_en 3 rw type(dpll_en_status) "Shadow register forCM_CLKMODE_DPLL_CORE.DPLL_EN. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1."; 254 _ 4 mbz; 255 dll_reset 1 rw type(dll_reset_status) "Specify if DLL should be reset or not during the frequency change hardware sequence."; 256 dll_override 1 rw type(dll_override_status) "Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to 1."; 257 _ 1 mbz; 258 freq_update 1 rw "Writing 1 indicates that a new configuration is available. It is automatically cleared by h/w after the configuration has been applied."; 259 }; 260 261 constants dpll_dcoclkldo_pwdn_status width(1) "" { 262 DPLL_DCOCLKLDO_PWDN_0 = 0 "Keep DCOCLKLDO powered even when all dividers in HSDIVIDER are powered down."; 263 DPLL_DCOCLKLDO_PWDN_1 = 1 "Automatically power down DCOCLKLDO when all o/ps of HSDIVIDER are powered down."; 264 }; 265 266 constants auto_dpll_mode_status width(3) "" { 267 AUTO_DPLL_MODE_0 = 0 "DPLL auto control disabled"; 268 AUTO_DPLL_MODE_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 269 AUTO_DPLL_MODE_2 = 2 "The DPLL is automatically put in fast-relock stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 270 AUTO_DPLL_MODE_3 = 3 "Reserved"; 271 AUTO_DPLL_MODE_4 = 4 "Reserved"; 272 AUTO_DPLL_MODE_5 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 273 AUTO_DPLL_MODE_6 = 6 "The DPLL is automatically put in idle bypass fast-relock mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 274 AUTO_DPLL_MODE_7 = 7 "Reserved"; 275 }; 276 277 register cm_autoidle_dpll_core_restore addr(base, 0x34) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 278 _ 27 mbz; 279 dpll_dcoclkldo_pwdn 1 rw type(dpll_dcoclkldo_pwdn_status) "Allows powering down the DCOCLKLDO o/p of DPLL if all dividers in HSDIVIDER are powered down. PRCM takes care of reenabling this path for either restarting HSDIVIDER o/p or entering bypass mode."; 280 _ 1 mbz; 281 auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control."; 282 }; 283 284 constants clkactivity_mpu_dpll_clk_status width(1) "" { 285 CLKACTIVITY_MPU_DPLL_CLK_0_r = 0 "Corresponding clock is definitely gated"; 286 CLKACTIVITY_MPU_DPLL_CLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing"; 287 }; 288 289 constants clktrctrl_status width(2) "" { 290 CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 291 CLKTRCTRL_1_r = 1 "Reserved"; 292 CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 293 CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 294 }; 295 296 register cm_mpu_clkstctrl_restore addr(base, 0x38) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 297 _ 23 mbz; 298 clkactivity_mpu_dpll_clk 1 ro type(clkactivity_mpu_dpll_clk_status) "This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive]"; 299 _ 6 mbz; 300 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the MPU clock domain."; 301 }; 302 303 constants idlest_status width(2) "" { 304 IDLEST_3_r = 3 "Module is disabled"; 305 IDLEST_2_r = 2 "Module is in Idle"; 306 IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 307 IDLEST_0_r = 0 "Module is fully functional"; 308 }; 309 310 constants modulemode_status width(2) "" { 311 MODULEMODE_0 = 0 "Module is disabled by software. OCP configuration port is not accessible."; 312 MODULEMODE_1 = 1 "Module is managed automatically by hadware along with CM1 and EMU domain. OCP configuration port is accessible only when EMU domain is on."; 313 MODULEMODE_2_r = 2 "Reserved"; 314 MODULEMODE_3_r = 3 "Reserved"; 315 }; 316 317 register cm_cm1_profiling_clkctrl_restore addr(base, 0x3C) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" { 318 _ 14 mbz; 319 idlest 2 ro type(idlest_status) "Module idle status"; 320 _ 14 mbz; 321 modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed."; 322 }; 323 324 register cm_dyn_dep_prescal_restore addr(base, 0x40) "Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." { 325 _ 26 mbz; 326 prescal 6 rw "Time unit is equal to (PRESCAL + 1) L4 clock cycles."; 327 }; 328};