1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_mpu_cm1.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_mpu_cm1 msbfirst ( addr base ) "" { 29 30 31 constants clkactivity_mpu_dpll_clk_status width(1) "" { 32 CLKACTIVITY_MPU_DPLL_CLK_0_r = 0 "Corresponding clock is definitely gated"; 33 CLKACTIVITY_MPU_DPLL_CLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing"; 34 }; 35 36 constants clktrctrl_status width(2) "" { 37 CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur."; 38 CLKTRCTRL_1_r = 1 "Reserved"; 39 CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain."; 40 CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions."; 41 }; 42 43 register cm_mpu_clkstctrl addr(base, 0x0) "This register enables the MPU domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." { 44 _ 23 mbz; 45 clkactivity_mpu_dpll_clk 1 ro type(clkactivity_mpu_dpll_clk_status) "This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive]"; 46 _ 6 mbz; 47 clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the MPU clock domain."; 48 }; 49 50 constants c2c_statdep_status width(1) "" { 51 C2C_STATDEP_0_r = 0 "Dependency is disabled"; 52 }; 53 54 constants l4wkup_statdep_status width(1) "" { 55 L4WKUP_STATDEP_0 = 0 "Dependency is disabled"; 56 L4WKUP_STATDEP_1 = 1 "Dependency is enabled"; 57 }; 58 59 register cm_mpu_staticdep addr(base, 0x4) "This register controls the static domain dependencies from MPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." { 60 _ 13 mbz; 61 c2c_statdep 1 ro type(c2c_statdep_status) "Static dependency towards C2C clock domain"; 62 _ 1 mbz; 63 alwoncore_statdep 1 ro type(c2c_statdep_status) "Static dependency towards ALWONCORE clock domain"; 64 l4wkup_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4WKUP clock domain"; 65 l4sec_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4SEC clock domain"; 66 l4per_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4PER clock domain"; 67 l4cfg_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L4CFG clock domain"; 68 sdma_statdep 1 ro type(c2c_statdep_status) "Static dependency towards SDMA clock domain"; 69 sgx_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards SGX clock domain"; 70 iss_statdep 1 ro type(c2c_statdep_status) "Static dependency towards ISS clock domain"; 71 dss_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards DSS clock domain"; 72 l3init_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3INIT clock domain"; 73 l3_2_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_2 clock domain"; 74 l3_1_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards L3_1 clock domain"; 75 memif_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MEMIF clock domain"; 76 abe_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards ABE clock domain"; 77 ivahd_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards IVAHD clock domain"; 78 dsp_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards DSP clock domain"; 79 mpu_m3_statdep 1 rw type(l4wkup_statdep_status) "Static dependency towards MPU_A3 clock domain"; 80 }; 81 82 register cm_mpu_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." { 83 _ 4 mbz; 84 windowsize 4 rw "Size of sliding window used to monitor INTRCONN interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register."; 85 _ 18 mbz; 86 l3_1_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards L3_1 clock domain"; 87 memif_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards MEMIF clock domain"; 88 abe_dyndep 1 ro type(l4wkup_statdep_status) "Dynamic dependency towards ABE clock domain"; 89 _ 3 mbz; 90 }; 91 92 constants clksel_abe_div_mode_status width(1) "" { 93 CLKSEL_ABE_DIV_MODE_0 = 0 "MPU DPLL clock divided by 4"; 94 CLKSEL_ABE_DIV_MODE_1 = 1 "MPU DPLL clock divided by 8"; 95 }; 96 97 constants clksel_emif_div_mode_status width(1) "" { 98 CLKSEL_EMIF_DIV_MODE_0 = 0 "MPU DPLL clock divided by 2"; 99 CLKSEL_EMIF_DIV_MODE_1 = 1 "MPU DPLL clock divided by 4"; 100 }; 101 102 constants stbyst_status width(1) "" { 103 STBYST_0_r = 0 "Module is functional (not in standby)"; 104 STBYST_1_r = 1 "Module is in standby"; 105 }; 106 107 constants idlest_status width(2) "" { 108 IDLEST_0_r = 0 "Module is fully functional, including INTRCONN"; 109 IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion"; 110 IDLEST_2_r = 2 "Module is in Idle mode (only INTRCONN part). It is functional if using separate functional clock"; 111 IDLEST_3_r = 3 "Module is disabled and cannot be accessed"; 112 }; 113 114 constants modulemode_status width(2) "" { 115 MODULEMODE_1_r = 1 "Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. Module clocks may be gated according to the clock domain state."; 116 }; 117 118 register cm_mpu_mpu_clkctrl addr(base, 0x20) "This register manages the MPU clocks." { 119 _ 6 mbz; 120 clksel_abe_div_mode 1 rw type(clksel_abe_div_mode_status) "Selects the ratio for MPU-ABE async bridge versus MPU DPLL clock."; 121 clksel_emif_div_mode 1 rw type(clksel_emif_div_mode_status) "Selects the ratio for memory adapter clock (MA_EOCP_ICLK) versus MPU DPLL clock."; 122 _ 5 mbz; 123 stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]"; 124 idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]"; 125 _ 14 mbz; 126 modulemode 2 ro type(modulemode_status) "Control the way mandatory clocks are managed."; 127 }; 128};